2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "glsl/glsl_parser_extras.h"
27 #include "glsl/nir/glsl_to_nir.h"
28 #include "program/prog_to_nir.h"
31 remap_vs_attrs(nir_block
*block
, void *closure
)
33 GLbitfield64 inputs_read
= *((GLbitfield64
*) closure
);
35 nir_foreach_instr(block
, instr
) {
36 if (instr
->type
!= nir_instr_type_intrinsic
)
39 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
41 /* We set EmitNoIndirect for VS inputs, so there are no indirects. */
42 assert(intrin
->intrinsic
!= nir_intrinsic_load_input_indirect
);
44 if (intrin
->intrinsic
== nir_intrinsic_load_input
) {
45 /* Attributes come in a contiguous block, ordered by their
46 * gl_vert_attrib value. That means we can compute the slot
47 * number for an attribute by masking out the enabled attributes
48 * before it and counting the bits.
50 int attr
= intrin
->const_index
[0];
51 int slot
= _mesa_bitcount_64(inputs_read
& BITFIELD64_MASK(attr
));
52 intrin
->const_index
[0] = 4 * slot
;
59 brw_nir_lower_inputs(nir_shader
*nir
, bool is_scalar
)
62 case MESA_SHADER_VERTEX
:
63 /* For now, leave the vec4 backend doing the old method. */
65 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
,
70 /* Start with the location of the variable's base. */
71 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
72 var
->data
.driver_location
= var
->data
.location
;
75 /* Now use nir_lower_io to walk dereference chains. Attribute arrays
76 * are loaded as one vec4 per element (or matrix column), so we use
77 * type_size_vec4 here.
79 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
);
81 /* Finally, translate VERT_ATTRIB_* values into the actual registers.
83 * Note that we can use nir->info.inputs_read instead of key->inputs_read
84 * since the two are identical aside from Gen4-5 edge flag differences.
86 GLbitfield64 inputs_read
= nir
->info
.inputs_read
;
87 nir_foreach_overload(nir
, overload
) {
89 nir_foreach_block(overload
->impl
, remap_vs_attrs
, &inputs_read
);
93 case MESA_SHADER_GEOMETRY
:
94 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
95 var
->data
.driver_location
= var
->data
.location
;
98 case MESA_SHADER_FRAGMENT
:
100 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
,
103 case MESA_SHADER_COMPUTE
:
104 /* Compute shaders have no inputs. */
105 assert(exec_list_is_empty(&nir
->inputs
));
108 unreachable("unsupported shader stage");
113 brw_nir_lower_outputs(nir_shader
*nir
, bool is_scalar
)
115 switch (nir
->stage
) {
116 case MESA_SHADER_VERTEX
:
117 case MESA_SHADER_GEOMETRY
:
119 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
122 nir_foreach_variable(var
, &nir
->outputs
)
123 var
->data
.driver_location
= var
->data
.location
;
126 case MESA_SHADER_FRAGMENT
:
127 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
130 case MESA_SHADER_COMPUTE
:
131 /* Compute shaders have no outputs. */
132 assert(exec_list_is_empty(&nir
->outputs
));
135 unreachable("unsupported shader stage");
140 nir_optimize(nir_shader
*nir
, bool is_scalar
)
145 nir_lower_vars_to_ssa(nir
);
146 nir_validate_shader(nir
);
149 nir_lower_alu_to_scalar(nir
);
150 nir_validate_shader(nir
);
153 progress
|= nir_copy_prop(nir
);
154 nir_validate_shader(nir
);
157 nir_lower_phis_to_scalar(nir
);
158 nir_validate_shader(nir
);
161 progress
|= nir_copy_prop(nir
);
162 nir_validate_shader(nir
);
163 progress
|= nir_opt_dce(nir
);
164 nir_validate_shader(nir
);
165 progress
|= nir_opt_cse(nir
);
166 nir_validate_shader(nir
);
167 progress
|= nir_opt_peephole_select(nir
);
168 nir_validate_shader(nir
);
169 progress
|= nir_opt_algebraic(nir
);
170 nir_validate_shader(nir
);
171 progress
|= nir_opt_constant_folding(nir
);
172 nir_validate_shader(nir
);
173 progress
|= nir_opt_dead_cf(nir
);
174 nir_validate_shader(nir
);
175 progress
|= nir_opt_remove_phis(nir
);
176 nir_validate_shader(nir
);
177 progress
|= nir_opt_undef(nir
);
178 nir_validate_shader(nir
);
183 brw_create_nir(struct brw_context
*brw
,
184 const struct gl_shader_program
*shader_prog
,
185 const struct gl_program
*prog
,
186 gl_shader_stage stage
,
189 struct gl_context
*ctx
= &brw
->ctx
;
190 const nir_shader_compiler_options
*options
=
191 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
192 static const nir_lower_tex_options tex_options
= {
195 bool debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
198 /* First, lower the GLSL IR or Mesa IR to NIR */
200 nir
= glsl_to_nir(shader_prog
, stage
, options
);
202 nir
= prog_to_nir(prog
, options
);
203 nir_convert_to_ssa(nir
); /* turn registers into SSA */
205 nir_validate_shader(nir
);
207 if (stage
== MESA_SHADER_GEOMETRY
) {
208 nir_lower_gs_intrinsics(nir
);
209 nir_validate_shader(nir
);
212 nir_lower_global_vars_to_local(nir
);
213 nir_validate_shader(nir
);
215 nir_lower_tex(nir
, &tex_options
);
216 nir_validate_shader(nir
);
218 nir_normalize_cubemap_coords(nir
);
219 nir_validate_shader(nir
);
221 nir_split_var_copies(nir
);
222 nir_validate_shader(nir
);
224 nir_optimize(nir
, is_scalar
);
226 /* Lower a bunch of stuff */
227 nir_lower_var_copies(nir
);
228 nir_validate_shader(nir
);
230 /* Get rid of split copies */
231 nir_optimize(nir
, is_scalar
);
233 brw_nir_lower_inputs(nir
, is_scalar
);
234 brw_nir_lower_outputs(nir
, is_scalar
);
235 nir_assign_var_locations(&nir
->uniforms
,
237 is_scalar
? type_size_scalar
: type_size_vec4
);
238 nir_lower_io(nir
, -1, is_scalar
? type_size_scalar
: type_size_vec4
);
239 nir_validate_shader(nir
);
241 nir_remove_dead_variables(nir
);
242 nir_validate_shader(nir
);
245 nir_lower_samplers(nir
, shader_prog
);
246 nir_validate_shader(nir
);
249 nir_lower_system_values(nir
);
250 nir_validate_shader(nir
);
252 nir_lower_atomics(nir
);
253 nir_validate_shader(nir
);
255 nir_optimize(nir
, is_scalar
);
258 /* Try and fuse multiply-adds */
259 nir_opt_peephole_ffma(nir
);
260 nir_validate_shader(nir
);
263 nir_opt_algebraic_late(nir
);
264 nir_validate_shader(nir
);
266 nir_lower_locals_to_regs(nir
);
267 nir_validate_shader(nir
);
269 nir_lower_to_source_mods(nir
);
270 nir_validate_shader(nir
);
272 nir_validate_shader(nir
);
274 nir_validate_shader(nir
);
276 if (unlikely(debug_enabled
)) {
277 /* Re-index SSA defs so we print more sensible numbers. */
278 nir_foreach_overload(nir
, overload
) {
280 nir_index_ssa_defs(overload
->impl
);
283 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
284 _mesa_shader_stage_to_string(stage
));
285 nir_print_shader(nir
, stderr
);
288 nir_convert_from_ssa(nir
, true);
289 nir_validate_shader(nir
);
292 nir_move_vec_src_uses_to_dest(nir
);
293 nir_validate_shader(nir
);
295 nir_lower_vec_to_movs(nir
);
296 nir_validate_shader(nir
);
299 /* This is the last pass we run before we start emitting stuff. It
300 * determines when we need to insert boolean resolves on Gen <= 5. We
301 * run it last because it stashes data in instr->pass_flags and we don't
302 * want that to be squashed by other NIR passes.
305 brw_nir_analyze_boolean_resolves(nir
);
309 if (unlikely(debug_enabled
)) {
310 fprintf(stderr
, "NIR (final form) for %s shader:\n",
311 _mesa_shader_stage_to_string(stage
));
312 nir_print_shader(nir
, stderr
);
319 brw_type_for_nir_type(nir_alu_type type
)
322 case nir_type_unsigned
:
323 return BRW_REGISTER_TYPE_UD
;
326 return BRW_REGISTER_TYPE_D
;
328 return BRW_REGISTER_TYPE_F
;
330 unreachable("unknown type");
333 return BRW_REGISTER_TYPE_F
;
336 /* Returns the glsl_base_type corresponding to a nir_alu_type.
337 * This is used by both brw_vec4_nir and brw_fs_nir.
340 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
344 return GLSL_TYPE_FLOAT
;
347 return GLSL_TYPE_INT
;
349 case nir_type_unsigned
:
350 return GLSL_TYPE_UINT
;
353 unreachable("bad type");