src/mesa/drivers/dri/i965/brw_nir.h

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include "brw_context.h"
  27 #include "brw_reg.h"
  28 #include "brw_shader.h"
  29 #include "compiler/nir/nir.h"
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 static inline int
  36 type_size_scalar_bytes(const struct glsl_type *type)
  37 {
  38    return type_size_scalar(type) * 4;
  39 }
  40
  41 static inline int
  42 type_size_vec4_bytes(const struct glsl_type *type)
  43 {
  44    return type_size_vec4(type) * 16;
  45 }
  46
  47 /* Flags set in the instr->pass_flags field by i965 analysis passes */
  48 enum {
  49    BRW_NIR_NON_BOOLEAN           = 0x0,
  50
  51    /* Indicates that the given instruction's destination is a boolean
  52     * value but that it needs to be resolved before it can be used.
  53     * On Gen <= 5, CMP instructions return a 32-bit value where the bottom
  54     * bit represents the actual true/false value of the compare and the top
  55     * 31 bits are undefined.  In order to use this value, we have to do a
  56     * "resolve" operation by replacing the value of the CMP with -(x & 1)
  57     * to sign-extend the bottom bit to 0/~0.
  58     */
  59    BRW_NIR_BOOLEAN_NEEDS_RESOLVE = 0x1,
  60
  61    /* Indicates that the given instruction's destination is a boolean
  62     * value that has intentionally been left unresolved.  Not all boolean
  63     * values need to be resolved immediately.  For instance, if we have
  64     *
  65     *    CMP r1 r2 r3
  66     *    CMP r4 r5 r6
  67     *    AND r7 r1 r4
  68     *
  69     * We don't have to resolve the result of the two CMP instructions
  70     * immediately because the AND still does an AND of the bottom bits.
  71     * Instead, we can save ourselves instructions by delaying the resolve
  72     * until after the AND.  The result of the two CMP instructions is left
  73     * as BRW_NIR_BOOLEAN_UNRESOLVED.
  74     */
  75    BRW_NIR_BOOLEAN_UNRESOLVED    = 0x2,
  76
  77    /* Indicates a that the given instruction's destination is a boolean
  78     * value that does not need a resolve.  For instance, if you AND two
  79     * values that are BRW_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both
  80     * values will be 0/~0 before we get them and the result of the AND is
  81     * also guaranteed to be 0/~0 and does not need a resolve.
  82     */
  83    BRW_NIR_BOOLEAN_NO_RESOLVE    = 0x3,
  84
  85    /* A mask to mask the boolean status values off of instr->pass_flags */
  86    BRW_NIR_BOOLEAN_MASK          = 0x3,
  87 };
  88
  89 void brw_nir_analyze_boolean_resolves(nir_shader *nir);
  90
  91 nir_shader *brw_preprocess_nir(const struct brw_compiler *compiler,
  92                                nir_shader *nir);
  93
  94 bool brw_nir_lower_intrinsics(nir_shader *nir,
  95                               struct brw_stage_prog_data *prog_data);
  96 void brw_nir_lower_vs_inputs(nir_shader *nir,
  97                              const struct brw_device_info *devinfo,
  98                              bool is_scalar,
  99                              bool use_legacy_snorm_formula,
 100                              const uint8_t *vs_attrib_wa_flags);
 101 void brw_nir_lower_vue_inputs(nir_shader *nir, bool is_scalar,
 102                               const struct brw_vue_map *vue_map);
 103 void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue);
 104 void brw_nir_lower_fs_inputs(nir_shader *nir);
 105 void brw_nir_lower_vue_outputs(nir_shader *nir, bool is_scalar);
 106 void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue);
 107 void brw_nir_lower_fs_outputs(nir_shader *nir);
 108 void brw_nir_lower_cs_shared(nir_shader *nir);
 109
 110 nir_shader *brw_postprocess_nir(nir_shader *nir,
 111                                 const struct brw_device_info *devinfo,
 112                                 bool is_scalar);
 113
 114 bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
 115                                          bool use_legacy_snorm_formula,
 116                                          const uint8_t *attrib_wa_flags);
 117
 118 bool brw_nir_apply_trig_workarounds(nir_shader *nir);
 119
 120 void brw_nir_apply_tcs_quads_workaround(nir_shader *nir);
 121
 122 nir_shader *brw_nir_apply_sampler_key(nir_shader *nir,
 123                                       const struct brw_device_info *devinfo,
 124                                       const struct brw_sampler_prog_key_data *key,
 125                                       bool is_scalar);
 126
 127 enum brw_reg_type brw_type_for_nir_type(nir_alu_type type);
 128
 129 enum glsl_base_type brw_glsl_base_type_for_nir_type(nir_alu_type type);
 130
 131 void brw_nir_setup_glsl_uniforms(nir_shader *shader,
 132                                  struct gl_shader_program *shader_prog,
 133                                  const struct gl_program *prog,
 134                                  struct brw_stage_prog_data *stage_prog_data,
 135                                  bool is_scalar);
 136
 137 void brw_nir_setup_arb_uniforms(nir_shader *shader, struct gl_program *prog,
 138                                 struct brw_stage_prog_data *stage_prog_data);
 139
 140 bool brw_nir_opt_peephole_ffma(nir_shader *shader);
 141
 142 #define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
 143 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
 144 #define BRW_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1
 145 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
 146
 147 #ifdef __cplusplus
 148 }
 149 #endif