2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_context.h"
28 #include "brw_shader.h"
29 #include "compiler/nir/nir.h"
36 type_size_scalar_bytes(const struct glsl_type
*type
)
38 return type_size_scalar(type
) * 4;
42 type_size_vec4_bytes(const struct glsl_type
*type
)
44 return type_size_vec4(type
) * 16;
47 /* Flags set in the instr->pass_flags field by i965 analysis passes */
49 BRW_NIR_NON_BOOLEAN
= 0x0,
51 /* Indicates that the given instruction's destination is a boolean
52 * value but that it needs to be resolved before it can be used.
53 * On Gen <= 5, CMP instructions return a 32-bit value where the bottom
54 * bit represents the actual true/false value of the compare and the top
55 * 31 bits are undefined. In order to use this value, we have to do a
56 * "resolve" operation by replacing the value of the CMP with -(x & 1)
57 * to sign-extend the bottom bit to 0/~0.
59 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
= 0x1,
61 /* Indicates that the given instruction's destination is a boolean
62 * value that has intentionally been left unresolved. Not all boolean
63 * values need to be resolved immediately. For instance, if we have
69 * We don't have to resolve the result of the two CMP instructions
70 * immediately because the AND still does an AND of the bottom bits.
71 * Instead, we can save ourselves instructions by delaying the resolve
72 * until after the AND. The result of the two CMP instructions is left
73 * as BRW_NIR_BOOLEAN_UNRESOLVED.
75 BRW_NIR_BOOLEAN_UNRESOLVED
= 0x2,
77 /* Indicates a that the given instruction's destination is a boolean
78 * value that does not need a resolve. For instance, if you AND two
79 * values that are BRW_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both
80 * values will be 0/~0 before we get them and the result of the AND is
81 * also guaranteed to be 0/~0 and does not need a resolve.
83 BRW_NIR_BOOLEAN_NO_RESOLVE
= 0x3,
85 /* A mask to mask the boolean status values off of instr->pass_flags */
86 BRW_NIR_BOOLEAN_MASK
= 0x3,
89 void brw_nir_analyze_boolean_resolves(nir_shader
*nir
);
91 nir_shader
*brw_create_nir(struct brw_context
*brw
,
92 const struct gl_shader_program
*shader_prog
,
93 const struct gl_program
*prog
,
94 gl_shader_stage stage
,
97 nir_shader
*brw_preprocess_nir(const struct brw_compiler
*compiler
,
100 void brw_nir_lower_vs_inputs(nir_shader
*nir
,
101 const struct brw_device_info
*devinfo
,
103 bool use_legacy_snorm_formula
,
104 const uint8_t *vs_attrib_wa_flags
);
105 void brw_nir_lower_vue_inputs(nir_shader
*nir
, bool is_scalar
,
106 const struct brw_vue_map
*vue_map
);
107 void brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue
);
108 void brw_nir_lower_fs_inputs(nir_shader
*nir
);
109 void brw_nir_lower_vue_outputs(nir_shader
*nir
, bool is_scalar
);
110 void brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue
);
111 void brw_nir_lower_fs_outputs(nir_shader
*nir
);
112 void brw_nir_lower_cs_shared(nir_shader
*nir
);
114 nir_shader
*brw_postprocess_nir(nir_shader
*nir
,
115 const struct brw_device_info
*devinfo
,
118 bool brw_nir_apply_attribute_workarounds(nir_shader
*nir
,
119 bool use_legacy_snorm_formula
,
120 const uint8_t *attrib_wa_flags
);
122 bool brw_nir_apply_trig_workarounds(nir_shader
*nir
);
124 nir_shader
*brw_nir_apply_sampler_key(nir_shader
*nir
,
125 const struct brw_device_info
*devinfo
,
126 const struct brw_sampler_prog_key_data
*key
,
129 enum brw_reg_type
brw_type_for_nir_type(nir_alu_type type
);
131 enum glsl_base_type
brw_glsl_base_type_for_nir_type(nir_alu_type type
);
133 void brw_nir_setup_glsl_uniforms(nir_shader
*shader
,
134 struct gl_shader_program
*shader_prog
,
135 const struct gl_program
*prog
,
136 struct brw_stage_prog_data
*stage_prog_data
,
139 void brw_nir_setup_arb_uniforms(nir_shader
*shader
, struct gl_program
*prog
,
140 struct brw_stage_prog_data
*stage_prog_data
);
142 bool brw_nir_opt_peephole_ffma(nir_shader
*shader
);