i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_performance_query_metrics.h
1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef BRW_PERFORMANCE_QUERY_METRICS_H
25 #define BRW_PERFORMANCE_QUERY_METRICS_H
26
27 #include <stdint.h>
28
29 struct brw_pipeline_stat
30 {
31 uint32_t reg;
32 uint32_t numerator;
33 uint32_t denominator;
34 };
35
36 struct brw_perf_query_counter
37 {
38 const char *name;
39 const char *desc;
40 GLenum type;
41 GLenum data_type;
42 uint64_t raw_max;
43 size_t offset;
44 size_t size;
45
46 union {
47 uint64_t (*oa_counter_read_uint64)(struct brw_context *brw,
48 const struct brw_perf_query_info *query,
49 uint64_t *accumulator);
50 float (*oa_counter_read_float)(struct brw_context *brw,
51 const struct brw_perf_query_info *query,
52 uint64_t *accumulator);
53 struct brw_pipeline_stat pipeline_stat;
54 };
55 };
56
57 #endif /* BRW_PERFORMANCE_QUERY_METRICS_H */