2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
25 #include "brw_defines.h"
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
30 * According to the latest documentation, any PIPE_CONTROL with the
31 * "Command Streamer Stall" bit set must also have another bit set,
32 * with five different options:
34 * - Render Target Cache Flush
36 * - Stall at Pixel Scoreboard
37 * - Post-Sync Operation
41 * I chose "Stall at Pixel Scoreboard" since we've used it effectively
42 * in the past, but the choice is fairly arbitrary.
45 gen8_add_cs_stall_workaround_bits(uint32_t *flags
)
47 uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
48 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
49 PIPE_CONTROL_WRITE_IMMEDIATE
|
50 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
51 PIPE_CONTROL_WRITE_TIMESTAMP
|
52 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
53 PIPE_CONTROL_DEPTH_STALL
|
54 PIPE_CONTROL_DATA_CACHE_FLUSH
;
56 /* If we're doing a CS stall, and don't already have one of the
57 * workaround bits set, add "Stall at Pixel Scoreboard."
59 if ((*flags
& PIPE_CONTROL_CS_STALL
) != 0 && (*flags
& wa_bits
) == 0)
60 *flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
63 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
65 * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
66 * only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
68 * Note that the kernel does CS stalls between batches, so we only need
69 * to count them within a batch.
72 gen7_cs_stall_every_four_pipe_controls(struct brw_context
*brw
, uint32_t flags
)
74 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
76 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
77 if (flags
& PIPE_CONTROL_CS_STALL
) {
78 /* If we're doing a CS stall, reset the counter and carry on. */
79 brw
->pipe_controls_since_last_cs_stall
= 0;
83 /* If this is the fourth pipe control without a CS stall, do one now. */
84 if (++brw
->pipe_controls_since_last_cs_stall
== 4) {
85 brw
->pipe_controls_since_last_cs_stall
= 0;
86 return PIPE_CONTROL_CS_STALL
;
93 brw_emit_pipe_control(struct brw_context
*brw
, uint32_t flags
,
94 struct brw_bo
*bo
, uint32_t offset
, uint64_t imm
)
96 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
98 if (devinfo
->gen
>= 8) {
99 if (devinfo
->gen
== 8)
100 gen8_add_cs_stall_workaround_bits(&flags
);
102 if (devinfo
->gen
== 9 &&
103 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
104 /* Hardware workaround: SKL
106 * Emit Pipe Control with all bits set to zero before emitting
107 * a Pipe Control with VF Cache Invalidate set.
109 brw_emit_pipe_control_flush(brw
, 0);
113 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
116 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
122 OUT_BATCH(imm
>> 32);
124 } else if (devinfo
->gen
>= 6) {
125 if (devinfo
->gen
== 6 &&
126 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
127 /* Hardware workaround: SNB B-Spec says:
129 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
130 * Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
133 brw_emit_post_sync_nonzero_flush(brw
);
136 flags
|= gen7_cs_stall_every_four_pipe_controls(brw
, flags
);
138 /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
139 * on later platforms. We always use PPGTT on Gen7+.
141 unsigned gen6_gtt
= devinfo
->gen
== 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE
: 0;
144 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
147 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, gen6_gtt
| offset
);
152 OUT_BATCH(imm
>> 32);
156 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
158 OUT_RELOC(bo
, RELOC_WRITE
, PIPE_CONTROL_GLOBAL_GTT_WRITE
| offset
);
163 OUT_BATCH(imm
>> 32);
169 * Emit a PIPE_CONTROL with various flushing flags.
171 * The caller is responsible for deciding what flags are appropriate for the
175 brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
)
177 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
179 if (devinfo
->gen
>= 6 &&
180 (flags
& PIPE_CONTROL_CACHE_FLUSH_BITS
) &&
181 (flags
& PIPE_CONTROL_CACHE_INVALIDATE_BITS
)) {
182 /* A pipe control command with flush and invalidate bits set
183 * simultaneously is an inherently racy operation on Gen6+ if the
184 * contents of the flushed caches were intended to become visible from
185 * any of the invalidated caches. Split it in two PIPE_CONTROLs, the
186 * first one should stall the pipeline to make sure that the flushed R/W
187 * caches are coherent with memory once the specified R/O caches are
188 * invalidated. On pre-Gen6 hardware the (implicit) R/O cache
189 * invalidation seems to happen at the bottom of the pipeline together
190 * with any write cache flush, so this shouldn't be a concern. In order
191 * to ensure a full stall, we do an end-of-pipe sync.
193 brw_emit_end_of_pipe_sync(brw
, (flags
& PIPE_CONTROL_CACHE_FLUSH_BITS
));
194 flags
&= ~(PIPE_CONTROL_CACHE_FLUSH_BITS
| PIPE_CONTROL_CS_STALL
);
197 brw_emit_pipe_control(brw
, flags
, NULL
, 0, 0);
201 * Emit a PIPE_CONTROL that writes to a buffer object.
203 * \p flags should contain one of the following items:
204 * - PIPE_CONTROL_WRITE_IMMEDIATE
205 * - PIPE_CONTROL_WRITE_TIMESTAMP
206 * - PIPE_CONTROL_WRITE_DEPTH_COUNT
209 brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
210 struct brw_bo
*bo
, uint32_t offset
,
213 brw_emit_pipe_control(brw
, flags
, bo
, offset
, imm
);
217 * Restriction [DevSNB, DevIVB]:
219 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
220 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
221 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
222 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
223 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
224 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
225 * unless SW can otherwise guarantee that the pipeline from WM onwards is
226 * already flushed (e.g., via a preceding MI_FLUSH).
229 brw_emit_depth_stall_flushes(struct brw_context
*brw
)
231 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
233 assert(devinfo
->gen
>= 6);
235 /* Starting on BDW, these pipe controls are unnecessary.
237 * WM HW will internally manage the draining pipe and flushing of the caches
238 * when this command is issued. The PIPE_CONTROL restrictions are removed.
240 if (devinfo
->gen
>= 8)
243 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
244 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
245 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
249 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
250 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
251 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
252 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
253 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
254 * to be sent before any combination of VS associated 3DSTATE."
257 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
259 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
261 assert(devinfo
->gen
== 7);
262 brw_emit_pipe_control_write(brw
,
263 PIPE_CONTROL_WRITE_IMMEDIATE
264 | PIPE_CONTROL_DEPTH_STALL
,
265 brw
->workaround_bo
, 0, 0);
270 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
273 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
275 brw_emit_pipe_control_write(brw
,
276 PIPE_CONTROL_CS_STALL
277 | PIPE_CONTROL_WRITE_IMMEDIATE
,
278 brw
->workaround_bo
, 0, 0);
282 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
283 * implementing two workarounds on gen6. From section 1.4.7.1
284 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
286 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
287 * produced by non-pipelined state commands), software needs to first
288 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
291 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
292 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
294 * And the workaround for these two requires this workaround first:
296 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
297 * BEFORE the pipe-control with a post-sync op and no write-cache
300 * And this last workaround is tricky because of the requirements on
301 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
304 * "1 of the following must also be set:
305 * - Render Target Cache Flush Enable ([12] of DW1)
306 * - Depth Cache Flush Enable ([0] of DW1)
307 * - Stall at Pixel Scoreboard ([1] of DW1)
308 * - Depth Stall ([13] of DW1)
309 * - Post-Sync Operation ([13] of DW1)
310 * - Notify Enable ([8] of DW1)"
312 * The cache flushes require the workaround flush that triggered this
313 * one, so we can't use it. Depth stall would trigger the same.
314 * Post-sync nonzero is what triggered this second workaround, so we
315 * can't use that one either. Notify enable is IRQs, which aren't
316 * really our business. That leaves only stall at scoreboard.
319 brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
321 brw_emit_pipe_control_flush(brw
,
322 PIPE_CONTROL_CS_STALL
|
323 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
325 brw_emit_pipe_control_write(brw
, PIPE_CONTROL_WRITE_IMMEDIATE
,
326 brw
->workaround_bo
, 0, 0);
330 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
332 * Write synchronization is a special case of end-of-pipe
333 * synchronization that requires that the render cache and/or depth
334 * related caches are flushed to memory, where the data will become
335 * globally visible. This type of synchronization is required prior to
336 * SW (CPU) actually reading the result data from memory, or initiating
337 * an operation that will use as a read surface (such as a texture
338 * surface) a previous render target and/or depth/stencil buffer
341 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
343 * Exercising the write cache flush bits (Render Target Cache Flush
344 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
345 * ensures the write caches are flushed and doesn't guarantee the data
346 * is globally visible.
348 * SW can track the completion of the end-of-pipe-synchronization by
349 * using "Notify Enable" and "PostSync Operation - Write Immediate
350 * Data" in the PIPE_CONTROL command.
353 brw_emit_end_of_pipe_sync(struct brw_context
*brw
, uint32_t flags
)
355 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
357 if (devinfo
->gen
>= 6) {
358 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
360 * "The most common action to perform upon reaching a synchronization
361 * point is to write a value out to memory. An immediate value
362 * (included with the synchronization command) may be written."
365 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
367 * "In case the data flushed out by the render engine is to be read
368 * back in to the render engine in coherent manner, then the render
369 * engine has to wait for the fence completion before accessing the
370 * flushed data. This can be achieved by following means on various
371 * products: PIPE_CONTROL command with CS Stall and the required
372 * write caches flushed with Post-Sync-Operation as Write Immediate
376 * - Workload-1 (3D/GPGPU/MEDIA)
377 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write Immediate
378 * Data, Required Write Cache Flush bits set)
379 * - Workload-2 (Can use the data produce or output by Workload-1)
381 brw_emit_pipe_control_write(brw
,
382 flags
| PIPE_CONTROL_CS_STALL
|
383 PIPE_CONTROL_WRITE_IMMEDIATE
,
384 brw
->workaround_bo
, 0, 0);
386 if (devinfo
->is_haswell
) {
387 /* Haswell needs addition work-arounds:
389 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
392 * PIPE_CONTROL command with the CS Stall and the required write
393 * caches flushed with Post-SyncOperation as Write Immediate Data
394 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
399 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
400 * Immediate Data, Required Write Cache Flush bits set)
401 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
402 * - Workload-2 (Can use the data produce or output by
405 * Unfortunately, both the PRMs and the internal docs are a bit
406 * out-of-date in this regard. What the windows driver does (and
407 * this appears to actually work) is to emit a register read from the
408 * memory address written by the pipe control above.
410 * What register we load into doesn't matter. We choose an indirect
411 * rendering register because we know it always exists and it's one
412 * of the first registers the command parser allows us to write. If
413 * you don't have command parser support in your kernel (pre-4.2),
414 * this will get turned into MI_NOOP and you won't get the
415 * workaround. Unfortunately, there's just not much we can do in
416 * that case. This register is perfectly safe to write since we
417 * always re-load all of the indirect draw registers right before
418 * 3DPRIMITIVE when needed anyway.
420 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
,
421 brw
->workaround_bo
, 0);
424 /* On gen4-5, a regular pipe control seems to suffice. */
425 brw_emit_pipe_control_flush(brw
, flags
);
429 /* Emit a pipelined flush to either flush render and texture cache for
430 * reading from a FBO-drawn texture, or flush so that frontbuffer
431 * render appears on the screen in DRI1.
433 * This is also used for the always_flush_cache driconf debug option.
436 brw_emit_mi_flush(struct brw_context
*brw
)
438 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
440 if (brw
->batch
.ring
== BLT_RING
&& devinfo
->gen
>= 6) {
442 OUT_BATCH(MI_FLUSH_DW
);
448 int flags
= PIPE_CONTROL_NO_WRITE
| PIPE_CONTROL_RENDER_TARGET_FLUSH
;
449 if (devinfo
->gen
>= 6) {
450 flags
|= PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
451 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
452 PIPE_CONTROL_DATA_CACHE_FLUSH
|
453 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
454 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
455 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
456 PIPE_CONTROL_CS_STALL
;
458 brw_emit_pipe_control_flush(brw
, flags
);
463 brw_init_pipe_control(struct brw_context
*brw
,
464 const struct gen_device_info
*devinfo
)
466 if (devinfo
->gen
< 6)
469 /* We can't just use brw_state_batch to get a chunk of space for
470 * the gen6 workaround because it involves actually writing to
471 * the buffer, and the kernel doesn't let us write to the batch.
473 brw
->workaround_bo
= brw_bo_alloc(brw
->bufmgr
,
474 "pipe_control workaround",
476 if (brw
->workaround_bo
== NULL
)
479 brw
->pipe_controls_since_last_cs_stall
= 0;
485 brw_fini_pipe_control(struct brw_context
*brw
)
487 brw_bo_unreference(brw
->workaround_bo
);