src/mesa/drivers/dri/i965/brw_pipe_control.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "intel_batchbuffer.h"
  26 #include "intel_fbo.h"
  27 #include "intel_reg.h"
  28
  29 /**
  30  * According to the latest documentation, any PIPE_CONTROL with the
  31  * "Command Streamer Stall" bit set must also have another bit set,
  32  * with five different options:
  33  *
  34  *  - Render Target Cache Flush
  35  *  - Depth Cache Flush
  36  *  - Stall at Pixel Scoreboard
  37  *  - Post-Sync Operation
  38  *  - Depth Stall
  39  *  - DC Flush Enable
  40  *
  41  * I chose "Stall at Pixel Scoreboard" since we've used it effectively
  42  * in the past, but the choice is fairly arbitrary.
  43  */
  44 static void
  45 gen8_add_cs_stall_workaround_bits(uint32_t *flags)
  46 {
  47    uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
  48                       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
  49                       PIPE_CONTROL_WRITE_IMMEDIATE |
  50                       PIPE_CONTROL_WRITE_DEPTH_COUNT |
  51                       PIPE_CONTROL_WRITE_TIMESTAMP |
  52                       PIPE_CONTROL_STALL_AT_SCOREBOARD |
  53                       PIPE_CONTROL_DEPTH_STALL |
  54                       PIPE_CONTROL_DATA_CACHE_FLUSH;
  55
  56    /* If we're doing a CS stall, and don't already have one of the
  57     * workaround bits set, add "Stall at Pixel Scoreboard."
  58     */
  59    if ((*flags & PIPE_CONTROL_CS_STALL) != 0 && (*flags & wa_bits) == 0)
  60       *flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
  61 }
  62
  63 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
  64  *
  65  * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
  66  *  only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
  67  *
  68  * Note that the kernel does CS stalls between batches, so we only need
  69  * to count them within a batch.
  70  */
  71 static uint32_t
  72 gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
  73 {
  74    if (brw->gen == 7 && !brw->is_haswell) {
  75       if (flags & PIPE_CONTROL_CS_STALL) {
  76          /* If we're doing a CS stall, reset the counter and carry on. */
  77          brw->pipe_controls_since_last_cs_stall = 0;
  78          return 0;
  79       }
  80
  81       /* If this is the fourth pipe control without a CS stall, do one now. */
  82       if (++brw->pipe_controls_since_last_cs_stall == 4) {
  83          brw->pipe_controls_since_last_cs_stall = 0;
  84          return PIPE_CONTROL_CS_STALL;
  85       }
  86    }
  87    return 0;
  88 }
  89
  90 /**
  91  * Emit a PIPE_CONTROL with various flushing flags.
  92  *
  93  * The caller is responsible for deciding what flags are appropriate for the
  94  * given generation.
  95  */
  96 void
  97 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
  98 {
  99    if (brw->gen >= 8) {
 100       if (brw->gen == 8)
 101          gen8_add_cs_stall_workaround_bits(&flags);
 102
 103       BEGIN_BATCH(6);
 104       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
 105       OUT_BATCH(flags);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       OUT_BATCH(0);
 110       ADVANCE_BATCH();
 111    } else if (brw->gen >= 6) {
 112       if (brw->gen == 6 &&
 113           (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
 114          /* Hardware workaround: SNB B-Spec says:
 115           *
 116           *   [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
 117           *   Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
 118           *   required.
 119           */
 120          brw_emit_post_sync_nonzero_flush(brw);
 121       }
 122
 123       flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
 124
 125       BEGIN_BATCH(5);
 126       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
 127       OUT_BATCH(flags);
 128       OUT_BATCH(0);
 129       OUT_BATCH(0);
 130       OUT_BATCH(0);
 131       ADVANCE_BATCH();
 132    } else {
 133       BEGIN_BATCH(4);
 134       OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
 135       OUT_BATCH(0);
 136       OUT_BATCH(0);
 137       OUT_BATCH(0);
 138       ADVANCE_BATCH();
 139    }
 140 }
 141
 142 /**
 143  * Emit a PIPE_CONTROL that writes to a buffer object.
 144  *
 145  * \p flags should contain one of the following items:
 146  *  - PIPE_CONTROL_WRITE_IMMEDIATE
 147  *  - PIPE_CONTROL_WRITE_TIMESTAMP
 148  *  - PIPE_CONTROL_WRITE_DEPTH_COUNT
 149  */
 150 void
 151 brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
 152                             drm_intel_bo *bo, uint32_t offset,
 153                             uint32_t imm_lower, uint32_t imm_upper)
 154 {
 155    if (brw->gen >= 8) {
 156       if (brw->gen == 8)
 157          gen8_add_cs_stall_workaround_bits(&flags);
 158
 159       BEGIN_BATCH(6);
 160       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
 161       OUT_BATCH(flags);
 162       OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 163                   offset);
 164       OUT_BATCH(imm_lower);
 165       OUT_BATCH(imm_upper);
 166       ADVANCE_BATCH();
 167    } else if (brw->gen >= 6) {
 168       flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
 169
 170       /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
 171        * on later platforms.  We always use PPGTT on Gen7+.
 172        */
 173       unsigned gen6_gtt = brw->gen == 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE : 0;
 174
 175       BEGIN_BATCH(5);
 176       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
 177       OUT_BATCH(flags);
 178       OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 179                 gen6_gtt | offset);
 180       OUT_BATCH(imm_lower);
 181       OUT_BATCH(imm_upper);
 182       ADVANCE_BATCH();
 183    } else {
 184       BEGIN_BATCH(4);
 185       OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
 186       OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 187                 PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
 188       OUT_BATCH(imm_lower);
 189       OUT_BATCH(imm_upper);
 190       ADVANCE_BATCH();
 191    }
 192 }
 193
 194 /**
 195  * Restriction [DevSNB, DevIVB]:
 196  *
 197  * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
 198  * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
 199  * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
 200  * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
 201  * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
 202  * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
 203  * unless SW can otherwise guarantee that the pipeline from WM onwards is
 204  * already flushed (e.g., via a preceding MI_FLUSH).
 205  */
 206 void
 207 brw_emit_depth_stall_flushes(struct brw_context *brw)
 208 {
 209    assert(brw->gen >= 6 && brw->gen <= 9);
 210
 211    /* Starting on BDW, these pipe controls are unnecessary.
 212     *
 213     *   WM HW will internally manage the draining pipe and flushing of the caches
 214     *   when this command is issued. The PIPE_CONTROL restrictions are removed.
 215     */
 216    if (brw->gen >= 8)
 217       return;
 218
 219    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 220    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
 221    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 222 }
 223
 224 /**
 225  * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
 226  * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
 227  *  stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 228  *  3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 229  *  3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL needs
 230  *  to be sent before any combination of VS associated 3DSTATE."
 231  */
 232 void
 233 gen7_emit_vs_workaround_flush(struct brw_context *brw)
 234 {
 235    assert(brw->gen == 7);
 236    brw_emit_pipe_control_write(brw,
 237                                PIPE_CONTROL_WRITE_IMMEDIATE
 238                                | PIPE_CONTROL_DEPTH_STALL,
 239                                brw->workaround_bo, 0,
 240                                0, 0);
 241 }
 242
 243
 244 /**
 245  * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
 246  */
 247 void
 248 gen7_emit_cs_stall_flush(struct brw_context *brw)
 249 {
 250    brw_emit_pipe_control_write(brw,
 251                                PIPE_CONTROL_CS_STALL
 252                                | PIPE_CONTROL_WRITE_IMMEDIATE,
 253                                brw->workaround_bo, 0,
 254                                0, 0);
 255 }
 256
 257
 258 /**
 259  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 260  * implementing two workarounds on gen6.  From section 1.4.7.1
 261  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 262  *
 263  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 264  * produced by non-pipelined state commands), software needs to first
 265  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 266  * 0.
 267  *
 268  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 269  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 270  *
 271  * And the workaround for these two requires this workaround first:
 272  *
 273  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 274  * BEFORE the pipe-control with a post-sync op and no write-cache
 275  * flushes.
 276  *
 277  * And this last workaround is tricky because of the requirements on
 278  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 279  * volume 2 part 1:
 280  *
 281  *     "1 of the following must also be set:
 282  *      - Render Target Cache Flush Enable ([12] of DW1)
 283  *      - Depth Cache Flush Enable ([0] of DW1)
 284  *      - Stall at Pixel Scoreboard ([1] of DW1)
 285  *      - Depth Stall ([13] of DW1)
 286  *      - Post-Sync Operation ([13] of DW1)
 287  *      - Notify Enable ([8] of DW1)"
 288  *
 289  * The cache flushes require the workaround flush that triggered this
 290  * one, so we can't use it.  Depth stall would trigger the same.
 291  * Post-sync nonzero is what triggered this second workaround, so we
 292  * can't use that one either.  Notify enable is IRQs, which aren't
 293  * really our business.  That leaves only stall at scoreboard.
 294  */
 295 void
 296 brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
 297 {
 298    brw_emit_pipe_control_flush(brw,
 299                                PIPE_CONTROL_CS_STALL |
 300                                PIPE_CONTROL_STALL_AT_SCOREBOARD);
 301
 302    brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
 303                                brw->workaround_bo, 0, 0, 0);
 304 }
 305
 306 /* Emit a pipelined flush to either flush render and texture cache for
 307  * reading from a FBO-drawn texture, or flush so that frontbuffer
 308  * render appears on the screen in DRI1.
 309  *
 310  * This is also used for the always_flush_cache driconf debug option.
 311  */
 312 void
 313 brw_emit_mi_flush(struct brw_context *brw)
 314 {
 315    if (brw->batch.ring == BLT_RING && brw->gen >= 6) {
 316       BEGIN_BATCH_BLT(4);
 317       OUT_BATCH(MI_FLUSH_DW);
 318       OUT_BATCH(0);
 319       OUT_BATCH(0);
 320       OUT_BATCH(0);
 321       ADVANCE_BATCH();
 322    } else {
 323       int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
 324       if (brw->gen >= 6) {
 325          if (brw->gen == 9) {
 326             /* Hardware workaround: SKL
 327              *
 328              * Emit Pipe Control with all bits set to zero before emitting
 329              * a Pipe Control with VF Cache Invalidate set.
 330              */
 331             brw_emit_pipe_control_flush(brw, 0);
 332          }
 333
 334          flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 335                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 336                   PIPE_CONTROL_VF_CACHE_INVALIDATE |
 337                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 338                   PIPE_CONTROL_CS_STALL;
 339       }
 340       brw_emit_pipe_control_flush(brw, flags);
 341    }
 342 }
 343
 344 int
 345 brw_init_pipe_control(struct brw_context *brw,
 346                       const struct brw_device_info *devinfo)
 347 {
 348    if (devinfo->gen < 6)
 349       return 0;
 350
 351    /* We can't just use brw_state_batch to get a chunk of space for
 352     * the gen6 workaround because it involves actually writing to
 353     * the buffer, and the kernel doesn't let us write to the batch.
 354     */
 355    brw->workaround_bo = drm_intel_bo_alloc(brw->bufmgr,
 356                                            "pipe_control workaround",
 357                                            4096, 4096);
 358    if (brw->workaround_bo == NULL)
 359       return -ENOMEM;
 360
 361    brw->pipe_controls_since_last_cs_stall = 0;
 362
 363    return 0;
 364 }
 365
 366 void
 367 brw_fini_pipe_control(struct brw_context *brw)
 368 {
 369    drm_intel_bo_unreference(brw->workaround_bo);
 370 }