2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
25 #include "brw_defines.h"
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
30 * According to the latest documentation, any PIPE_CONTROL with the
31 * "Command Streamer Stall" bit set must also have another bit set,
32 * with five different options:
34 * - Render Target Cache Flush
36 * - Stall at Pixel Scoreboard
37 * - Post-Sync Operation
41 * I chose "Stall at Pixel Scoreboard" since we've used it effectively
42 * in the past, but the choice is fairly arbitrary.
45 gen8_add_cs_stall_workaround_bits(uint32_t *flags
)
47 uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
48 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
49 PIPE_CONTROL_WRITE_IMMEDIATE
|
50 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
51 PIPE_CONTROL_WRITE_TIMESTAMP
|
52 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
53 PIPE_CONTROL_DEPTH_STALL
|
54 PIPE_CONTROL_DATA_CACHE_FLUSH
;
56 /* If we're doing a CS stall, and don't already have one of the
57 * workaround bits set, add "Stall at Pixel Scoreboard."
59 if ((*flags
& PIPE_CONTROL_CS_STALL
) != 0 && (*flags
& wa_bits
) == 0)
60 *flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
63 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
65 * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
66 * only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
68 * Note that the kernel does CS stalls between batches, so we only need
69 * to count them within a batch.
72 gen7_cs_stall_every_four_pipe_controls(struct brw_context
*brw
, uint32_t flags
)
74 if (brw
->gen
== 7 && !brw
->is_haswell
) {
75 if (flags
& PIPE_CONTROL_CS_STALL
) {
76 /* If we're doing a CS stall, reset the counter and carry on. */
77 brw
->pipe_controls_since_last_cs_stall
= 0;
81 /* If this is the fourth pipe control without a CS stall, do one now. */
82 if (++brw
->pipe_controls_since_last_cs_stall
== 4) {
83 brw
->pipe_controls_since_last_cs_stall
= 0;
84 return PIPE_CONTROL_CS_STALL
;
91 brw_emit_pipe_control(struct brw_context
*brw
, uint32_t flags
,
92 struct brw_bo
*bo
, uint32_t offset
, uint64_t imm
)
96 gen8_add_cs_stall_workaround_bits(&flags
);
99 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
100 /* Hardware workaround: SKL
102 * Emit Pipe Control with all bits set to zero before emitting
103 * a Pipe Control with VF Cache Invalidate set.
105 brw_emit_pipe_control_flush(brw
, 0);
109 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
112 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
,
113 I915_GEM_DOMAIN_INSTRUCTION
, offset
);
119 OUT_BATCH(imm
>> 32);
121 } else if (brw
->gen
>= 6) {
123 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
124 /* Hardware workaround: SNB B-Spec says:
126 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
127 * Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
130 brw_emit_post_sync_nonzero_flush(brw
);
133 flags
|= gen7_cs_stall_every_four_pipe_controls(brw
, flags
);
135 /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
136 * on later platforms. We always use PPGTT on Gen7+.
138 unsigned gen6_gtt
= brw
->gen
== 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE
: 0;
141 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
144 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
150 OUT_BATCH(imm
>> 32);
154 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
156 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
157 PIPE_CONTROL_GLOBAL_GTT_WRITE
| offset
);
162 OUT_BATCH(imm
>> 32);
168 * Emit a PIPE_CONTROL with various flushing flags.
170 * The caller is responsible for deciding what flags are appropriate for the
174 brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
)
177 (flags
& PIPE_CONTROL_CACHE_FLUSH_BITS
) &&
178 (flags
& PIPE_CONTROL_CACHE_INVALIDATE_BITS
)) {
179 /* A pipe control command with flush and invalidate bits set
180 * simultaneously is an inherently racy operation on Gen6+ if the
181 * contents of the flushed caches were intended to become visible from
182 * any of the invalidated caches. Split it in two PIPE_CONTROLs, the
183 * first one should stall the pipeline to make sure that the flushed R/W
184 * caches are coherent with memory once the specified R/O caches are
185 * invalidated. On pre-Gen6 hardware the (implicit) R/O cache
186 * invalidation seems to happen at the bottom of the pipeline together
187 * with any write cache flush, so this shouldn't be a concern. In order
188 * to ensure a full stall, we do an end-of-pipe sync.
190 brw_emit_end_of_pipe_sync(brw
, (flags
& PIPE_CONTROL_CACHE_FLUSH_BITS
));
191 flags
&= ~(PIPE_CONTROL_CACHE_FLUSH_BITS
| PIPE_CONTROL_CS_STALL
);
194 brw_emit_pipe_control(brw
, flags
, NULL
, 0, 0);
198 * Emit a PIPE_CONTROL that writes to a buffer object.
200 * \p flags should contain one of the following items:
201 * - PIPE_CONTROL_WRITE_IMMEDIATE
202 * - PIPE_CONTROL_WRITE_TIMESTAMP
203 * - PIPE_CONTROL_WRITE_DEPTH_COUNT
206 brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
207 struct brw_bo
*bo
, uint32_t offset
,
210 brw_emit_pipe_control(brw
, flags
, bo
, offset
, imm
);
214 * Restriction [DevSNB, DevIVB]:
216 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
217 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
218 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
219 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
220 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
221 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
222 * unless SW can otherwise guarantee that the pipeline from WM onwards is
223 * already flushed (e.g., via a preceding MI_FLUSH).
226 brw_emit_depth_stall_flushes(struct brw_context
*brw
)
228 assert(brw
->gen
>= 6);
230 /* Starting on BDW, these pipe controls are unnecessary.
232 * WM HW will internally manage the draining pipe and flushing of the caches
233 * when this command is issued. The PIPE_CONTROL restrictions are removed.
238 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
239 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
240 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
244 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
245 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
246 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
247 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
248 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
249 * to be sent before any combination of VS associated 3DSTATE."
252 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
254 assert(brw
->gen
== 7);
255 brw_emit_pipe_control_write(brw
,
256 PIPE_CONTROL_WRITE_IMMEDIATE
257 | PIPE_CONTROL_DEPTH_STALL
,
258 brw
->workaround_bo
, 0, 0);
263 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
266 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
268 brw_emit_pipe_control_write(brw
,
269 PIPE_CONTROL_CS_STALL
270 | PIPE_CONTROL_WRITE_IMMEDIATE
,
271 brw
->workaround_bo
, 0, 0);
275 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
276 * implementing two workarounds on gen6. From section 1.4.7.1
277 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
279 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
280 * produced by non-pipelined state commands), software needs to first
281 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
284 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
285 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
287 * And the workaround for these two requires this workaround first:
289 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
290 * BEFORE the pipe-control with a post-sync op and no write-cache
293 * And this last workaround is tricky because of the requirements on
294 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
297 * "1 of the following must also be set:
298 * - Render Target Cache Flush Enable ([12] of DW1)
299 * - Depth Cache Flush Enable ([0] of DW1)
300 * - Stall at Pixel Scoreboard ([1] of DW1)
301 * - Depth Stall ([13] of DW1)
302 * - Post-Sync Operation ([13] of DW1)
303 * - Notify Enable ([8] of DW1)"
305 * The cache flushes require the workaround flush that triggered this
306 * one, so we can't use it. Depth stall would trigger the same.
307 * Post-sync nonzero is what triggered this second workaround, so we
308 * can't use that one either. Notify enable is IRQs, which aren't
309 * really our business. That leaves only stall at scoreboard.
312 brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
314 brw_emit_pipe_control_flush(brw
,
315 PIPE_CONTROL_CS_STALL
|
316 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
318 brw_emit_pipe_control_write(brw
, PIPE_CONTROL_WRITE_IMMEDIATE
,
319 brw
->workaround_bo
, 0, 0);
323 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
325 * Write synchronization is a special case of end-of-pipe
326 * synchronization that requires that the render cache and/or depth
327 * related caches are flushed to memory, where the data will become
328 * globally visible. This type of synchronization is required prior to
329 * SW (CPU) actually reading the result data from memory, or initiating
330 * an operation that will use as a read surface (such as a texture
331 * surface) a previous render target and/or depth/stencil buffer
334 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
336 * Exercising the write cache flush bits (Render Target Cache Flush
337 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
338 * ensures the write caches are flushed and doesn't guarantee the data
339 * is globally visible.
341 * SW can track the completion of the end-of-pipe-synchronization by
342 * using "Notify Enable" and "PostSync Operation - Write Immediate
343 * Data" in the PIPE_CONTROL command.
346 brw_emit_end_of_pipe_sync(struct brw_context
*brw
, uint32_t flags
)
349 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
351 * "The most common action to perform upon reaching a synchronization
352 * point is to write a value out to memory. An immediate value
353 * (included with the synchronization command) may be written."
356 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
358 * "In case the data flushed out by the render engine is to be read
359 * back in to the render engine in coherent manner, then the render
360 * engine has to wait for the fence completion before accessing the
361 * flushed data. This can be achieved by following means on various
362 * products: PIPE_CONTROL command with CS Stall and the required
363 * write caches flushed with Post-Sync-Operation as Write Immediate
367 * - Workload-1 (3D/GPGPU/MEDIA)
368 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write Immediate
369 * Data, Required Write Cache Flush bits set)
370 * - Workload-2 (Can use the data produce or output by Workload-1)
372 brw_emit_pipe_control_write(brw
,
373 flags
| PIPE_CONTROL_CS_STALL
|
374 PIPE_CONTROL_WRITE_IMMEDIATE
,
375 brw
->workaround_bo
, 0, 0);
377 if (brw
->is_haswell
) {
378 /* Haswell needs addition work-arounds:
380 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
383 * PIPE_CONTROL command with the CS Stall and the required write
384 * caches flushed with Post-SyncOperation as Write Immediate Data
385 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
390 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
391 * Immediate Data, Required Write Cache Flush bits set)
392 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
393 * - Workload-2 (Can use the data produce or output by
396 * Unfortunately, both the PRMs and the internal docs are a bit
397 * out-of-date in this regard. What the windows driver does (and
398 * this appears to actually work) is to emit a register read from the
399 * memory address written by the pipe control above.
401 * What register we load into doesn't matter. We choose an indirect
402 * rendering register because we know it always exists and it's one
403 * of the first registers the command parser allows us to write. If
404 * you don't have command parser support in your kernel (pre-4.2),
405 * this will get turned into MI_NOOP and you won't get the
406 * workaround. Unfortunately, there's just not much we can do in
407 * that case. This register is perfectly safe to write since we
408 * always re-load all of the indirect draw registers right before
409 * 3DPRIMITIVE when needed anyway.
411 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
,
413 I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
416 /* On gen4-5, a regular pipe control seems to suffice. */
417 brw_emit_pipe_control_flush(brw
, flags
);
421 /* Emit a pipelined flush to either flush render and texture cache for
422 * reading from a FBO-drawn texture, or flush so that frontbuffer
423 * render appears on the screen in DRI1.
425 * This is also used for the always_flush_cache driconf debug option.
428 brw_emit_mi_flush(struct brw_context
*brw
)
430 if (brw
->batch
.ring
== BLT_RING
&& brw
->gen
>= 6) {
432 OUT_BATCH(MI_FLUSH_DW
);
438 int flags
= PIPE_CONTROL_NO_WRITE
| PIPE_CONTROL_RENDER_TARGET_FLUSH
;
440 flags
|= PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
441 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
442 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
443 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
444 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
445 PIPE_CONTROL_CS_STALL
;
447 brw_emit_pipe_control_flush(brw
, flags
);
452 brw_init_pipe_control(struct brw_context
*brw
,
453 const struct gen_device_info
*devinfo
)
455 if (devinfo
->gen
< 6)
458 /* We can't just use brw_state_batch to get a chunk of space for
459 * the gen6 workaround because it involves actually writing to
460 * the buffer, and the kernel doesn't let us write to the batch.
462 brw
->workaround_bo
= brw_bo_alloc(brw
->bufmgr
,
463 "pipe_control workaround",
465 if (brw
->workaround_bo
== NULL
)
468 brw
->pipe_controls_since_last_cs_stall
= 0;
474 brw_fini_pipe_control(struct brw_context
*brw
)
476 brw_bo_unreference(brw
->workaround_bo
);