src/mesa/drivers/dri/i965/brw_pipe_control.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "intel_batchbuffer.h"
  26 #include "intel_fbo.h"
  27 #include "intel_reg.h"
  28
  29 /**
  30  * According to the latest documentation, any PIPE_CONTROL with the
  31  * "Command Streamer Stall" bit set must also have another bit set,
  32  * with five different options:
  33  *
  34  *  - Render Target Cache Flush
  35  *  - Depth Cache Flush
  36  *  - Stall at Pixel Scoreboard
  37  *  - Post-Sync Operation
  38  *  - Depth Stall
  39  *  - DC Flush Enable
  40  *
  41  * I chose "Stall at Pixel Scoreboard" since we've used it effectively
  42  * in the past, but the choice is fairly arbitrary.
  43  */
  44 static void
  45 gen8_add_cs_stall_workaround_bits(uint32_t *flags)
  46 {
  47    uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
  48                       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
  49                       PIPE_CONTROL_WRITE_IMMEDIATE |
  50                       PIPE_CONTROL_WRITE_DEPTH_COUNT |
  51                       PIPE_CONTROL_WRITE_TIMESTAMP |
  52                       PIPE_CONTROL_STALL_AT_SCOREBOARD |
  53                       PIPE_CONTROL_DEPTH_STALL |
  54                       PIPE_CONTROL_DATA_CACHE_FLUSH;
  55
  56    /* If we're doing a CS stall, and don't already have one of the
  57     * workaround bits set, add "Stall at Pixel Scoreboard."
  58     */
  59    if ((*flags & PIPE_CONTROL_CS_STALL) != 0 && (*flags & wa_bits) == 0)
  60       *flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
  61 }
  62
  63 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
  64  *
  65  * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
  66  *  only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
  67  *
  68  * Note that the kernel does CS stalls between batches, so we only need
  69  * to count them within a batch.
  70  */
  71 static uint32_t
  72 gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
  73 {
  74    if (brw->gen == 7 && !brw->is_haswell) {
  75       if (flags & PIPE_CONTROL_CS_STALL) {
  76          /* If we're doing a CS stall, reset the counter and carry on. */
  77          brw->pipe_controls_since_last_cs_stall = 0;
  78          return 0;
  79       }
  80
  81       /* If this is the fourth pipe control without a CS stall, do one now. */
  82       if (++brw->pipe_controls_since_last_cs_stall == 4) {
  83          brw->pipe_controls_since_last_cs_stall = 0;
  84          return PIPE_CONTROL_CS_STALL;
  85       }
  86    }
  87    return 0;
  88 }
  89
  90 /**
  91  * Emit a PIPE_CONTROL with various flushing flags.
  92  *
  93  * The caller is responsible for deciding what flags are appropriate for the
  94  * given generation.
  95  */
  96 void
  97 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
  98 {
  99    if (brw->gen >= 8) {
 100       if (brw->gen == 8)
 101          gen8_add_cs_stall_workaround_bits(&flags);
 102
 103       if (brw->gen == 9 &&
 104           (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
 105          /* Hardware workaround: SKL
 106           *
 107           * Emit Pipe Control with all bits set to zero before emitting
 108           * a Pipe Control with VF Cache Invalidate set.
 109           */
 110          brw_emit_pipe_control_flush(brw, 0);
 111       }
 112
 113       BEGIN_BATCH(6);
 114       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
 115       OUT_BATCH(flags);
 116       OUT_BATCH(0);
 117       OUT_BATCH(0);
 118       OUT_BATCH(0);
 119       OUT_BATCH(0);
 120       ADVANCE_BATCH();
 121    } else if (brw->gen >= 6) {
 122       if (brw->gen == 6 &&
 123           (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
 124          /* Hardware workaround: SNB B-Spec says:
 125           *
 126           *   [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
 127           *   Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
 128           *   required.
 129           */
 130          brw_emit_post_sync_nonzero_flush(brw);
 131       }
 132
 133       flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
 134
 135       BEGIN_BATCH(5);
 136       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
 137       OUT_BATCH(flags);
 138       OUT_BATCH(0);
 139       OUT_BATCH(0);
 140       OUT_BATCH(0);
 141       ADVANCE_BATCH();
 142    } else {
 143       BEGIN_BATCH(4);
 144       OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
 145       OUT_BATCH(0);
 146       OUT_BATCH(0);
 147       OUT_BATCH(0);
 148       ADVANCE_BATCH();
 149    }
 150 }
 151
 152 /**
 153  * Emit a PIPE_CONTROL that writes to a buffer object.
 154  *
 155  * \p flags should contain one of the following items:
 156  *  - PIPE_CONTROL_WRITE_IMMEDIATE
 157  *  - PIPE_CONTROL_WRITE_TIMESTAMP
 158  *  - PIPE_CONTROL_WRITE_DEPTH_COUNT
 159  */
 160 void
 161 brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
 162                             drm_intel_bo *bo, uint32_t offset,
 163                             uint32_t imm_lower, uint32_t imm_upper)
 164 {
 165    if (brw->gen >= 8) {
 166       if (brw->gen == 8)
 167          gen8_add_cs_stall_workaround_bits(&flags);
 168
 169       BEGIN_BATCH(6);
 170       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
 171       OUT_BATCH(flags);
 172       OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 173                   offset);
 174       OUT_BATCH(imm_lower);
 175       OUT_BATCH(imm_upper);
 176       ADVANCE_BATCH();
 177    } else if (brw->gen >= 6) {
 178       flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
 179
 180       /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
 181        * on later platforms.  We always use PPGTT on Gen7+.
 182        */
 183       unsigned gen6_gtt = brw->gen == 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE : 0;
 184
 185       BEGIN_BATCH(5);
 186       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
 187       OUT_BATCH(flags);
 188       OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 189                 gen6_gtt | offset);
 190       OUT_BATCH(imm_lower);
 191       OUT_BATCH(imm_upper);
 192       ADVANCE_BATCH();
 193    } else {
 194       BEGIN_BATCH(4);
 195       OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
 196       OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 197                 PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
 198       OUT_BATCH(imm_lower);
 199       OUT_BATCH(imm_upper);
 200       ADVANCE_BATCH();
 201    }
 202 }
 203
 204 /**
 205  * Restriction [DevSNB, DevIVB]:
 206  *
 207  * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
 208  * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
 209  * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
 210  * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
 211  * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
 212  * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
 213  * unless SW can otherwise guarantee that the pipeline from WM onwards is
 214  * already flushed (e.g., via a preceding MI_FLUSH).
 215  */
 216 void
 217 brw_emit_depth_stall_flushes(struct brw_context *brw)
 218 {
 219    assert(brw->gen >= 6 && brw->gen <= 9);
 220
 221    /* Starting on BDW, these pipe controls are unnecessary.
 222     *
 223     *   WM HW will internally manage the draining pipe and flushing of the caches
 224     *   when this command is issued. The PIPE_CONTROL restrictions are removed.
 225     */
 226    if (brw->gen >= 8)
 227       return;
 228
 229    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 230    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
 231    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 232 }
 233
 234 /**
 235  * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
 236  * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
 237  *  stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 238  *  3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 239  *  3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL needs
 240  *  to be sent before any combination of VS associated 3DSTATE."
 241  */
 242 void
 243 gen7_emit_vs_workaround_flush(struct brw_context *brw)
 244 {
 245    assert(brw->gen == 7);
 246    brw_emit_pipe_control_write(brw,
 247                                PIPE_CONTROL_WRITE_IMMEDIATE
 248                                | PIPE_CONTROL_DEPTH_STALL,
 249                                brw->workaround_bo, 0,
 250                                0, 0);
 251 }
 252
 253
 254 /**
 255  * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
 256  */
 257 void
 258 gen7_emit_cs_stall_flush(struct brw_context *brw)
 259 {
 260    brw_emit_pipe_control_write(brw,
 261                                PIPE_CONTROL_CS_STALL
 262                                | PIPE_CONTROL_WRITE_IMMEDIATE,
 263                                brw->workaround_bo, 0,
 264                                0, 0);
 265 }
 266
 267
 268 /**
 269  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 270  * implementing two workarounds on gen6.  From section 1.4.7.1
 271  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 272  *
 273  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 274  * produced by non-pipelined state commands), software needs to first
 275  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 276  * 0.
 277  *
 278  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 279  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 280  *
 281  * And the workaround for these two requires this workaround first:
 282  *
 283  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 284  * BEFORE the pipe-control with a post-sync op and no write-cache
 285  * flushes.
 286  *
 287  * And this last workaround is tricky because of the requirements on
 288  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 289  * volume 2 part 1:
 290  *
 291  *     "1 of the following must also be set:
 292  *      - Render Target Cache Flush Enable ([12] of DW1)
 293  *      - Depth Cache Flush Enable ([0] of DW1)
 294  *      - Stall at Pixel Scoreboard ([1] of DW1)
 295  *      - Depth Stall ([13] of DW1)
 296  *      - Post-Sync Operation ([13] of DW1)
 297  *      - Notify Enable ([8] of DW1)"
 298  *
 299  * The cache flushes require the workaround flush that triggered this
 300  * one, so we can't use it.  Depth stall would trigger the same.
 301  * Post-sync nonzero is what triggered this second workaround, so we
 302  * can't use that one either.  Notify enable is IRQs, which aren't
 303  * really our business.  That leaves only stall at scoreboard.
 304  */
 305 void
 306 brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
 307 {
 308    brw_emit_pipe_control_flush(brw,
 309                                PIPE_CONTROL_CS_STALL |
 310                                PIPE_CONTROL_STALL_AT_SCOREBOARD);
 311
 312    brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
 313                                brw->workaround_bo, 0, 0, 0);
 314 }
 315
 316 /* Emit a pipelined flush to either flush render and texture cache for
 317  * reading from a FBO-drawn texture, or flush so that frontbuffer
 318  * render appears on the screen in DRI1.
 319  *
 320  * This is also used for the always_flush_cache driconf debug option.
 321  */
 322 void
 323 brw_emit_mi_flush(struct brw_context *brw)
 324 {
 325    if (brw->batch.ring == BLT_RING && brw->gen >= 6) {
 326       BEGIN_BATCH_BLT(4);
 327       OUT_BATCH(MI_FLUSH_DW);
 328       OUT_BATCH(0);
 329       OUT_BATCH(0);
 330       OUT_BATCH(0);
 331       ADVANCE_BATCH();
 332    } else {
 333       int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
 334       if (brw->gen >= 6) {
 335          flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 336                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 337                   PIPE_CONTROL_VF_CACHE_INVALIDATE |
 338                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 339                   PIPE_CONTROL_CS_STALL;
 340       }
 341       brw_emit_pipe_control_flush(brw, flags);
 342    }
 343 }
 344
 345 int
 346 brw_init_pipe_control(struct brw_context *brw,
 347                       const struct brw_device_info *devinfo)
 348 {
 349    if (devinfo->gen < 6)
 350       return 0;
 351
 352    /* We can't just use brw_state_batch to get a chunk of space for
 353     * the gen6 workaround because it involves actually writing to
 354     * the buffer, and the kernel doesn't let us write to the batch.
 355     */
 356    brw->workaround_bo = drm_intel_bo_alloc(brw->bufmgr,
 357                                            "pipe_control workaround",
 358                                            4096, 4096);
 359    if (brw->workaround_bo == NULL)
 360       return -ENOMEM;
 361
 362    brw->pipe_controls_since_last_cs_stall = 0;
 363
 364    return 0;
 365 }
 366
 367 void
 368 brw_fini_pipe_control(struct brw_context *brw)
 369 {
 370    drm_intel_bo_unreference(brw->workaround_bo);
 371 }