src/mesa/drivers/dri/i965/brw_pipe_control.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_defines.h"
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28
  29 /**
  30  * According to the latest documentation, any PIPE_CONTROL with the
  31  * "Command Streamer Stall" bit set must also have another bit set,
  32  * with five different options:
  33  *
  34  *  - Render Target Cache Flush
  35  *  - Depth Cache Flush
  36  *  - Stall at Pixel Scoreboard
  37  *  - Post-Sync Operation
  38  *  - Depth Stall
  39  *  - DC Flush Enable
  40  *
  41  * I chose "Stall at Pixel Scoreboard" since we've used it effectively
  42  * in the past, but the choice is fairly arbitrary.
  43  */
  44 static void
  45 gen8_add_cs_stall_workaround_bits(uint32_t *flags)
  46 {
  47    uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
  48                       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
  49                       PIPE_CONTROL_WRITE_IMMEDIATE |
  50                       PIPE_CONTROL_WRITE_DEPTH_COUNT |
  51                       PIPE_CONTROL_WRITE_TIMESTAMP |
  52                       PIPE_CONTROL_STALL_AT_SCOREBOARD |
  53                       PIPE_CONTROL_DEPTH_STALL |
  54                       PIPE_CONTROL_DATA_CACHE_FLUSH;
  55
  56    /* If we're doing a CS stall, and don't already have one of the
  57     * workaround bits set, add "Stall at Pixel Scoreboard."
  58     */
  59    if ((*flags & PIPE_CONTROL_CS_STALL) != 0 && (*flags & wa_bits) == 0)
  60       *flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
  61 }
  62
  63 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
  64  *
  65  * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
  66  *  only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
  67  *
  68  * Note that the kernel does CS stalls between batches, so we only need
  69  * to count them within a batch.
  70  */
  71 static uint32_t
  72 gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
  73 {
  74    if (brw->gen == 7 && !brw->is_haswell) {
  75       if (flags & PIPE_CONTROL_CS_STALL) {
  76          /* If we're doing a CS stall, reset the counter and carry on. */
  77          brw->pipe_controls_since_last_cs_stall = 0;
  78          return 0;
  79       }
  80
  81       /* If this is the fourth pipe control without a CS stall, do one now. */
  82       if (++brw->pipe_controls_since_last_cs_stall == 4) {
  83          brw->pipe_controls_since_last_cs_stall = 0;
  84          return PIPE_CONTROL_CS_STALL;
  85       }
  86    }
  87    return 0;
  88 }
  89
  90 static void
  91 brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
  92                       struct brw_bo *bo, uint32_t offset, uint64_t imm)
  93 {
  94    if (brw->gen >= 8) {
  95       if (brw->gen == 8)
  96          gen8_add_cs_stall_workaround_bits(&flags);
  97
  98       if (brw->gen == 9 &&
  99           (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
 100          /* Hardware workaround: SKL
 101           *
 102           * Emit Pipe Control with all bits set to zero before emitting
 103           * a Pipe Control with VF Cache Invalidate set.
 104           */
 105          brw_emit_pipe_control_flush(brw, 0);
 106       }
 107
 108       BEGIN_BATCH(6);
 109       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
 110       OUT_BATCH(flags);
 111       if (bo) {
 112          OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION,
 113                      I915_GEM_DOMAIN_INSTRUCTION, offset);
 114       } else {
 115          OUT_BATCH(0);
 116          OUT_BATCH(0);
 117       }
 118       OUT_BATCH(imm);
 119       OUT_BATCH(imm >> 32);
 120       ADVANCE_BATCH();
 121    } else if (brw->gen >= 6) {
 122       if (brw->gen == 6 &&
 123           (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
 124          /* Hardware workaround: SNB B-Spec says:
 125           *
 126           *   [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
 127           *   Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
 128           *   required.
 129           */
 130          brw_emit_post_sync_nonzero_flush(brw);
 131       }
 132
 133       flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
 134
 135       /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
 136        * on later platforms.  We always use PPGTT on Gen7+.
 137        */
 138       unsigned gen6_gtt = brw->gen == 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE : 0;
 139
 140       BEGIN_BATCH(5);
 141       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
 142       OUT_BATCH(flags);
 143       if (bo) {
 144          OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 145                    gen6_gtt | offset);
 146       } else {
 147          OUT_BATCH(0);
 148       }
 149       OUT_BATCH(imm);
 150       OUT_BATCH(imm >> 32);
 151       ADVANCE_BATCH();
 152    } else {
 153       BEGIN_BATCH(4);
 154       OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
 155       if (bo) {
 156          OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 157                    PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
 158       } else {
 159          OUT_BATCH(0);
 160       }
 161       OUT_BATCH(imm);
 162       OUT_BATCH(imm >> 32);
 163       ADVANCE_BATCH();
 164    }
 165 }
 166
 167 /**
 168  * Emit a PIPE_CONTROL with various flushing flags.
 169  *
 170  * The caller is responsible for deciding what flags are appropriate for the
 171  * given generation.
 172  */
 173 void
 174 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
 175 {
 176    if (brw->gen >= 6 &&
 177        (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) &&
 178        (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) {
 179       /* A pipe control command with flush and invalidate bits set
 180        * simultaneously is an inherently racy operation on Gen6+ if the
 181        * contents of the flushed caches were intended to become visible from
 182        * any of the invalidated caches.  Split it in two PIPE_CONTROLs, the
 183        * first one should stall the pipeline to make sure that the flushed R/W
 184        * caches are coherent with memory once the specified R/O caches are
 185        * invalidated.  On pre-Gen6 hardware the (implicit) R/O cache
 186        * invalidation seems to happen at the bottom of the pipeline together
 187        * with any write cache flush, so this shouldn't be a concern.
 188        */
 189       brw_emit_pipe_control_flush(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) |
 190                                        PIPE_CONTROL_CS_STALL);
 191       flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
 192    }
 193
 194    brw_emit_pipe_control(brw, flags, NULL, 0, 0);
 195 }
 196
 197 /**
 198  * Emit a PIPE_CONTROL that writes to a buffer object.
 199  *
 200  * \p flags should contain one of the following items:
 201  *  - PIPE_CONTROL_WRITE_IMMEDIATE
 202  *  - PIPE_CONTROL_WRITE_TIMESTAMP
 203  *  - PIPE_CONTROL_WRITE_DEPTH_COUNT
 204  */
 205 void
 206 brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
 207                             struct brw_bo *bo, uint32_t offset,
 208                             uint64_t imm)
 209 {
 210    brw_emit_pipe_control(brw, flags, bo, offset, imm);
 211 }
 212
 213 /**
 214  * Restriction [DevSNB, DevIVB]:
 215  *
 216  * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
 217  * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
 218  * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
 219  * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
 220  * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
 221  * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
 222  * unless SW can otherwise guarantee that the pipeline from WM onwards is
 223  * already flushed (e.g., via a preceding MI_FLUSH).
 224  */
 225 void
 226 brw_emit_depth_stall_flushes(struct brw_context *brw)
 227 {
 228    assert(brw->gen >= 6);
 229
 230    /* Starting on BDW, these pipe controls are unnecessary.
 231     *
 232     *   WM HW will internally manage the draining pipe and flushing of the caches
 233     *   when this command is issued. The PIPE_CONTROL restrictions are removed.
 234     */
 235    if (brw->gen >= 8)
 236       return;
 237
 238    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 239    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
 240    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 241 }
 242
 243 /**
 244  * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
 245  * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
 246  *  stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 247  *  3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 248  *  3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL needs
 249  *  to be sent before any combination of VS associated 3DSTATE."
 250  */
 251 void
 252 gen7_emit_vs_workaround_flush(struct brw_context *brw)
 253 {
 254    assert(brw->gen == 7);
 255    brw_emit_pipe_control_write(brw,
 256                                PIPE_CONTROL_WRITE_IMMEDIATE
 257                                | PIPE_CONTROL_DEPTH_STALL,
 258                                brw->workaround_bo, 0, 0);
 259 }
 260
 261
 262 /**
 263  * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
 264  */
 265 void
 266 gen7_emit_cs_stall_flush(struct brw_context *brw)
 267 {
 268    brw_emit_pipe_control_write(brw,
 269                                PIPE_CONTROL_CS_STALL
 270                                | PIPE_CONTROL_WRITE_IMMEDIATE,
 271                                brw->workaround_bo, 0, 0);
 272 }
 273
 274
 275 /**
 276  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 277  * implementing two workarounds on gen6.  From section 1.4.7.1
 278  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 279  *
 280  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 281  * produced by non-pipelined state commands), software needs to first
 282  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 283  * 0.
 284  *
 285  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 286  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 287  *
 288  * And the workaround for these two requires this workaround first:
 289  *
 290  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 291  * BEFORE the pipe-control with a post-sync op and no write-cache
 292  * flushes.
 293  *
 294  * And this last workaround is tricky because of the requirements on
 295  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 296  * volume 2 part 1:
 297  *
 298  *     "1 of the following must also be set:
 299  *      - Render Target Cache Flush Enable ([12] of DW1)
 300  *      - Depth Cache Flush Enable ([0] of DW1)
 301  *      - Stall at Pixel Scoreboard ([1] of DW1)
 302  *      - Depth Stall ([13] of DW1)
 303  *      - Post-Sync Operation ([13] of DW1)
 304  *      - Notify Enable ([8] of DW1)"
 305  *
 306  * The cache flushes require the workaround flush that triggered this
 307  * one, so we can't use it.  Depth stall would trigger the same.
 308  * Post-sync nonzero is what triggered this second workaround, so we
 309  * can't use that one either.  Notify enable is IRQs, which aren't
 310  * really our business.  That leaves only stall at scoreboard.
 311  */
 312 void
 313 brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
 314 {
 315    brw_emit_pipe_control_flush(brw,
 316                                PIPE_CONTROL_CS_STALL |
 317                                PIPE_CONTROL_STALL_AT_SCOREBOARD);
 318
 319    brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
 320                                brw->workaround_bo, 0, 0);
 321 }
 322
 323 /* Emit a pipelined flush to either flush render and texture cache for
 324  * reading from a FBO-drawn texture, or flush so that frontbuffer
 325  * render appears on the screen in DRI1.
 326  *
 327  * This is also used for the always_flush_cache driconf debug option.
 328  */
 329 void
 330 brw_emit_mi_flush(struct brw_context *brw)
 331 {
 332    if (brw->batch.ring == BLT_RING && brw->gen >= 6) {
 333       BEGIN_BATCH_BLT(4);
 334       OUT_BATCH(MI_FLUSH_DW);
 335       OUT_BATCH(0);
 336       OUT_BATCH(0);
 337       OUT_BATCH(0);
 338       ADVANCE_BATCH();
 339    } else {
 340       int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
 341       if (brw->gen >= 6) {
 342          flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 343                   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 344                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 345                   PIPE_CONTROL_VF_CACHE_INVALIDATE |
 346                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 347                   PIPE_CONTROL_CS_STALL;
 348       }
 349       brw_emit_pipe_control_flush(brw, flags);
 350    }
 351 }
 352
 353 int
 354 brw_init_pipe_control(struct brw_context *brw,
 355                       const struct gen_device_info *devinfo)
 356 {
 357    if (devinfo->gen < 6)
 358       return 0;
 359
 360    /* We can't just use brw_state_batch to get a chunk of space for
 361     * the gen6 workaround because it involves actually writing to
 362     * the buffer, and the kernel doesn't let us write to the batch.
 363     */
 364    brw->workaround_bo = brw_bo_alloc(brw->bufmgr,
 365                                      "pipe_control workaround",
 366                                      4096, 4096);
 367    if (brw->workaround_bo == NULL)
 368       return -ENOMEM;
 369
 370    brw->pipe_controls_since_last_cs_stall = 0;
 371
 372    return 0;
 373 }
 374
 375 void
 376 brw_fini_pipe_control(struct brw_context *brw)
 377 {
 378    brw_bo_unreference(brw->workaround_bo);
 379 }