2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/imports.h"
34 #include "main/glspirv.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_to_nir.h"
38 #include "program/program.h"
39 #include "program/programopt.h"
41 #include "util/ralloc.h"
42 #include "compiler/glsl/ir.h"
43 #include "compiler/glsl/program.h"
44 #include "compiler/glsl/gl_nir.h"
45 #include "compiler/glsl/glsl_to_nir.h"
46 #include "glsl/float64_glsl.h"
48 #include "brw_program.h"
49 #include "brw_context.h"
50 #include "compiler/brw_nir.h"
51 #include "brw_defines.h"
52 #include "intel_batchbuffer.h"
59 #include "main/shaderapi.h"
60 #include "main/shaderobj.h"
63 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
66 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
67 type_size_scalar_bytes
);
68 return nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
, 0);
70 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
71 type_size_vec4_bytes
);
72 return nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
, 0);
76 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
77 GLuint id
, bool is_arb_asm
);
80 compile_fp64_funcs(struct gl_context
*ctx
,
81 const nir_shader_compiler_options
*options
,
83 gl_shader_stage stage
)
85 const GLuint name
= ~0;
88 sh
= _mesa_new_shader(name
, stage
);
90 sh
->Source
= float64_source
;
91 sh
->CompileStatus
= COMPILE_FAILURE
;
92 _mesa_glsl_compile_shader(ctx
, sh
, false, false, true);
94 if (!sh
->CompileStatus
) {
97 "fp64 software impl compile failed:\n%s\nsource:\n%s\n",
98 sh
->InfoLog
, float64_source
);
102 struct gl_shader_program
*sh_prog
;
103 sh_prog
= _mesa_new_shader_program(name
);
104 sh_prog
->Label
= NULL
;
105 sh_prog
->NumShaders
= 1;
106 sh_prog
->Shaders
= malloc(sizeof(struct gl_shader
*));
107 sh_prog
->Shaders
[0] = sh
;
109 struct gl_linked_shader
*linked
= rzalloc(NULL
, struct gl_linked_shader
);
110 linked
->Stage
= stage
;
113 _mesa_shader_stage_to_program(stage
),
117 sh_prog
->_LinkedShaders
[stage
] = linked
;
119 nir_shader
*nir
= glsl_to_nir(sh_prog
, stage
, options
);
121 return nir_shader_clone(mem_ctx
, nir
);
125 brw_create_nir(struct brw_context
*brw
,
126 const struct gl_shader_program
*shader_prog
,
127 struct gl_program
*prog
,
128 gl_shader_stage stage
,
131 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
132 struct gl_context
*ctx
= &brw
->ctx
;
133 const nir_shader_compiler_options
*options
=
134 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
137 /* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
139 if (shader_prog
->data
->spirv
) {
140 nir
= _mesa_spirv_to_nir(ctx
, shader_prog
, stage
, options
);
142 nir
= glsl_to_nir(shader_prog
, stage
, options
);
146 nir_remove_dead_variables(nir
, nir_var_shader_in
| nir_var_shader_out
);
147 nir_lower_returns(nir
);
148 nir_validate_shader(nir
, "after glsl_to_nir or spirv_to_nir and "
150 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
151 nir_shader_get_entrypoint(nir
), true, false);
153 nir
= prog_to_nir(prog
, options
);
154 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
); /* turn registers into SSA */
155 NIR_PASS_V(nir
, gl_nir_lower_samplers
, NULL
);
157 nir_validate_shader(nir
, "before brw_preprocess_nir");
159 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
161 if ((options
->lower_doubles_options
& nir_lower_fp64_full_software
) &&
162 nir
->info
.uses_64bit
) {
163 nir_shader
*fp64
= compile_fp64_funcs(ctx
, options
, ralloc_parent(nir
), stage
);
165 nir_validate_shader(fp64
, "fp64");
166 exec_list_append(&nir
->functions
, &fp64
->functions
);
169 nir
= brw_preprocess_nir(brw
->screen
->compiler
, nir
);
171 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
173 if (stage
== MESA_SHADER_TESS_CTRL
) {
174 /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */
175 static const gl_state_index16 tokens
[STATE_LENGTH
] =
176 { STATE_INTERNAL
, STATE_TCS_PATCH_VERTICES_IN
};
177 nir_lower_patch_vertices(nir
, 0, devinfo
->gen
>= 8 ? tokens
: NULL
);
180 if (stage
== MESA_SHADER_TESS_EVAL
) {
181 /* Lower gl_PatchVerticesIn to a constant if we have a TCS, or
182 * a uniform if we don't.
184 struct gl_linked_shader
*tcs
=
185 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_CTRL
];
186 uint32_t static_patch_vertices
=
187 tcs
? tcs
->Program
->nir
->info
.tess
.tcs_vertices_out
: 0;
188 static const gl_state_index16 tokens
[STATE_LENGTH
] =
189 { STATE_INTERNAL
, STATE_TES_PATCH_VERTICES_IN
};
190 nir_lower_patch_vertices(nir
, static_patch_vertices
, tokens
);
193 if (stage
== MESA_SHADER_FRAGMENT
) {
194 static const struct nir_lower_wpos_ytransform_options wpos_options
= {
195 .state_tokens
= {STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0},
196 .fs_coord_pixel_center_integer
= 1,
197 .fs_coord_origin_upper_left
= 1,
200 bool progress
= false;
201 NIR_PASS(progress
, nir
, nir_lower_wpos_ytransform
, &wpos_options
);
203 _mesa_add_state_reference(prog
->Parameters
,
204 wpos_options
.state_tokens
);
208 NIR_PASS_V(nir
, brw_nir_lower_uniforms
, is_scalar
);
214 brw_shader_gather_info(nir_shader
*nir
, struct gl_program
*prog
)
216 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
218 /* Copy the info we just generated back into the gl_program */
219 const char *prog_name
= prog
->info
.name
;
220 const char *prog_label
= prog
->info
.label
;
221 prog
->info
= nir
->info
;
222 prog
->info
.name
= prog_name
;
223 prog
->info
.label
= prog_label
;
227 get_new_program_id(struct intel_screen
*screen
)
229 return p_atomic_inc_return(&screen
->program_id
);
232 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
233 GLuint id
, bool is_arb_asm
)
235 struct brw_context
*brw
= brw_context(ctx
);
236 struct brw_program
*prog
= rzalloc(NULL
, struct brw_program
);
239 prog
->id
= get_new_program_id(brw
->screen
);
241 return _mesa_init_gl_program(&prog
->program
, target
, id
, is_arb_asm
);
247 static void brwDeleteProgram( struct gl_context
*ctx
,
248 struct gl_program
*prog
)
250 struct brw_context
*brw
= brw_context(ctx
);
252 /* Beware! prog's refcount has reached zero, and it's about to be freed.
254 * In brw_upload_pipeline_state(), we compare brw->programs[i] to
255 * ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
256 * pointer has changed.
258 * We cannot leave brw->programs[i] as a dangling pointer to the dead
259 * program. malloc() may allocate the same memory for a new gl_program,
260 * causing us to see matching pointers...but totally different programs.
262 * We cannot set brw->programs[i] to NULL, either. If we've deleted the
263 * active program, Mesa may set ctx->FooProgram._Current to NULL. That
264 * would cause us to see matching pointers (NULL == NULL), and fail to
265 * detect that a program has changed since our last draw.
267 * So, set it to a bogus gl_program pointer that will never match,
268 * causing us to properly reevaluate the state on our next draw.
270 * Getting this wrong causes heisenbugs which are very hard to catch,
271 * as you need a very specific allocation pattern to hit the problem.
273 static const struct gl_program deleted_program
;
275 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
276 if (brw
->programs
[i
] == prog
)
277 brw
->programs
[i
] = (struct gl_program
*) &deleted_program
;
280 _mesa_delete_program( ctx
, prog
);
285 brwProgramStringNotify(struct gl_context
*ctx
,
287 struct gl_program
*prog
)
289 assert(target
== GL_VERTEX_PROGRAM_ARB
|| !prog
->arb
.IsPositionInvariant
);
291 struct brw_context
*brw
= brw_context(ctx
);
292 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
295 case GL_FRAGMENT_PROGRAM_ARB
: {
296 struct brw_program
*newFP
= brw_program(prog
);
297 const struct brw_program
*curFP
=
298 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
301 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
302 newFP
->id
= get_new_program_id(brw
->screen
);
304 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_FRAGMENT
, true);
306 brw_shader_gather_info(prog
->nir
, prog
);
308 brw_fs_precompile(ctx
, prog
);
311 case GL_VERTEX_PROGRAM_ARB
: {
312 struct brw_program
*newVP
= brw_program(prog
);
313 const struct brw_program
*curVP
=
314 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
317 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
318 if (newVP
->program
.arb
.IsPositionInvariant
) {
319 _mesa_insert_mvp_code(ctx
, &newVP
->program
);
321 newVP
->id
= get_new_program_id(brw
->screen
);
323 /* Also tell tnl about it:
325 _tnl_program_string(ctx
, target
, prog
);
327 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_VERTEX
,
328 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
330 brw_shader_gather_info(prog
->nir
, prog
);
332 brw_vs_precompile(ctx
, prog
);
337 * driver->ProgramStringNotify is only called for ARB programs, fixed
338 * function vertex programs, and ir_to_mesa (which isn't used by the
339 * i965 back-end). Therefore, even after geometry shaders are added,
340 * this function should only ever be called with a target of
341 * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
343 unreachable("Unexpected target in brwProgramStringNotify");
350 brw_memory_barrier(struct gl_context
*ctx
, GLbitfield barriers
)
352 struct brw_context
*brw
= brw_context(ctx
);
353 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
354 unsigned bits
= PIPE_CONTROL_DATA_CACHE_FLUSH
| PIPE_CONTROL_CS_STALL
;
355 assert(devinfo
->gen
>= 7 && devinfo
->gen
<= 11);
357 if (barriers
& (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT
|
358 GL_ELEMENT_ARRAY_BARRIER_BIT
|
359 GL_COMMAND_BARRIER_BIT
))
360 bits
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
362 if (barriers
& GL_UNIFORM_BARRIER_BIT
)
363 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
364 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
366 if (barriers
& GL_TEXTURE_FETCH_BARRIER_BIT
)
367 bits
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
369 if (barriers
& (GL_TEXTURE_UPDATE_BARRIER_BIT
|
370 GL_PIXEL_BUFFER_BARRIER_BIT
))
371 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
372 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
374 if (barriers
& GL_FRAMEBUFFER_BARRIER_BIT
)
375 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
376 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
378 /* Typed surface messages are handled by the render cache on IVB, so we
379 * need to flush it too.
381 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
382 bits
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
384 brw_emit_pipe_control_flush(brw
, bits
);
388 brw_framebuffer_fetch_barrier(struct gl_context
*ctx
)
390 struct brw_context
*brw
= brw_context(ctx
);
391 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
393 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
) {
394 if (devinfo
->gen
>= 6) {
395 brw_emit_pipe_control_flush(brw
,
396 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
397 PIPE_CONTROL_CS_STALL
);
398 brw_emit_pipe_control_flush(brw
,
399 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
401 brw_emit_pipe_control_flush(brw
,
402 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
408 brw_get_scratch_bo(struct brw_context
*brw
,
409 struct brw_bo
**scratch_bo
, int size
)
411 struct brw_bo
*old_bo
= *scratch_bo
;
413 if (old_bo
&& old_bo
->size
< size
) {
414 brw_bo_unreference(old_bo
);
420 brw_bo_alloc(brw
->bufmgr
, "scratch bo", size
, BRW_MEMZONE_SCRATCH
);
425 * Reserve enough scratch space for the given stage to hold \p per_thread_size
426 * bytes times the given \p thread_count.
429 brw_alloc_stage_scratch(struct brw_context
*brw
,
430 struct brw_stage_state
*stage_state
,
431 unsigned per_thread_size
)
433 if (stage_state
->per_thread_scratch
>= per_thread_size
)
436 stage_state
->per_thread_scratch
= per_thread_size
;
438 if (stage_state
->scratch_bo
)
439 brw_bo_unreference(stage_state
->scratch_bo
);
441 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
442 unsigned thread_count
;
443 switch(stage_state
->stage
) {
444 case MESA_SHADER_VERTEX
:
445 thread_count
= devinfo
->max_vs_threads
;
447 case MESA_SHADER_TESS_CTRL
:
448 thread_count
= devinfo
->max_tcs_threads
;
450 case MESA_SHADER_TESS_EVAL
:
451 thread_count
= devinfo
->max_tes_threads
;
453 case MESA_SHADER_GEOMETRY
:
454 thread_count
= devinfo
->max_gs_threads
;
456 case MESA_SHADER_FRAGMENT
:
457 thread_count
= devinfo
->max_wm_threads
;
459 case MESA_SHADER_COMPUTE
: {
460 unsigned subslices
= MAX2(brw
->screen
->subslice_total
, 1);
462 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
464 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
465 * allocate scratch space enough so that each slice has 4 slices
468 * According to the other driver team, this applies to compute shaders
469 * as well. This is not currently documented at all.
471 * brw->screen->subslice_total is the TOTAL number of subslices
472 * and we wish to view that there are 4 subslices per slice
473 * instead of the actual number of subslices per slice.
475 if (devinfo
->gen
>= 9 && devinfo
->gen
< 11)
476 subslices
= 4 * brw
->screen
->devinfo
.num_slices
;
478 unsigned scratch_ids_per_subslice
;
479 if (devinfo
->is_haswell
) {
480 /* WaCSScratchSize:hsw
482 * Haswell's scratch space address calculation appears to be sparse
483 * rather than tightly packed. The Thread ID has bits indicating
484 * which subslice, EU within a subslice, and thread within an EU it
485 * is. There's a maximum of two slices and two subslices, so these
486 * can be stored with a single bit. Even though there are only 10 EUs
487 * per subslice, this is stored in 4 bits, so there's an effective
488 * maximum value of 16 EUs. Similarly, although there are only 7
489 * threads per EU, this is stored in a 3 bit number, giving an
490 * effective maximum value of 8 threads per EU.
492 * This means that we need to use 16 * 8 instead of 10 * 7 for the
493 * number of threads per subslice.
495 scratch_ids_per_subslice
= 16 * 8;
496 } else if (devinfo
->is_cherryview
) {
497 /* Cherryview devices have either 6 or 8 EUs per subslice, and each
498 * EU has 7 threads. The 6 EU devices appear to calculate thread IDs
499 * as if it had 8 EUs.
501 scratch_ids_per_subslice
= 8 * 7;
503 scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
506 thread_count
= scratch_ids_per_subslice
* subslices
;
510 unreachable("Unsupported stage!");
513 stage_state
->scratch_bo
=
514 brw_bo_alloc(brw
->bufmgr
, "shader scratch space",
515 per_thread_size
* thread_count
, BRW_MEMZONE_SCRATCH
);
518 void brwInitFragProgFuncs( struct dd_function_table
*functions
)
520 assert(functions
->ProgramStringNotify
== _tnl_program_string
);
522 functions
->NewProgram
= brwNewProgram
;
523 functions
->DeleteProgram
= brwDeleteProgram
;
524 functions
->ProgramStringNotify
= brwProgramStringNotify
;
526 functions
->LinkShader
= brw_link_shader
;
528 functions
->MemoryBarrier
= brw_memory_barrier
;
529 functions
->FramebufferFetchBarrier
= brw_framebuffer_fetch_barrier
;
532 struct shader_times
{
539 brw_init_shader_time(struct brw_context
*brw
)
541 const int max_entries
= 2048;
542 brw
->shader_time
.bo
=
543 brw_bo_alloc(brw
->bufmgr
, "shader time",
544 max_entries
* BRW_SHADER_TIME_STRIDE
* 3,
546 brw
->shader_time
.names
= rzalloc_array(brw
, const char *, max_entries
);
547 brw
->shader_time
.ids
= rzalloc_array(brw
, int, max_entries
);
548 brw
->shader_time
.types
= rzalloc_array(brw
, enum shader_time_shader_type
,
550 brw
->shader_time
.cumulative
= rzalloc_array(brw
, struct shader_times
,
552 brw
->shader_time
.max_entries
= max_entries
;
556 compare_time(const void *a
, const void *b
)
558 uint64_t * const *a_val
= a
;
559 uint64_t * const *b_val
= b
;
561 /* We don't just subtract because we're turning the value to an int. */
562 if (**a_val
< **b_val
)
564 else if (**a_val
== **b_val
)
571 print_shader_time_line(const char *stage
, const char *name
,
572 int shader_num
, uint64_t time
, uint64_t total
)
574 fprintf(stderr
, "%-6s%-18s", stage
, name
);
577 fprintf(stderr
, "%4d: ", shader_num
);
579 fprintf(stderr
, " : ");
581 fprintf(stderr
, "%16lld (%7.2f Gcycles) %4.1f%%\n",
583 (double)time
/ 1000000000.0,
584 (double)time
/ total
* 100.0);
588 brw_report_shader_time(struct brw_context
*brw
)
590 if (!brw
->shader_time
.bo
|| !brw
->shader_time
.num_entries
)
593 uint64_t scaled
[brw
->shader_time
.num_entries
];
594 uint64_t *sorted
[brw
->shader_time
.num_entries
];
595 uint64_t total_by_type
[ST_CS
+ 1];
596 memset(total_by_type
, 0, sizeof(total_by_type
));
598 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
599 uint64_t written
= 0, reset
= 0;
600 enum shader_time_shader_type type
= brw
->shader_time
.types
[i
];
602 sorted
[i
] = &scaled
[i
];
613 written
= brw
->shader_time
.cumulative
[i
].written
;
614 reset
= brw
->shader_time
.cumulative
[i
].reset
;
618 /* I sometimes want to print things that aren't the 3 shader times.
619 * Just print the sum in that case.
626 uint64_t time
= brw
->shader_time
.cumulative
[i
].time
;
628 scaled
[i
] = time
/ written
* (written
+ reset
);
642 total_by_type
[type
] += scaled
[i
];
652 fprintf(stderr
, "No shader time collected yet\n");
656 qsort(sorted
, brw
->shader_time
.num_entries
, sizeof(sorted
[0]), compare_time
);
658 fprintf(stderr
, "\n");
659 fprintf(stderr
, "type ID cycles spent %% of total\n");
660 for (int s
= 0; s
< brw
->shader_time
.num_entries
; s
++) {
662 /* Work back from the sorted pointers times to a time to print. */
663 int i
= sorted
[s
] - scaled
;
668 int shader_num
= brw
->shader_time
.ids
[i
];
669 const char *shader_name
= brw
->shader_time
.names
[i
];
671 switch (brw
->shader_time
.types
[i
]) {
701 print_shader_time_line(stage
, shader_name
, shader_num
,
705 fprintf(stderr
, "\n");
706 print_shader_time_line("total", "vs", 0, total_by_type
[ST_VS
], total
);
707 print_shader_time_line("total", "tcs", 0, total_by_type
[ST_TCS
], total
);
708 print_shader_time_line("total", "tes", 0, total_by_type
[ST_TES
], total
);
709 print_shader_time_line("total", "gs", 0, total_by_type
[ST_GS
], total
);
710 print_shader_time_line("total", "fs8", 0, total_by_type
[ST_FS8
], total
);
711 print_shader_time_line("total", "fs16", 0, total_by_type
[ST_FS16
], total
);
712 print_shader_time_line("total", "fs32", 0, total_by_type
[ST_FS32
], total
);
713 print_shader_time_line("total", "cs", 0, total_by_type
[ST_CS
], total
);
717 brw_collect_shader_time(struct brw_context
*brw
)
719 if (!brw
->shader_time
.bo
)
722 /* This probably stalls on the last rendering. We could fix that by
723 * delaying reading the reports, but it doesn't look like it's a big
724 * overhead compared to the cost of tracking the time in the first place.
726 void *bo_map
= brw_bo_map(brw
, brw
->shader_time
.bo
, MAP_READ
| MAP_WRITE
);
728 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
729 uint32_t *times
= bo_map
+ i
* 3 * BRW_SHADER_TIME_STRIDE
;
731 brw
->shader_time
.cumulative
[i
].time
+= times
[BRW_SHADER_TIME_STRIDE
* 0 / 4];
732 brw
->shader_time
.cumulative
[i
].written
+= times
[BRW_SHADER_TIME_STRIDE
* 1 / 4];
733 brw
->shader_time
.cumulative
[i
].reset
+= times
[BRW_SHADER_TIME_STRIDE
* 2 / 4];
736 /* Zero the BO out to clear it out for our next collection.
738 memset(bo_map
, 0, brw
->shader_time
.bo
->size
);
739 brw_bo_unmap(brw
->shader_time
.bo
);
743 brw_collect_and_report_shader_time(struct brw_context
*brw
)
745 brw_collect_shader_time(brw
);
747 if (brw
->shader_time
.report_time
== 0 ||
748 get_time() - brw
->shader_time
.report_time
>= 1.0) {
749 brw_report_shader_time(brw
);
750 brw
->shader_time
.report_time
= get_time();
755 * Chooses an index in the shader_time buffer and sets up tracking information
758 * Note that this holds on to references to the underlying programs, which may
759 * change their lifetimes compared to normal operation.
762 brw_get_shader_time_index(struct brw_context
*brw
, struct gl_program
*prog
,
763 enum shader_time_shader_type type
, bool is_glsl_sh
)
765 int shader_time_index
= brw
->shader_time
.num_entries
++;
766 assert(shader_time_index
< brw
->shader_time
.max_entries
);
767 brw
->shader_time
.types
[shader_time_index
] = type
;
772 } else if (is_glsl_sh
) {
773 name
= prog
->info
.label
?
774 ralloc_strdup(brw
->shader_time
.names
, prog
->info
.label
) : "glsl";
779 brw
->shader_time
.names
[shader_time_index
] = name
;
780 brw
->shader_time
.ids
[shader_time_index
] = prog
->Id
;
782 return shader_time_index
;
786 brw_destroy_shader_time(struct brw_context
*brw
)
788 brw_bo_unreference(brw
->shader_time
.bo
);
789 brw
->shader_time
.bo
= NULL
;
793 brw_stage_prog_data_free(const void *p
)
795 struct brw_stage_prog_data
*prog_data
= (struct brw_stage_prog_data
*)p
;
797 ralloc_free(prog_data
->param
);
798 ralloc_free(prog_data
->pull_param
);
802 brw_dump_arb_asm(const char *stage
, struct gl_program
*prog
)
804 fprintf(stderr
, "ARB_%s_program %d ir for native %s shader\n",
805 stage
, prog
->Id
, stage
);
806 _mesa_print_program(prog
);
810 brw_setup_tex_for_precompile(const struct gen_device_info
*devinfo
,
811 struct brw_sampler_prog_key_data
*tex
,
812 struct gl_program
*prog
)
814 const bool has_shader_channel_select
= devinfo
->is_haswell
|| devinfo
->gen
>= 8;
815 unsigned sampler_count
= util_last_bit(prog
->SamplersUsed
);
816 for (unsigned i
= 0; i
< sampler_count
; i
++) {
817 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
818 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
820 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
822 /* Color sampler: assume no swizzling. */
823 tex
->swizzles
[i
] = SWIZZLE_XYZW
;
829 * Sets up the starting offsets for the groups of binding table entries
830 * common to all pipeline stages.
832 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
833 * unused but also make sure that addition of small offsets to them will
834 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
837 brw_assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
838 const struct gl_program
*prog
,
839 struct brw_stage_prog_data
*stage_prog_data
,
840 uint32_t next_binding_table_offset
)
842 int num_textures
= util_last_bit(prog
->SamplersUsed
);
844 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
845 next_binding_table_offset
+= num_textures
;
847 if (prog
->info
.num_ubos
) {
848 assert(prog
->info
.num_ubos
<= BRW_MAX_UBO
);
849 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
850 next_binding_table_offset
+= prog
->info
.num_ubos
;
852 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
855 if (prog
->info
.num_ssbos
|| prog
->info
.num_abos
) {
856 assert(prog
->info
.num_abos
<= BRW_MAX_ABO
);
857 assert(prog
->info
.num_ssbos
<= BRW_MAX_SSBO
);
858 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
859 next_binding_table_offset
+= prog
->info
.num_abos
+ prog
->info
.num_ssbos
;
861 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
864 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
865 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
866 next_binding_table_offset
++;
868 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
871 if (prog
->info
.uses_texture_gather
) {
872 if (devinfo
->gen
>= 8) {
873 stage_prog_data
->binding_table
.gather_texture_start
=
874 stage_prog_data
->binding_table
.texture_start
;
876 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
877 next_binding_table_offset
+= num_textures
;
880 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
883 if (prog
->info
.num_images
) {
884 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
885 next_binding_table_offset
+= prog
->info
.num_images
;
887 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
890 /* This may or may not be used depending on how the compile goes. */
891 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
892 next_binding_table_offset
++;
894 /* Plane 0 is just the regular texture section */
895 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
897 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
898 next_binding_table_offset
+= num_textures
;
900 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
901 next_binding_table_offset
+= num_textures
;
903 /* Set the binding table size. Some callers may append new entries
904 * and increase this accordingly.
906 stage_prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
908 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
909 return next_binding_table_offset
;
913 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage stage
,
916 static const unsigned stage_offsets
[] = {
917 offsetof(struct brw_vs_prog_key
, program_string_id
),
918 offsetof(struct brw_tcs_prog_key
, program_string_id
),
919 offsetof(struct brw_tes_prog_key
, program_string_id
),
920 offsetof(struct brw_gs_prog_key
, program_string_id
),
921 offsetof(struct brw_wm_prog_key
, program_string_id
),
922 offsetof(struct brw_cs_prog_key
, program_string_id
),
924 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_offsets
));
925 *(unsigned*)((uint8_t*)key
+ stage_offsets
[stage
]) = id
;
929 brw_populate_default_key(const struct gen_device_info
*devinfo
,
930 union brw_any_prog_key
*prog_key
,
931 struct gl_shader_program
*sh_prog
,
932 struct gl_program
*prog
)
934 switch (prog
->info
.stage
) {
935 case MESA_SHADER_VERTEX
:
936 brw_vs_populate_default_key(devinfo
, &prog_key
->vs
, prog
);
938 case MESA_SHADER_TESS_CTRL
:
939 brw_tcs_populate_default_key(devinfo
, &prog_key
->tcs
, sh_prog
, prog
);
941 case MESA_SHADER_TESS_EVAL
:
942 brw_tes_populate_default_key(devinfo
, &prog_key
->tes
, sh_prog
, prog
);
944 case MESA_SHADER_GEOMETRY
:
945 brw_gs_populate_default_key(devinfo
, &prog_key
->gs
, prog
);
947 case MESA_SHADER_FRAGMENT
:
948 brw_wm_populate_default_key(devinfo
, &prog_key
->wm
, prog
);
950 case MESA_SHADER_COMPUTE
:
951 brw_cs_populate_default_key(devinfo
, &prog_key
->cs
, prog
);
954 unreachable("Unsupported stage!");