2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/imports.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_to_nir.h"
37 #include "program/program.h"
38 #include "program/programopt.h"
40 #include "util/ralloc.h"
41 #include "compiler/glsl/ir.h"
42 #include "compiler/glsl/glsl_to_nir.h"
43 #include "compiler/nir/nir_serialize.h"
45 #include "brw_program.h"
46 #include "brw_context.h"
47 #include "compiler/brw_nir.h"
48 #include "brw_defines.h"
49 #include "intel_batchbuffer.h"
52 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
55 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
56 type_size_scalar_bytes
);
57 return nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
, 0);
59 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
60 type_size_vec4_bytes
);
61 return nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
, 0);
66 brw_create_nir(struct brw_context
*brw
,
67 const struct gl_shader_program
*shader_prog
,
68 struct gl_program
*prog
,
69 gl_shader_stage stage
,
72 struct gl_context
*ctx
= &brw
->ctx
;
73 const nir_shader_compiler_options
*options
=
74 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
77 /* First, lower the GLSL IR or Mesa IR to NIR */
79 nir
= glsl_to_nir(shader_prog
, stage
, options
);
80 nir_remove_dead_variables(nir
, nir_var_shader_in
| nir_var_shader_out
);
81 nir_lower_returns(nir
);
82 nir_validate_shader(nir
);
83 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
84 nir_shader_get_entrypoint(nir
), true, false);
86 nir
= prog_to_nir(prog
, options
);
87 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
); /* turn registers into SSA */
89 nir_validate_shader(nir
);
91 nir
= brw_preprocess_nir(brw
->screen
->compiler
, nir
);
93 if (stage
== MESA_SHADER_FRAGMENT
) {
94 static const struct nir_lower_wpos_ytransform_options wpos_options
= {
95 .state_tokens
= {STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0},
96 .fs_coord_pixel_center_integer
= 1,
97 .fs_coord_origin_upper_left
= 1,
100 bool progress
= false;
101 NIR_PASS(progress
, nir
, nir_lower_wpos_ytransform
, &wpos_options
);
103 _mesa_add_state_reference(prog
->Parameters
,
104 (gl_state_index
*) wpos_options
.state_tokens
);
108 NIR_PASS_V(nir
, brw_nir_lower_uniforms
, is_scalar
);
114 brw_shader_gather_info(nir_shader
*nir
, struct gl_program
*prog
)
116 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
118 /* Copy the info we just generated back into the gl_program */
119 const char *prog_name
= prog
->info
.name
;
120 const char *prog_label
= prog
->info
.label
;
121 prog
->info
= nir
->info
;
122 prog
->info
.name
= prog_name
;
123 prog
->info
.label
= prog_label
;
127 get_new_program_id(struct intel_screen
*screen
)
129 return p_atomic_inc_return(&screen
->program_id
);
132 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
133 GLuint id
, bool is_arb_asm
)
135 struct brw_context
*brw
= brw_context(ctx
);
136 struct brw_program
*prog
= rzalloc(NULL
, struct brw_program
);
139 prog
->id
= get_new_program_id(brw
->screen
);
141 return _mesa_init_gl_program(&prog
->program
, target
, id
, is_arb_asm
);
147 static void brwDeleteProgram( struct gl_context
*ctx
,
148 struct gl_program
*prog
)
150 struct brw_context
*brw
= brw_context(ctx
);
152 /* Beware! prog's refcount has reached zero, and it's about to be freed.
154 * In brw_upload_pipeline_state(), we compare brw->programs[i] to
155 * ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
156 * pointer has changed.
158 * We cannot leave brw->programs[i] as a dangling pointer to the dead
159 * program. malloc() may allocate the same memory for a new gl_program,
160 * causing us to see matching pointers...but totally different programs.
162 * We cannot set brw->programs[i] to NULL, either. If we've deleted the
163 * active program, Mesa may set ctx->FooProgram._Current to NULL. That
164 * would cause us to see matching pointers (NULL == NULL), and fail to
165 * detect that a program has changed since our last draw.
167 * So, set it to a bogus gl_program pointer that will never match,
168 * causing us to properly reevaluate the state on our next draw.
170 * Getting this wrong causes heisenbugs which are very hard to catch,
171 * as you need a very specific allocation pattern to hit the problem.
173 static const struct gl_program deleted_program
;
175 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
176 if (brw
->programs
[i
] == prog
)
177 brw
->programs
[i
] = (struct gl_program
*) &deleted_program
;
180 _mesa_delete_program( ctx
, prog
);
185 brwProgramStringNotify(struct gl_context
*ctx
,
187 struct gl_program
*prog
)
189 assert(target
== GL_VERTEX_PROGRAM_ARB
|| !prog
->arb
.IsPositionInvariant
);
191 struct brw_context
*brw
= brw_context(ctx
);
192 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
195 case GL_FRAGMENT_PROGRAM_ARB
: {
196 struct brw_program
*newFP
= brw_program(prog
);
197 const struct brw_program
*curFP
=
198 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
201 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
202 newFP
->id
= get_new_program_id(brw
->screen
);
204 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_FRAGMENT
, true);
206 brw_shader_gather_info(prog
->nir
, prog
);
208 brw_fs_precompile(ctx
, prog
);
211 case GL_VERTEX_PROGRAM_ARB
: {
212 struct brw_program
*newVP
= brw_program(prog
);
213 const struct brw_program
*curVP
=
214 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
217 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
218 if (newVP
->program
.arb
.IsPositionInvariant
) {
219 _mesa_insert_mvp_code(ctx
, &newVP
->program
);
221 newVP
->id
= get_new_program_id(brw
->screen
);
223 /* Also tell tnl about it:
225 _tnl_program_string(ctx
, target
, prog
);
227 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_VERTEX
,
228 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
230 brw_shader_gather_info(prog
->nir
, prog
);
232 brw_vs_precompile(ctx
, prog
);
237 * driver->ProgramStringNotify is only called for ARB programs, fixed
238 * function vertex programs, and ir_to_mesa (which isn't used by the
239 * i965 back-end). Therefore, even after geometry shaders are added,
240 * this function should only ever be called with a target of
241 * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
243 unreachable("Unexpected target in brwProgramStringNotify");
250 brw_memory_barrier(struct gl_context
*ctx
, GLbitfield barriers
)
252 struct brw_context
*brw
= brw_context(ctx
);
253 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
254 unsigned bits
= (PIPE_CONTROL_DATA_CACHE_FLUSH
|
255 PIPE_CONTROL_NO_WRITE
|
256 PIPE_CONTROL_CS_STALL
);
257 assert(devinfo
->gen
>= 7 && devinfo
->gen
<= 10);
259 if (barriers
& (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT
|
260 GL_ELEMENT_ARRAY_BARRIER_BIT
|
261 GL_COMMAND_BARRIER_BIT
))
262 bits
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
264 if (barriers
& GL_UNIFORM_BARRIER_BIT
)
265 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
266 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
268 if (barriers
& GL_TEXTURE_FETCH_BARRIER_BIT
)
269 bits
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
271 if (barriers
& (GL_TEXTURE_UPDATE_BARRIER_BIT
|
272 GL_PIXEL_BUFFER_BARRIER_BIT
))
273 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
274 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
276 if (barriers
& GL_FRAMEBUFFER_BARRIER_BIT
)
277 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
278 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
280 /* Typed surface messages are handled by the render cache on IVB, so we
281 * need to flush it too.
283 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
284 bits
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
286 brw_emit_pipe_control_flush(brw
, bits
);
290 brw_blend_barrier(struct gl_context
*ctx
)
292 struct brw_context
*brw
= brw_context(ctx
);
293 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
295 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
) {
296 if (devinfo
->gen
>= 6) {
297 brw_emit_pipe_control_flush(brw
,
298 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
299 PIPE_CONTROL_CS_STALL
);
300 brw_emit_pipe_control_flush(brw
,
301 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
303 brw_emit_pipe_control_flush(brw
,
304 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
310 brw_get_scratch_bo(struct brw_context
*brw
,
311 struct brw_bo
**scratch_bo
, int size
)
313 struct brw_bo
*old_bo
= *scratch_bo
;
315 if (old_bo
&& old_bo
->size
< size
) {
316 brw_bo_unreference(old_bo
);
321 *scratch_bo
= brw_bo_alloc(brw
->bufmgr
, "scratch bo", size
, 4096);
326 * Reserve enough scratch space for the given stage to hold \p per_thread_size
327 * bytes times the given \p thread_count.
330 brw_alloc_stage_scratch(struct brw_context
*brw
,
331 struct brw_stage_state
*stage_state
,
332 unsigned per_thread_size
)
334 if (stage_state
->per_thread_scratch
>= per_thread_size
)
337 stage_state
->per_thread_scratch
= per_thread_size
;
339 if (stage_state
->scratch_bo
)
340 brw_bo_unreference(stage_state
->scratch_bo
);
342 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
343 unsigned thread_count
;
344 switch(stage_state
->stage
) {
345 case MESA_SHADER_VERTEX
:
346 thread_count
= devinfo
->max_vs_threads
;
348 case MESA_SHADER_TESS_CTRL
:
349 thread_count
= devinfo
->max_tcs_threads
;
351 case MESA_SHADER_TESS_EVAL
:
352 thread_count
= devinfo
->max_tes_threads
;
354 case MESA_SHADER_GEOMETRY
:
355 thread_count
= devinfo
->max_gs_threads
;
357 case MESA_SHADER_FRAGMENT
:
358 thread_count
= devinfo
->max_wm_threads
;
360 case MESA_SHADER_COMPUTE
: {
361 unsigned subslices
= MAX2(brw
->screen
->subslice_total
, 1);
363 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
365 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
366 * allocate scratch space enough so that each slice has 4 slices
369 * According to the other driver team, this applies to compute shaders
370 * as well. This is not currently documented at all.
372 if (devinfo
->gen
>= 9)
375 /* WaCSScratchSize:hsw
377 * Haswell's scratch space address calculation appears to be sparse
378 * rather than tightly packed. The Thread ID has bits indicating
379 * which subslice, EU within a subslice, and thread within an EU
380 * it is. There's a maximum of two slices and two subslices, so these
381 * can be stored with a single bit. Even though there are only 10 EUs
382 * per subslice, this is stored in 4 bits, so there's an effective
383 * maximum value of 16 EUs. Similarly, although there are only 7
384 * threads per EU, this is stored in a 3 bit number, giving an effective
385 * maximum value of 8 threads per EU.
387 * This means that we need to use 16 * 8 instead of 10 * 7 for the
388 * number of threads per subslice.
390 const unsigned scratch_ids_per_subslice
=
391 devinfo
->is_haswell
? 16 * 8 : devinfo
->max_cs_threads
;
393 thread_count
= scratch_ids_per_subslice
* subslices
;
397 unreachable("Unsupported stage!");
400 stage_state
->scratch_bo
=
401 brw_bo_alloc(brw
->bufmgr
, "shader scratch space",
402 per_thread_size
* thread_count
, 4096);
405 void brwInitFragProgFuncs( struct dd_function_table
*functions
)
407 assert(functions
->ProgramStringNotify
== _tnl_program_string
);
409 functions
->NewProgram
= brwNewProgram
;
410 functions
->DeleteProgram
= brwDeleteProgram
;
411 functions
->ProgramStringNotify
= brwProgramStringNotify
;
413 functions
->LinkShader
= brw_link_shader
;
415 functions
->MemoryBarrier
= brw_memory_barrier
;
416 functions
->BlendBarrier
= brw_blend_barrier
;
419 struct shader_times
{
426 brw_init_shader_time(struct brw_context
*brw
)
428 const int max_entries
= 2048;
429 brw
->shader_time
.bo
=
430 brw_bo_alloc(brw
->bufmgr
, "shader time",
431 max_entries
* BRW_SHADER_TIME_STRIDE
* 3, 4096);
432 brw
->shader_time
.names
= rzalloc_array(brw
, const char *, max_entries
);
433 brw
->shader_time
.ids
= rzalloc_array(brw
, int, max_entries
);
434 brw
->shader_time
.types
= rzalloc_array(brw
, enum shader_time_shader_type
,
436 brw
->shader_time
.cumulative
= rzalloc_array(brw
, struct shader_times
,
438 brw
->shader_time
.max_entries
= max_entries
;
442 compare_time(const void *a
, const void *b
)
444 uint64_t * const *a_val
= a
;
445 uint64_t * const *b_val
= b
;
447 /* We don't just subtract because we're turning the value to an int. */
448 if (**a_val
< **b_val
)
450 else if (**a_val
== **b_val
)
457 print_shader_time_line(const char *stage
, const char *name
,
458 int shader_num
, uint64_t time
, uint64_t total
)
460 fprintf(stderr
, "%-6s%-18s", stage
, name
);
463 fprintf(stderr
, "%4d: ", shader_num
);
465 fprintf(stderr
, " : ");
467 fprintf(stderr
, "%16lld (%7.2f Gcycles) %4.1f%%\n",
469 (double)time
/ 1000000000.0,
470 (double)time
/ total
* 100.0);
474 brw_report_shader_time(struct brw_context
*brw
)
476 if (!brw
->shader_time
.bo
|| !brw
->shader_time
.num_entries
)
479 uint64_t scaled
[brw
->shader_time
.num_entries
];
480 uint64_t *sorted
[brw
->shader_time
.num_entries
];
481 uint64_t total_by_type
[ST_CS
+ 1];
482 memset(total_by_type
, 0, sizeof(total_by_type
));
484 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
485 uint64_t written
= 0, reset
= 0;
486 enum shader_time_shader_type type
= brw
->shader_time
.types
[i
];
488 sorted
[i
] = &scaled
[i
];
498 written
= brw
->shader_time
.cumulative
[i
].written
;
499 reset
= brw
->shader_time
.cumulative
[i
].reset
;
503 /* I sometimes want to print things that aren't the 3 shader times.
504 * Just print the sum in that case.
511 uint64_t time
= brw
->shader_time
.cumulative
[i
].time
;
513 scaled
[i
] = time
/ written
* (written
+ reset
);
526 total_by_type
[type
] += scaled
[i
];
536 fprintf(stderr
, "No shader time collected yet\n");
540 qsort(sorted
, brw
->shader_time
.num_entries
, sizeof(sorted
[0]), compare_time
);
542 fprintf(stderr
, "\n");
543 fprintf(stderr
, "type ID cycles spent %% of total\n");
544 for (int s
= 0; s
< brw
->shader_time
.num_entries
; s
++) {
546 /* Work back from the sorted pointers times to a time to print. */
547 int i
= sorted
[s
] - scaled
;
552 int shader_num
= brw
->shader_time
.ids
[i
];
553 const char *shader_name
= brw
->shader_time
.names
[i
];
555 switch (brw
->shader_time
.types
[i
]) {
582 print_shader_time_line(stage
, shader_name
, shader_num
,
586 fprintf(stderr
, "\n");
587 print_shader_time_line("total", "vs", 0, total_by_type
[ST_VS
], total
);
588 print_shader_time_line("total", "tcs", 0, total_by_type
[ST_TCS
], total
);
589 print_shader_time_line("total", "tes", 0, total_by_type
[ST_TES
], total
);
590 print_shader_time_line("total", "gs", 0, total_by_type
[ST_GS
], total
);
591 print_shader_time_line("total", "fs8", 0, total_by_type
[ST_FS8
], total
);
592 print_shader_time_line("total", "fs16", 0, total_by_type
[ST_FS16
], total
);
593 print_shader_time_line("total", "cs", 0, total_by_type
[ST_CS
], total
);
597 brw_collect_shader_time(struct brw_context
*brw
)
599 if (!brw
->shader_time
.bo
)
602 /* This probably stalls on the last rendering. We could fix that by
603 * delaying reading the reports, but it doesn't look like it's a big
604 * overhead compared to the cost of tracking the time in the first place.
606 void *bo_map
= brw_bo_map(brw
, brw
->shader_time
.bo
, MAP_READ
| MAP_WRITE
);
608 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
609 uint32_t *times
= bo_map
+ i
* 3 * BRW_SHADER_TIME_STRIDE
;
611 brw
->shader_time
.cumulative
[i
].time
+= times
[BRW_SHADER_TIME_STRIDE
* 0 / 4];
612 brw
->shader_time
.cumulative
[i
].written
+= times
[BRW_SHADER_TIME_STRIDE
* 1 / 4];
613 brw
->shader_time
.cumulative
[i
].reset
+= times
[BRW_SHADER_TIME_STRIDE
* 2 / 4];
616 /* Zero the BO out to clear it out for our next collection.
618 memset(bo_map
, 0, brw
->shader_time
.bo
->size
);
619 brw_bo_unmap(brw
->shader_time
.bo
);
623 brw_collect_and_report_shader_time(struct brw_context
*brw
)
625 brw_collect_shader_time(brw
);
627 if (brw
->shader_time
.report_time
== 0 ||
628 get_time() - brw
->shader_time
.report_time
>= 1.0) {
629 brw_report_shader_time(brw
);
630 brw
->shader_time
.report_time
= get_time();
635 * Chooses an index in the shader_time buffer and sets up tracking information
638 * Note that this holds on to references to the underlying programs, which may
639 * change their lifetimes compared to normal operation.
642 brw_get_shader_time_index(struct brw_context
*brw
, struct gl_program
*prog
,
643 enum shader_time_shader_type type
, bool is_glsl_sh
)
645 int shader_time_index
= brw
->shader_time
.num_entries
++;
646 assert(shader_time_index
< brw
->shader_time
.max_entries
);
647 brw
->shader_time
.types
[shader_time_index
] = type
;
652 } else if (is_glsl_sh
) {
653 name
= prog
->info
.label
?
654 ralloc_strdup(brw
->shader_time
.names
, prog
->info
.label
) : "glsl";
659 brw
->shader_time
.names
[shader_time_index
] = name
;
660 brw
->shader_time
.ids
[shader_time_index
] = prog
->Id
;
662 return shader_time_index
;
666 brw_destroy_shader_time(struct brw_context
*brw
)
668 brw_bo_unreference(brw
->shader_time
.bo
);
669 brw
->shader_time
.bo
= NULL
;
673 brw_stage_prog_data_free(const void *p
)
675 struct brw_stage_prog_data
*prog_data
= (struct brw_stage_prog_data
*)p
;
677 ralloc_free(prog_data
->param
);
678 ralloc_free(prog_data
->pull_param
);
682 brw_dump_arb_asm(const char *stage
, struct gl_program
*prog
)
684 fprintf(stderr
, "ARB_%s_program %d ir for native %s shader\n",
685 stage
, prog
->Id
, stage
);
686 _mesa_print_program(prog
);
690 brw_setup_tex_for_precompile(struct brw_context
*brw
,
691 struct brw_sampler_prog_key_data
*tex
,
692 struct gl_program
*prog
)
694 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
695 const bool has_shader_channel_select
= devinfo
->is_haswell
|| devinfo
->gen
>= 8;
696 unsigned sampler_count
= util_last_bit(prog
->SamplersUsed
);
697 for (unsigned i
= 0; i
< sampler_count
; i
++) {
698 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
699 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
701 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
703 /* Color sampler: assume no swizzling. */
704 tex
->swizzles
[i
] = SWIZZLE_XYZW
;
710 * Sets up the starting offsets for the groups of binding table entries
711 * common to all pipeline stages.
713 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
714 * unused but also make sure that addition of small offsets to them will
715 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
718 brw_assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
719 const struct gl_program
*prog
,
720 struct brw_stage_prog_data
*stage_prog_data
,
721 uint32_t next_binding_table_offset
)
723 int num_textures
= util_last_bit(prog
->SamplersUsed
);
725 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
726 next_binding_table_offset
+= num_textures
;
728 if (prog
->info
.num_ubos
) {
729 assert(prog
->info
.num_ubos
<= BRW_MAX_UBO
);
730 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
731 next_binding_table_offset
+= prog
->info
.num_ubos
;
733 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
736 if (prog
->info
.num_ssbos
|| prog
->info
.num_abos
) {
737 assert(prog
->info
.num_abos
<= BRW_MAX_ABO
);
738 assert(prog
->info
.num_ssbos
<= BRW_MAX_SSBO
);
739 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
740 next_binding_table_offset
+= prog
->info
.num_abos
+ prog
->info
.num_ssbos
;
742 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
745 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
746 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
747 next_binding_table_offset
++;
749 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
752 if (prog
->info
.uses_texture_gather
) {
753 if (devinfo
->gen
>= 8) {
754 stage_prog_data
->binding_table
.gather_texture_start
=
755 stage_prog_data
->binding_table
.texture_start
;
757 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
758 next_binding_table_offset
+= num_textures
;
761 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
764 if (prog
->info
.num_images
) {
765 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
766 next_binding_table_offset
+= prog
->info
.num_images
;
768 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
771 /* This may or may not be used depending on how the compile goes. */
772 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
773 next_binding_table_offset
++;
775 /* Plane 0 is just the regular texture section */
776 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
778 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
779 next_binding_table_offset
+= num_textures
;
781 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
782 next_binding_table_offset
+= num_textures
;
784 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
786 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
787 return next_binding_table_offset
;
791 brw_program_deserialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
,
792 gl_shader_stage stage
)
795 assert(prog
->driver_cache_blob
&& prog
->driver_cache_blob_size
> 0);
796 const struct nir_shader_compiler_options
*options
=
797 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
798 struct blob_reader reader
;
799 blob_reader_init(&reader
, prog
->driver_cache_blob
,
800 prog
->driver_cache_blob_size
);
801 prog
->nir
= nir_deserialize(NULL
, options
, &reader
);
804 if (prog
->driver_cache_blob
) {
805 ralloc_free(prog
->driver_cache_blob
);
806 prog
->driver_cache_blob
= NULL
;
807 prog
->driver_cache_blob_size
= 0;