src/mesa/drivers/dri/i965/brw_reg.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 /** @file brw_reg.h
  33  *
  34  * This file defines struct brw_reg, which is our representation for EU
  35  * registers.  They're not a hardware specific format, just an abstraction
  36  * that intends to capture the full flexibility of the hardware registers.
  37  *
  38  * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
  39  * the abstract brw_reg type into the actual hardware instruction encoding.
  40  */
  41
  42 #ifndef BRW_REG_H
  43 #define BRW_REG_H
  44
  45 #include <stdbool.h>
  46 #include "program/prog_instruction.h"
  47 #include "brw_defines.h"
  48
  49 #ifdef __cplusplus
  50 extern "C" {
  51 #endif
  52
  53 /** Number of general purpose registers (VS, WM, etc) */
  54 #define BRW_MAX_GRF 128
  55
  56 /**
  57  * First GRF used for the MRF hack.
  58  *
  59  * On gen7, MRFs are no longer used, and contiguous GRFs are used instead.  We
  60  * haven't converted our compiler to be aware of this, so it asks for MRFs and
  61  * brw_eu_emit.c quietly converts them to be accesses of the top GRFs.  The
  62  * register allocators have to be careful of this to avoid corrupting the "MRF"s
  63  * with actual GRF allocations.
  64  */
  65 #define GEN7_MRF_HACK_START 112
  66
  67 /** Number of message register file registers */
  68 #define BRW_MAX_MRF 16
  69
  70 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
  71 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
  72
  73 #define BRW_SWIZZLE_NOOP      BRW_SWIZZLE4(0,1,2,3)
  74 #define BRW_SWIZZLE_XYZW      BRW_SWIZZLE4(0,1,2,3)
  75 #define BRW_SWIZZLE_XXXX      BRW_SWIZZLE4(0,0,0,0)
  76 #define BRW_SWIZZLE_YYYY      BRW_SWIZZLE4(1,1,1,1)
  77 #define BRW_SWIZZLE_ZZZZ      BRW_SWIZZLE4(2,2,2,2)
  78 #define BRW_SWIZZLE_WWWW      BRW_SWIZZLE4(3,3,3,3)
  79 #define BRW_SWIZZLE_XYXY      BRW_SWIZZLE4(0,1,0,1)
  80
  81 static inline bool
  82 brw_is_single_value_swizzle(int swiz)
  83 {
  84    return (swiz == BRW_SWIZZLE_XXXX ||
  85            swiz == BRW_SWIZZLE_YYYY ||
  86            swiz == BRW_SWIZZLE_ZZZZ ||
  87            swiz == BRW_SWIZZLE_WWWW);
  88 }
  89
  90 #define REG_SIZE (8*4)
  91
  92 /* These aren't hardware structs, just something useful for us to pass around:
  93  *
  94  * Align1 operation has a lot of control over input ranges.  Used in
  95  * WM programs to implement shaders decomposed into "channel serial"
  96  * or "structure of array" form:
  97  */
  98 struct brw_reg {
  99    unsigned type:4;
 100    unsigned file:2;
 101    unsigned nr:8;
 102    unsigned subnr:5;              /* :1 in align16 */
 103    unsigned negate:1;             /* source only */
 104    unsigned abs:1;                /* source only */
 105    unsigned vstride:4;            /* source only */
 106    unsigned width:3;              /* src only, align1 only */
 107    unsigned hstride:2;            /* align1 only */
 108    unsigned address_mode:1;       /* relative addressing, hopefully! */
 109    unsigned pad0:1;
 110
 111    union {
 112       struct {
 113          unsigned swizzle:8;      /* src only, align16 only */
 114          unsigned writemask:4;    /* dest only, align16 only */
 115          int  indirect_offset:10; /* relative addressing offset */
 116          unsigned pad1:10;        /* two dwords total */
 117       } bits;
 118
 119       float f;
 120       int   d;
 121       unsigned ud;
 122    } dw1;
 123 };
 124
 125
 126 struct brw_indirect {
 127    unsigned addr_subnr:4;
 128    int addr_offset:10;
 129    unsigned pad:18;
 130 };
 131
 132
 133 static inline int
 134 type_sz(unsigned type)
 135 {
 136    switch(type) {
 137    case BRW_REGISTER_TYPE_UD:
 138    case BRW_REGISTER_TYPE_D:
 139    case BRW_REGISTER_TYPE_F:
 140       return 4;
 141    case BRW_REGISTER_TYPE_HF:
 142    case BRW_REGISTER_TYPE_UW:
 143    case BRW_REGISTER_TYPE_W:
 144       return 2;
 145    case BRW_REGISTER_TYPE_UB:
 146    case BRW_REGISTER_TYPE_B:
 147       return 1;
 148    default:
 149       return 0;
 150    }
 151 }
 152
 153 /**
 154  * Construct a brw_reg.
 155  * \param file      one of the BRW_x_REGISTER_FILE values
 156  * \param nr        register number/index
 157  * \param subnr     register sub number
 158  * \param type      one of BRW_REGISTER_TYPE_x
 159  * \param vstride   one of BRW_VERTICAL_STRIDE_x
 160  * \param width     one of BRW_WIDTH_x
 161  * \param hstride   one of BRW_HORIZONTAL_STRIDE_x
 162  * \param swizzle   one of BRW_SWIZZLE_x
 163  * \param writemask WRITEMASK_X/Y/Z/W bitfield
 164  */
 165 static inline struct brw_reg
 166 brw_reg(unsigned file,
 167         unsigned nr,
 168         unsigned subnr,
 169         unsigned type,
 170         unsigned vstride,
 171         unsigned width,
 172         unsigned hstride,
 173         unsigned swizzle,
 174         unsigned writemask)
 175 {
 176    struct brw_reg reg;
 177    if (file == BRW_GENERAL_REGISTER_FILE)
 178       assert(nr < BRW_MAX_GRF);
 179    else if (file == BRW_MESSAGE_REGISTER_FILE)
 180       assert((nr & ~(1 << 7)) < BRW_MAX_MRF);
 181    else if (file == BRW_ARCHITECTURE_REGISTER_FILE)
 182       assert(nr <= BRW_ARF_TIMESTAMP);
 183
 184    reg.type = type;
 185    reg.file = file;
 186    reg.nr = nr;
 187    reg.subnr = subnr * type_sz(type);
 188    reg.negate = 0;
 189    reg.abs = 0;
 190    reg.vstride = vstride;
 191    reg.width = width;
 192    reg.hstride = hstride;
 193    reg.address_mode = BRW_ADDRESS_DIRECT;
 194    reg.pad0 = 0;
 195
 196    /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
 197     * set swizzle and writemask to W, as the lower bits of subnr will
 198     * be lost when converted to align16.  This is probably too much to
 199     * keep track of as you'd want it adjusted by suboffset(), etc.
 200     * Perhaps fix up when converting to align16?
 201     */
 202    reg.dw1.bits.swizzle = swizzle;
 203    reg.dw1.bits.writemask = writemask;
 204    reg.dw1.bits.indirect_offset = 0;
 205    reg.dw1.bits.pad1 = 0;
 206    return reg;
 207 }
 208
 209 /** Construct float[16] register */
 210 static inline struct brw_reg
 211 brw_vec16_reg(unsigned file, unsigned nr, unsigned subnr)
 212 {
 213    return brw_reg(file,
 214                   nr,
 215                   subnr,
 216                   BRW_REGISTER_TYPE_F,
 217                   BRW_VERTICAL_STRIDE_16,
 218                   BRW_WIDTH_16,
 219                   BRW_HORIZONTAL_STRIDE_1,
 220                   BRW_SWIZZLE_XYZW,
 221                   WRITEMASK_XYZW);
 222 }
 223
 224 /** Construct float[8] register */
 225 static inline struct brw_reg
 226 brw_vec8_reg(unsigned file, unsigned nr, unsigned subnr)
 227 {
 228    return brw_reg(file,
 229                   nr,
 230                   subnr,
 231                   BRW_REGISTER_TYPE_F,
 232                   BRW_VERTICAL_STRIDE_8,
 233                   BRW_WIDTH_8,
 234                   BRW_HORIZONTAL_STRIDE_1,
 235                   BRW_SWIZZLE_XYZW,
 236                   WRITEMASK_XYZW);
 237 }
 238
 239 /** Construct float[4] register */
 240 static inline struct brw_reg
 241 brw_vec4_reg(unsigned file, unsigned nr, unsigned subnr)
 242 {
 243    return brw_reg(file,
 244                   nr,
 245                   subnr,
 246                   BRW_REGISTER_TYPE_F,
 247                   BRW_VERTICAL_STRIDE_4,
 248                   BRW_WIDTH_4,
 249                   BRW_HORIZONTAL_STRIDE_1,
 250                   BRW_SWIZZLE_XYZW,
 251                   WRITEMASK_XYZW);
 252 }
 253
 254 /** Construct float[2] register */
 255 static inline struct brw_reg
 256 brw_vec2_reg(unsigned file, unsigned nr, unsigned subnr)
 257 {
 258    return brw_reg(file,
 259                   nr,
 260                   subnr,
 261                   BRW_REGISTER_TYPE_F,
 262                   BRW_VERTICAL_STRIDE_2,
 263                   BRW_WIDTH_2,
 264                   BRW_HORIZONTAL_STRIDE_1,
 265                   BRW_SWIZZLE_XYXY,
 266                   WRITEMASK_XY);
 267 }
 268
 269 /** Construct float[1] register */
 270 static inline struct brw_reg
 271 brw_vec1_reg(unsigned file, unsigned nr, unsigned subnr)
 272 {
 273    return brw_reg(file,
 274                   nr,
 275                   subnr,
 276                   BRW_REGISTER_TYPE_F,
 277                   BRW_VERTICAL_STRIDE_0,
 278                   BRW_WIDTH_1,
 279                   BRW_HORIZONTAL_STRIDE_0,
 280                   BRW_SWIZZLE_XXXX,
 281                   WRITEMASK_X);
 282 }
 283
 284
 285 static inline struct brw_reg
 286 retype(struct brw_reg reg, unsigned type)
 287 {
 288    reg.type = type;
 289    return reg;
 290 }
 291
 292 static inline struct brw_reg
 293 sechalf(struct brw_reg reg)
 294 {
 295    if (reg.vstride)
 296       reg.nr++;
 297    return reg;
 298 }
 299
 300 static inline struct brw_reg
 301 suboffset(struct brw_reg reg, unsigned delta)
 302 {
 303    reg.subnr += delta * type_sz(reg.type);
 304    return reg;
 305 }
 306
 307
 308 static inline struct brw_reg
 309 offset(struct brw_reg reg, unsigned delta)
 310 {
 311    reg.nr += delta;
 312    return reg;
 313 }
 314
 315
 316 static inline struct brw_reg
 317 byte_offset(struct brw_reg reg, unsigned bytes)
 318 {
 319    unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
 320    reg.nr = newoffset / REG_SIZE;
 321    reg.subnr = newoffset % REG_SIZE;
 322    return reg;
 323 }
 324
 325
 326 /** Construct unsigned word[16] register */
 327 static inline struct brw_reg
 328 brw_uw16_reg(unsigned file, unsigned nr, unsigned subnr)
 329 {
 330    return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 331 }
 332
 333 /** Construct unsigned word[8] register */
 334 static inline struct brw_reg
 335 brw_uw8_reg(unsigned file, unsigned nr, unsigned subnr)
 336 {
 337    return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 338 }
 339
 340 /** Construct unsigned word[1] register */
 341 static inline struct brw_reg
 342 brw_uw1_reg(unsigned file, unsigned nr, unsigned subnr)
 343 {
 344    return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 345 }
 346
 347 static inline struct brw_reg
 348 brw_imm_reg(unsigned type)
 349 {
 350    return brw_reg(BRW_IMMEDIATE_VALUE,
 351                   0,
 352                   0,
 353                   type,
 354                   BRW_VERTICAL_STRIDE_0,
 355                   BRW_WIDTH_1,
 356                   BRW_HORIZONTAL_STRIDE_0,
 357                   0,
 358                   0);
 359 }
 360
 361 /** Construct float immediate register */
 362 static inline struct brw_reg
 363 brw_imm_f(float f)
 364 {
 365    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
 366    imm.dw1.f = f;
 367    return imm;
 368 }
 369
 370 /** Construct integer immediate register */
 371 static inline struct brw_reg
 372 brw_imm_d(int d)
 373 {
 374    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
 375    imm.dw1.d = d;
 376    return imm;
 377 }
 378
 379 /** Construct uint immediate register */
 380 static inline struct brw_reg
 381 brw_imm_ud(unsigned ud)
 382 {
 383    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
 384    imm.dw1.ud = ud;
 385    return imm;
 386 }
 387
 388 /** Construct ushort immediate register */
 389 static inline struct brw_reg
 390 brw_imm_uw(uint16_t uw)
 391 {
 392    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
 393    imm.dw1.ud = uw | (uw << 16);
 394    return imm;
 395 }
 396
 397 /** Construct short immediate register */
 398 static inline struct brw_reg
 399 brw_imm_w(int16_t w)
 400 {
 401    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
 402    imm.dw1.d = w | (w << 16);
 403    return imm;
 404 }
 405
 406 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
 407  * numbers alias with _V and _VF below:
 408  */
 409
 410 /** Construct vector of eight signed half-byte values */
 411 static inline struct brw_reg
 412 brw_imm_v(unsigned v)
 413 {
 414    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
 415    imm.vstride = BRW_VERTICAL_STRIDE_0;
 416    imm.width = BRW_WIDTH_8;
 417    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 418    imm.dw1.ud = v;
 419    return imm;
 420 }
 421
 422 /** Construct vector of four 8-bit float values */
 423 static inline struct brw_reg
 424 brw_imm_vf(unsigned v)
 425 {
 426    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 427    imm.vstride = BRW_VERTICAL_STRIDE_0;
 428    imm.width = BRW_WIDTH_4;
 429    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 430    imm.dw1.ud = v;
 431    return imm;
 432 }
 433
 434 #define VF_ZERO 0x0
 435 #define VF_ONE  0x30
 436 #define VF_NEG  (1<<7)
 437
 438 static inline struct brw_reg
 439 brw_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3)
 440 {
 441    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 442    imm.vstride = BRW_VERTICAL_STRIDE_0;
 443    imm.width = BRW_WIDTH_4;
 444    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 445    imm.dw1.ud = ((v0 << 0) | (v1 << 8) | (v2 << 16) | (v3 << 24));
 446    return imm;
 447 }
 448
 449
 450 static inline struct brw_reg
 451 brw_address(struct brw_reg reg)
 452 {
 453    return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
 454 }
 455
 456 /** Construct float[1] general-purpose register */
 457 static inline struct brw_reg
 458 brw_vec1_grf(unsigned nr, unsigned subnr)
 459 {
 460    return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 461 }
 462
 463 /** Construct float[2] general-purpose register */
 464 static inline struct brw_reg
 465 brw_vec2_grf(unsigned nr, unsigned subnr)
 466 {
 467    return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 468 }
 469
 470 /** Construct float[4] general-purpose register */
 471 static inline struct brw_reg
 472 brw_vec4_grf(unsigned nr, unsigned subnr)
 473 {
 474    return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 475 }
 476
 477 /** Construct float[8] general-purpose register */
 478 static inline struct brw_reg
 479 brw_vec8_grf(unsigned nr, unsigned subnr)
 480 {
 481    return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 482 }
 483
 484
 485 static inline struct brw_reg
 486 brw_uw8_grf(unsigned nr, unsigned subnr)
 487 {
 488    return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 489 }
 490
 491 static inline struct brw_reg
 492 brw_uw16_grf(unsigned nr, unsigned subnr)
 493 {
 494    return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 495 }
 496
 497
 498 /** Construct null register (usually used for setting condition codes) */
 499 static inline struct brw_reg
 500 brw_null_reg(void)
 501 {
 502    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0);
 503 }
 504
 505 static inline struct brw_reg
 506 brw_address_reg(unsigned subnr)
 507 {
 508    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr);
 509 }
 510
 511 /* If/else instructions break in align16 mode if writemask & swizzle
 512  * aren't xyzw.  This goes against the convention for other scalar
 513  * regs:
 514  */
 515 static inline struct brw_reg
 516 brw_ip_reg(void)
 517 {
 518    return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 519                   BRW_ARF_IP,
 520                   0,
 521                   BRW_REGISTER_TYPE_UD,
 522                   BRW_VERTICAL_STRIDE_4, /* ? */
 523                   BRW_WIDTH_1,
 524                   BRW_HORIZONTAL_STRIDE_0,
 525                   BRW_SWIZZLE_XYZW, /* NOTE! */
 526                   WRITEMASK_XYZW); /* NOTE! */
 527 }
 528
 529 static inline struct brw_reg
 530 brw_acc_reg(void)
 531 {
 532    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ACCUMULATOR, 0);
 533 }
 534
 535 static inline struct brw_reg
 536 brw_notification_1_reg(void)
 537 {
 538
 539    return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 540                   BRW_ARF_NOTIFICATION_COUNT,
 541                   1,
 542                   BRW_REGISTER_TYPE_UD,
 543                   BRW_VERTICAL_STRIDE_0,
 544                   BRW_WIDTH_1,
 545                   BRW_HORIZONTAL_STRIDE_0,
 546                   BRW_SWIZZLE_XXXX,
 547                   WRITEMASK_X);
 548 }
 549
 550
 551 static inline struct brw_reg
 552 brw_flag_reg(int reg, int subreg)
 553 {
 554    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 555                       BRW_ARF_FLAG + reg, subreg);
 556 }
 557
 558
 559 static inline struct brw_reg
 560 brw_mask_reg(unsigned subnr)
 561 {
 562    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr);
 563 }
 564
 565 static inline struct brw_reg
 566 brw_message_reg(unsigned nr)
 567 {
 568    assert((nr & ~(1 << 7)) < BRW_MAX_MRF);
 569    return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, nr, 0);
 570 }
 571
 572
 573 /* This is almost always called with a numeric constant argument, so
 574  * make things easy to evaluate at compile time:
 575  */
 576 static inline unsigned cvt(unsigned val)
 577 {
 578    switch (val) {
 579    case 0: return 0;
 580    case 1: return 1;
 581    case 2: return 2;
 582    case 4: return 3;
 583    case 8: return 4;
 584    case 16: return 5;
 585    case 32: return 6;
 586    }
 587    return 0;
 588 }
 589
 590 static inline struct brw_reg
 591 stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride)
 592 {
 593    reg.vstride = cvt(vstride);
 594    reg.width = cvt(width) - 1;
 595    reg.hstride = cvt(hstride);
 596    return reg;
 597 }
 598
 599
 600 static inline struct brw_reg
 601 vec16(struct brw_reg reg)
 602 {
 603    return stride(reg, 16,16,1);
 604 }
 605
 606 static inline struct brw_reg
 607 vec8(struct brw_reg reg)
 608 {
 609    return stride(reg, 8,8,1);
 610 }
 611
 612 static inline struct brw_reg
 613 vec4(struct brw_reg reg)
 614 {
 615    return stride(reg, 4,4,1);
 616 }
 617
 618 static inline struct brw_reg
 619 vec2(struct brw_reg reg)
 620 {
 621    return stride(reg, 2,2,1);
 622 }
 623
 624 static inline struct brw_reg
 625 vec1(struct brw_reg reg)
 626 {
 627    return stride(reg, 0,1,0);
 628 }
 629
 630
 631 static inline struct brw_reg
 632 get_element(struct brw_reg reg, unsigned elt)
 633 {
 634    return vec1(suboffset(reg, elt));
 635 }
 636
 637 static inline struct brw_reg
 638 get_element_ud(struct brw_reg reg, unsigned elt)
 639 {
 640    return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
 641 }
 642
 643 static inline struct brw_reg
 644 get_element_d(struct brw_reg reg, unsigned elt)
 645 {
 646    return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt));
 647 }
 648
 649
 650 static inline struct brw_reg
 651 brw_swizzle(struct brw_reg reg, unsigned x, unsigned y, unsigned z, unsigned w)
 652 {
 653    assert(reg.file != BRW_IMMEDIATE_VALUE);
 654
 655    reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
 656                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
 657                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
 658                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
 659    return reg;
 660 }
 661
 662
 663 static inline struct brw_reg
 664 brw_swizzle1(struct brw_reg reg, unsigned x)
 665 {
 666    return brw_swizzle(reg, x, x, x, x);
 667 }
 668
 669 static inline struct brw_reg
 670 brw_writemask(struct brw_reg reg, unsigned mask)
 671 {
 672    assert(reg.file != BRW_IMMEDIATE_VALUE);
 673    reg.dw1.bits.writemask &= mask;
 674    return reg;
 675 }
 676
 677 static inline struct brw_reg
 678 brw_set_writemask(struct brw_reg reg, unsigned mask)
 679 {
 680    assert(reg.file != BRW_IMMEDIATE_VALUE);
 681    reg.dw1.bits.writemask = mask;
 682    return reg;
 683 }
 684
 685 static inline struct brw_reg
 686 negate(struct brw_reg reg)
 687 {
 688    reg.negate ^= 1;
 689    return reg;
 690 }
 691
 692 static inline struct brw_reg
 693 brw_abs(struct brw_reg reg)
 694 {
 695    reg.abs = 1;
 696    reg.negate = 0;
 697    return reg;
 698 }
 699
 700 /************************************************************************/
 701
 702 static inline struct brw_reg
 703 brw_vec4_indirect(unsigned subnr, int offset)
 704 {
 705    struct brw_reg reg =  brw_vec4_grf(0, 0);
 706    reg.subnr = subnr;
 707    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 708    reg.dw1.bits.indirect_offset = offset;
 709    return reg;
 710 }
 711
 712 static inline struct brw_reg
 713 brw_vec1_indirect(unsigned subnr, int offset)
 714 {
 715    struct brw_reg reg =  brw_vec1_grf(0, 0);
 716    reg.subnr = subnr;
 717    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 718    reg.dw1.bits.indirect_offset = offset;
 719    return reg;
 720 }
 721
 722 static inline struct brw_reg
 723 deref_4f(struct brw_indirect ptr, int offset)
 724 {
 725    return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 726 }
 727
 728 static inline struct brw_reg
 729 deref_1f(struct brw_indirect ptr, int offset)
 730 {
 731    return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 732 }
 733
 734 static inline struct brw_reg
 735 deref_4b(struct brw_indirect ptr, int offset)
 736 {
 737    return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
 738 }
 739
 740 static inline struct brw_reg
 741 deref_1uw(struct brw_indirect ptr, int offset)
 742 {
 743    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
 744 }
 745
 746 static inline struct brw_reg
 747 deref_1d(struct brw_indirect ptr, int offset)
 748 {
 749    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
 750 }
 751
 752 static inline struct brw_reg
 753 deref_1ud(struct brw_indirect ptr, int offset)
 754 {
 755    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
 756 }
 757
 758 static inline struct brw_reg
 759 get_addr_reg(struct brw_indirect ptr)
 760 {
 761    return brw_address_reg(ptr.addr_subnr);
 762 }
 763
 764 static inline struct brw_indirect
 765 brw_indirect_offset(struct brw_indirect ptr, int offset)
 766 {
 767    ptr.addr_offset += offset;
 768    return ptr;
 769 }
 770
 771 static inline struct brw_indirect
 772 brw_indirect(unsigned addr_subnr, int offset)
 773 {
 774    struct brw_indirect ptr;
 775    ptr.addr_subnr = addr_subnr;
 776    ptr.addr_offset = offset;
 777    ptr.pad = 0;
 778    return ptr;
 779 }
 780
 781 /** Do two brw_regs refer to the same register? */
 782 static inline bool
 783 brw_same_reg(struct brw_reg r1, struct brw_reg r2)
 784 {
 785    return r1.file == r2.file && r1.nr == r2.nr;
 786 }
 787
 788 void brw_print_reg(struct brw_reg reg);
 789
 790 #ifdef __cplusplus
 791 }
 792 #endif
 793
 794 #endif