2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
46 #include "main/compiler.h"
47 #include "main/macros.h"
48 #include "program/prog_instruction.h"
49 #include "brw_defines.h"
55 struct brw_device_info
;
57 /** Number of general purpose registers (VS, WM, etc) */
58 #define BRW_MAX_GRF 128
61 * First GRF used for the MRF hack.
63 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
64 * haven't converted our compiler to be aware of this, so it asks for MRFs and
65 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
66 * register allocators have to be careful of this to avoid corrupting the "MRF"s
67 * with actual GRF allocations.
69 #define GEN7_MRF_HACK_START 112
71 /** Number of message register file registers */
72 #define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)
74 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
75 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
77 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
78 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
79 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
80 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
81 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
82 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
83 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
84 #define BRW_SWIZZLE_XZXZ BRW_SWIZZLE4(0,2,0,2)
85 #define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
86 #define BRW_SWIZZLE_YWYW BRW_SWIZZLE4(1,3,1,3)
87 #define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
88 #define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
89 #define BRW_SWIZZLE_WZYX BRW_SWIZZLE4(3,2,1,0)
92 brw_is_single_value_swizzle(unsigned swiz
)
94 return (swiz
== BRW_SWIZZLE_XXXX
||
95 swiz
== BRW_SWIZZLE_YYYY
||
96 swiz
== BRW_SWIZZLE_ZZZZ
||
97 swiz
== BRW_SWIZZLE_WWWW
);
101 * Compute the swizzle obtained from the application of \p swz0 on the result
102 * of \p swz1. The argument ordering is expected to match function
105 static inline unsigned
106 brw_compose_swizzle(unsigned swz0
, unsigned swz1
)
109 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 0)),
110 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 1)),
111 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 2)),
112 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 3)));
116 * Return the result of applying swizzle \p swz to shuffle the bits of \p mask
119 static inline unsigned
120 brw_apply_swizzle_to_mask(unsigned swz
, unsigned mask
)
124 for (unsigned i
= 0; i
< 4; i
++) {
125 if (mask
& (1 << BRW_GET_SWZ(swz
, i
)))
133 * Return the result of applying the inverse of swizzle \p swz to shuffle the
134 * bits of \p mask (AKA preimage). Useful to find out which components are
135 * read from a swizzled source given the instruction writemask.
137 static inline unsigned
138 brw_apply_inv_swizzle_to_mask(unsigned swz
, unsigned mask
)
142 for (unsigned i
= 0; i
< 4; i
++) {
144 result
|= 1 << BRW_GET_SWZ(swz
, i
);
151 * Construct an identity swizzle for the set of enabled channels given by \p
152 * mask. The result will only reference channels enabled in the provided \p
153 * mask, assuming that \p mask is non-zero. The constructed swizzle will
154 * satisfy the property that for any instruction OP and any mask:
156 * brw_OP(p, brw_writemask(dst, mask),
157 * brw_swizzle(src, brw_swizzle_for_mask(mask)));
159 * will be equivalent to the same instruction without swizzle:
161 * brw_OP(p, brw_writemask(dst, mask), src);
163 static inline unsigned
164 brw_swizzle_for_mask(unsigned mask
)
166 unsigned last
= (mask
? ffs(mask
) - 1 : 0);
169 for (unsigned i
= 0; i
< 4; i
++)
170 last
= swz
[i
] = (mask
& (1 << i
) ? i
: last
);
172 return BRW_SWIZZLE4(swz
[0], swz
[1], swz
[2], swz
[3]);
176 * Construct an identity swizzle for the first \p n components of a vector.
177 * When only a subset of channels of a vec4 are used we don't want to
178 * reference the other channels, as that will tell optimization passes that
179 * those other channels are used.
181 static inline unsigned
182 brw_swizzle_for_size(unsigned n
)
184 return brw_swizzle_for_mask((1 << n
) - 1);
188 * Converse of brw_swizzle_for_mask(). Returns the mask of components
189 * accessed by the specified swizzle \p swz.
191 static inline unsigned
192 brw_mask_for_swizzle(unsigned swz
)
194 return brw_apply_inv_swizzle_to_mask(swz
, ~0);
197 enum PACKED brw_reg_type
{
198 BRW_REGISTER_TYPE_UD
= 0,
200 BRW_REGISTER_TYPE_UW
,
204 /** Non-immediates only: @{ */
205 BRW_REGISTER_TYPE_UB
,
209 /** Immediates only: @{ */
210 BRW_REGISTER_TYPE_UV
, /* Gen6+ */
212 BRW_REGISTER_TYPE_VF
,
215 BRW_REGISTER_TYPE_DF
, /* Gen7+ (no immediates until Gen8+) */
218 BRW_REGISTER_TYPE_HF
,
219 BRW_REGISTER_TYPE_UQ
,
223 unsigned brw_reg_type_to_hw_type(const struct brw_device_info
*devinfo
,
224 enum brw_reg_type type
, enum brw_reg_file file
);
225 const char *brw_reg_type_letters(unsigned brw_reg_type
);
226 uint32_t brw_swizzle_immediate(enum brw_reg_type type
, uint32_t x
, unsigned swz
);
228 #define REG_SIZE (8*4)
230 /* These aren't hardware structs, just something useful for us to pass around:
232 * Align1 operation has a lot of control over input ranges. Used in
233 * WM programs to implement shaders decomposed into "channel serial"
234 * or "structure of array" form:
239 enum brw_reg_type type
:4;
240 enum brw_reg_file file
:3; /* :2 hardware format */
241 unsigned negate
:1; /* source only */
242 unsigned abs
:1; /* source only */
243 unsigned address_mode
:1; /* relative addressing, hopefully! */
245 unsigned subnr
:5; /* :1 in align16 */
253 unsigned swizzle
:8; /* src only, align16 only */
254 unsigned writemask
:4; /* dest only, align16 only */
255 int indirect_offset
:10; /* relative addressing offset */
256 unsigned vstride
:4; /* source only */
257 unsigned width
:3; /* src only, align1 only */
258 unsigned hstride
:2; /* align1 only */
271 brw_regs_equal(const struct brw_reg
*a
, const struct brw_reg
*b
)
273 const bool df
= a
->type
== BRW_REGISTER_TYPE_DF
&& a
->file
== IMM
;
274 return a
->bits
== b
->bits
&& (df
? a
->u64
== b
->u64
: a
->ud
== b
->ud
);
277 struct brw_indirect
{
278 unsigned addr_subnr
:4;
284 static inline unsigned
285 type_sz(unsigned type
)
288 case BRW_REGISTER_TYPE_UQ
:
289 case BRW_REGISTER_TYPE_Q
:
290 case BRW_REGISTER_TYPE_DF
:
292 case BRW_REGISTER_TYPE_UD
:
293 case BRW_REGISTER_TYPE_D
:
294 case BRW_REGISTER_TYPE_F
:
296 case BRW_REGISTER_TYPE_UW
:
297 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_UB
:
300 case BRW_REGISTER_TYPE_B
:
308 * Construct a brw_reg.
309 * \param file one of the BRW_x_REGISTER_FILE values
310 * \param nr register number/index
311 * \param subnr register sub number
312 * \param negate register negate modifier
313 * \param abs register abs modifier
314 * \param type one of BRW_REGISTER_TYPE_x
315 * \param vstride one of BRW_VERTICAL_STRIDE_x
316 * \param width one of BRW_WIDTH_x
317 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
318 * \param swizzle one of BRW_SWIZZLE_x
319 * \param writemask WRITEMASK_X/Y/Z/W bitfield
321 static inline struct brw_reg
322 brw_reg(enum brw_reg_file file
,
327 enum brw_reg_type type
,
335 if (file
== BRW_GENERAL_REGISTER_FILE
)
336 assert(nr
< BRW_MAX_GRF
);
337 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
338 assert(nr
<= BRW_ARF_TIMESTAMP
);
339 /* Asserting on the MRF register number requires to know the hardware gen
340 * (gen6 has 24 MRF registers), which we don't know here, so we assert
341 * for that in the generators and in brw_eu_emit.c
348 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
350 reg
.subnr
= subnr
* type_sz(type
);
353 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
354 * set swizzle and writemask to W, as the lower bits of subnr will
355 * be lost when converted to align16. This is probably too much to
356 * keep track of as you'd want it adjusted by suboffset(), etc.
357 * Perhaps fix up when converting to align16?
359 reg
.swizzle
= swizzle
;
360 reg
.writemask
= writemask
;
361 reg
.indirect_offset
= 0;
362 reg
.vstride
= vstride
;
364 reg
.hstride
= hstride
;
369 /** Construct float[16] register */
370 static inline struct brw_reg
371 brw_vec16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
379 BRW_VERTICAL_STRIDE_16
,
381 BRW_HORIZONTAL_STRIDE_1
,
386 /** Construct float[8] register */
387 static inline struct brw_reg
388 brw_vec8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
396 BRW_VERTICAL_STRIDE_8
,
398 BRW_HORIZONTAL_STRIDE_1
,
403 /** Construct float[4] register */
404 static inline struct brw_reg
405 brw_vec4_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
413 BRW_VERTICAL_STRIDE_4
,
415 BRW_HORIZONTAL_STRIDE_1
,
420 /** Construct float[2] register */
421 static inline struct brw_reg
422 brw_vec2_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
430 BRW_VERTICAL_STRIDE_2
,
432 BRW_HORIZONTAL_STRIDE_1
,
437 /** Construct float[1] register */
438 static inline struct brw_reg
439 brw_vec1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
447 BRW_VERTICAL_STRIDE_0
,
449 BRW_HORIZONTAL_STRIDE_0
,
454 static inline struct brw_reg
455 brw_vecn_reg(unsigned width
, enum brw_reg_file file
,
456 unsigned nr
, unsigned subnr
)
460 return brw_vec1_reg(file
, nr
, subnr
);
462 return brw_vec2_reg(file
, nr
, subnr
);
464 return brw_vec4_reg(file
, nr
, subnr
);
466 return brw_vec8_reg(file
, nr
, subnr
);
468 return brw_vec16_reg(file
, nr
, subnr
);
470 unreachable("Invalid register width");
474 static inline struct brw_reg
475 retype(struct brw_reg reg
, enum brw_reg_type type
)
481 static inline struct brw_reg
482 firsthalf(struct brw_reg reg
)
487 static inline struct brw_reg
488 sechalf(struct brw_reg reg
)
495 static inline struct brw_reg
496 suboffset(struct brw_reg reg
, unsigned delta
)
498 reg
.subnr
+= delta
* type_sz(reg
.type
);
503 static inline struct brw_reg
504 offset(struct brw_reg reg
, unsigned delta
)
511 static inline struct brw_reg
512 byte_offset(struct brw_reg reg
, unsigned bytes
)
514 unsigned newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
515 reg
.nr
= newoffset
/ REG_SIZE
;
516 reg
.subnr
= newoffset
% REG_SIZE
;
521 /** Construct unsigned word[16] register */
522 static inline struct brw_reg
523 brw_uw16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
525 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
528 /** Construct unsigned word[8] register */
529 static inline struct brw_reg
530 brw_uw8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
532 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
535 /** Construct unsigned word[1] register */
536 static inline struct brw_reg
537 brw_uw1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
539 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
542 static inline struct brw_reg
543 brw_imm_reg(enum brw_reg_type type
)
545 return brw_reg(BRW_IMMEDIATE_VALUE
,
551 BRW_VERTICAL_STRIDE_0
,
553 BRW_HORIZONTAL_STRIDE_0
,
558 /** Construct float immediate register */
559 static inline struct brw_reg
560 brw_imm_df(double df
)
562 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_DF
);
567 static inline struct brw_reg
570 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
575 /** Construct integer immediate register */
576 static inline struct brw_reg
579 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
584 /** Construct uint immediate register */
585 static inline struct brw_reg
586 brw_imm_ud(unsigned ud
)
588 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
593 /** Construct ushort immediate register */
594 static inline struct brw_reg
595 brw_imm_uw(uint16_t uw
)
597 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
598 imm
.ud
= uw
| (uw
<< 16);
602 /** Construct short immediate register */
603 static inline struct brw_reg
606 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
607 imm
.d
= w
| (w
<< 16);
611 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
612 * numbers alias with _V and _VF below:
615 /** Construct vector of eight signed half-byte values */
616 static inline struct brw_reg
617 brw_imm_v(unsigned v
)
619 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
624 /** Construct vector of eight unsigned half-byte values */
625 static inline struct brw_reg
626 brw_imm_uv(unsigned uv
)
628 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UV
);
633 /** Construct vector of four 8-bit float values */
634 static inline struct brw_reg
635 brw_imm_vf(unsigned v
)
637 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
642 static inline struct brw_reg
643 brw_imm_vf4(unsigned v0
, unsigned v1
, unsigned v2
, unsigned v3
)
645 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
646 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
647 imm
.width
= BRW_WIDTH_4
;
648 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
649 imm
.ud
= ((v0
<< 0) | (v1
<< 8) | (v2
<< 16) | (v3
<< 24));
654 static inline struct brw_reg
655 brw_address(struct brw_reg reg
)
657 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
660 /** Construct float[1] general-purpose register */
661 static inline struct brw_reg
662 brw_vec1_grf(unsigned nr
, unsigned subnr
)
664 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
667 /** Construct float[2] general-purpose register */
668 static inline struct brw_reg
669 brw_vec2_grf(unsigned nr
, unsigned subnr
)
671 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
674 /** Construct float[4] general-purpose register */
675 static inline struct brw_reg
676 brw_vec4_grf(unsigned nr
, unsigned subnr
)
678 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
681 /** Construct float[8] general-purpose register */
682 static inline struct brw_reg
683 brw_vec8_grf(unsigned nr
, unsigned subnr
)
685 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
688 /** Construct float[16] general-purpose register */
689 static inline struct brw_reg
690 brw_vec16_grf(unsigned nr
, unsigned subnr
)
692 return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
696 static inline struct brw_reg
697 brw_uw8_grf(unsigned nr
, unsigned subnr
)
699 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
702 static inline struct brw_reg
703 brw_uw16_grf(unsigned nr
, unsigned subnr
)
705 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
709 /** Construct null register (usually used for setting condition codes) */
710 static inline struct brw_reg
713 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
716 static inline struct brw_reg
717 brw_null_vec(unsigned width
)
719 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
722 static inline struct brw_reg
723 brw_address_reg(unsigned subnr
)
725 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_ADDRESS
, subnr
);
728 /* If/else instructions break in align16 mode if writemask & swizzle
729 * aren't xyzw. This goes against the convention for other scalar
732 static inline struct brw_reg
735 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
740 BRW_REGISTER_TYPE_UD
,
741 BRW_VERTICAL_STRIDE_4
, /* ? */
743 BRW_HORIZONTAL_STRIDE_0
,
744 BRW_SWIZZLE_XYZW
, /* NOTE! */
745 WRITEMASK_XYZW
); /* NOTE! */
748 static inline struct brw_reg
749 brw_notification_reg(void)
751 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
752 BRW_ARF_NOTIFICATION_COUNT
,
756 BRW_REGISTER_TYPE_UD
,
757 BRW_VERTICAL_STRIDE_0
,
759 BRW_HORIZONTAL_STRIDE_0
,
764 static inline struct brw_reg
767 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
772 BRW_REGISTER_TYPE_UD
,
773 BRW_VERTICAL_STRIDE_8
,
775 BRW_HORIZONTAL_STRIDE_1
,
780 static inline struct brw_reg
781 brw_acc_reg(unsigned width
)
783 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
,
784 BRW_ARF_ACCUMULATOR
, 0);
787 static inline struct brw_reg
788 brw_flag_reg(int reg
, int subreg
)
790 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
791 BRW_ARF_FLAG
+ reg
, subreg
);
795 * Return the mask register present in Gen4-5, or the related register present
796 * in Gen7.5 and later hardware referred to as "channel enable" register in
799 static inline struct brw_reg
800 brw_mask_reg(unsigned subnr
)
802 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_MASK
, subnr
);
805 static inline struct brw_reg
806 brw_message_reg(unsigned nr
)
808 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, nr
, 0);
811 static inline struct brw_reg
812 brw_uvec_mrf(unsigned width
, unsigned nr
, unsigned subnr
)
814 return retype(brw_vecn_reg(width
, BRW_MESSAGE_REGISTER_FILE
, nr
, subnr
),
815 BRW_REGISTER_TYPE_UD
);
818 /* This is almost always called with a numeric constant argument, so
819 * make things easy to evaluate at compile time:
821 static inline unsigned cvt(unsigned val
)
835 static inline struct brw_reg
836 stride(struct brw_reg reg
, unsigned vstride
, unsigned width
, unsigned hstride
)
838 reg
.vstride
= cvt(vstride
);
839 reg
.width
= cvt(width
) - 1;
840 reg
.hstride
= cvt(hstride
);
845 * Multiply the vertical and horizontal stride of a register by the given
848 static inline struct brw_reg
849 spread(struct brw_reg reg
, unsigned s
)
852 assert(_mesa_is_pow_two(s
));
855 reg
.hstride
+= cvt(s
) - 1;
858 reg
.vstride
+= cvt(s
) - 1;
862 return stride(reg
, 0, 1, 0);
866 static inline struct brw_reg
867 vec16(struct brw_reg reg
)
869 return stride(reg
, 16,16,1);
872 static inline struct brw_reg
873 vec8(struct brw_reg reg
)
875 return stride(reg
, 8,8,1);
878 static inline struct brw_reg
879 vec4(struct brw_reg reg
)
881 return stride(reg
, 4,4,1);
884 static inline struct brw_reg
885 vec2(struct brw_reg reg
)
887 return stride(reg
, 2,2,1);
890 static inline struct brw_reg
891 vec1(struct brw_reg reg
)
893 return stride(reg
, 0,1,0);
897 static inline struct brw_reg
898 get_element(struct brw_reg reg
, unsigned elt
)
900 return vec1(suboffset(reg
, elt
));
903 static inline struct brw_reg
904 get_element_ud(struct brw_reg reg
, unsigned elt
)
906 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
909 static inline struct brw_reg
910 get_element_d(struct brw_reg reg
, unsigned elt
)
912 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
915 static inline struct brw_reg
916 brw_swizzle(struct brw_reg reg
, unsigned swz
)
918 if (reg
.file
== BRW_IMMEDIATE_VALUE
)
919 reg
.ud
= brw_swizzle_immediate(reg
.type
, reg
.ud
, swz
);
921 reg
.swizzle
= brw_compose_swizzle(swz
, reg
.swizzle
);
926 static inline struct brw_reg
927 brw_writemask(struct brw_reg reg
, unsigned mask
)
929 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
930 reg
.writemask
&= mask
;
934 static inline struct brw_reg
935 brw_set_writemask(struct brw_reg reg
, unsigned mask
)
937 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
938 reg
.writemask
= mask
;
942 static inline unsigned
943 brw_writemask_for_size(unsigned n
)
948 static inline struct brw_reg
949 negate(struct brw_reg reg
)
955 static inline struct brw_reg
956 brw_abs(struct brw_reg reg
)
963 /************************************************************************/
965 static inline struct brw_reg
966 brw_vec4_indirect(unsigned subnr
, int offset
)
968 struct brw_reg reg
= brw_vec4_grf(0, 0);
970 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
971 reg
.indirect_offset
= offset
;
975 static inline struct brw_reg
976 brw_vec1_indirect(unsigned subnr
, int offset
)
978 struct brw_reg reg
= brw_vec1_grf(0, 0);
980 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
981 reg
.indirect_offset
= offset
;
985 static inline struct brw_reg
986 brw_VxH_indirect(unsigned subnr
, int offset
)
988 struct brw_reg reg
= brw_vec1_grf(0, 0);
989 reg
.vstride
= BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL
;
991 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
992 reg
.indirect_offset
= offset
;
996 static inline struct brw_reg
997 deref_4f(struct brw_indirect ptr
, int offset
)
999 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1002 static inline struct brw_reg
1003 deref_1f(struct brw_indirect ptr
, int offset
)
1005 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1008 static inline struct brw_reg
1009 deref_4b(struct brw_indirect ptr
, int offset
)
1011 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
1014 static inline struct brw_reg
1015 deref_1uw(struct brw_indirect ptr
, int offset
)
1017 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
1020 static inline struct brw_reg
1021 deref_1d(struct brw_indirect ptr
, int offset
)
1023 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
1026 static inline struct brw_reg
1027 deref_1ud(struct brw_indirect ptr
, int offset
)
1029 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
1032 static inline struct brw_reg
1033 get_addr_reg(struct brw_indirect ptr
)
1035 return brw_address_reg(ptr
.addr_subnr
);
1038 static inline struct brw_indirect
1039 brw_indirect_offset(struct brw_indirect ptr
, int offset
)
1041 ptr
.addr_offset
+= offset
;
1045 static inline struct brw_indirect
1046 brw_indirect(unsigned addr_subnr
, int offset
)
1048 struct brw_indirect ptr
;
1049 ptr
.addr_subnr
= addr_subnr
;
1050 ptr
.addr_offset
= offset
;
1056 region_matches(struct brw_reg reg
, enum brw_vertical_stride v
,
1057 enum brw_width w
, enum brw_horizontal_stride h
)
1059 return reg
.vstride
== v
&&
1064 #define has_scalar_region(reg) \
1065 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
1066 BRW_HORIZONTAL_STRIDE_0)
1068 /* brw_packed_float.c */
1069 int brw_float_to_vf(float f
);
1070 float brw_vf_to_float(unsigned char vf
);