2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
46 #include "main/imports.h"
47 #include "main/compiler.h"
48 #include "main/macros.h"
49 #include "program/prog_instruction.h"
50 #include "brw_defines.h"
58 /** Number of general purpose registers (VS, WM, etc) */
59 #define BRW_MAX_GRF 128
62 * First GRF used for the MRF hack.
64 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
65 * haven't converted our compiler to be aware of this, so it asks for MRFs and
66 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
67 * register allocators have to be careful of this to avoid corrupting the "MRF"s
68 * with actual GRF allocations.
70 #define GEN7_MRF_HACK_START 112
72 /** Number of message register file registers */
73 #define BRW_MAX_MRF 16
75 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
76 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
78 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
79 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
80 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
81 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
82 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
83 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
84 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
85 #define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
86 #define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
87 #define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
90 brw_is_single_value_swizzle(int swiz
)
92 return (swiz
== BRW_SWIZZLE_XXXX
||
93 swiz
== BRW_SWIZZLE_YYYY
||
94 swiz
== BRW_SWIZZLE_ZZZZ
||
95 swiz
== BRW_SWIZZLE_WWWW
);
98 enum PACKED brw_reg_type
{
99 BRW_REGISTER_TYPE_UD
= 0,
101 BRW_REGISTER_TYPE_UW
,
105 /** Non-immediates only: @{ */
106 BRW_REGISTER_TYPE_UB
,
110 /** Immediates only: @{ */
111 BRW_REGISTER_TYPE_UV
,
113 BRW_REGISTER_TYPE_VF
,
116 BRW_REGISTER_TYPE_DF
, /* Gen7+ (no immediates until Gen8+) */
119 BRW_REGISTER_TYPE_HF
,
120 BRW_REGISTER_TYPE_UQ
,
124 unsigned brw_reg_type_to_hw_type(const struct brw_context
*brw
,
125 enum brw_reg_type type
, unsigned file
);
126 const char *brw_reg_type_letters(unsigned brw_reg_type
);
128 #define REG_SIZE (8*4)
130 /* These aren't hardware structs, just something useful for us to pass around:
132 * Align1 operation has a lot of control over input ranges. Used in
133 * WM programs to implement shaders decomposed into "channel serial"
134 * or "structure of array" form:
137 enum brw_reg_type type
:4;
140 unsigned subnr
:5; /* :1 in align16 */
141 unsigned negate
:1; /* source only */
142 unsigned abs
:1; /* source only */
143 unsigned vstride
:4; /* source only */
144 unsigned width
:3; /* src only, align1 only */
145 unsigned hstride
:2; /* align1 only */
146 unsigned address_mode
:1; /* relative addressing, hopefully! */
151 unsigned swizzle
:8; /* src only, align16 only */
152 unsigned writemask
:4; /* dest only, align16 only */
153 int indirect_offset
:10; /* relative addressing offset */
154 unsigned pad1
:10; /* two dwords total */
164 struct brw_indirect
{
165 unsigned addr_subnr
:4;
172 type_sz(unsigned type
)
175 case BRW_REGISTER_TYPE_UQ
:
176 case BRW_REGISTER_TYPE_Q
:
178 case BRW_REGISTER_TYPE_UD
:
179 case BRW_REGISTER_TYPE_D
:
180 case BRW_REGISTER_TYPE_F
:
182 case BRW_REGISTER_TYPE_UW
:
183 case BRW_REGISTER_TYPE_W
:
185 case BRW_REGISTER_TYPE_UB
:
186 case BRW_REGISTER_TYPE_B
:
194 type_is_signed(unsigned type
)
197 case BRW_REGISTER_TYPE_D
:
198 case BRW_REGISTER_TYPE_W
:
199 case BRW_REGISTER_TYPE_F
:
200 case BRW_REGISTER_TYPE_B
:
201 case BRW_REGISTER_TYPE_V
:
202 case BRW_REGISTER_TYPE_VF
:
203 case BRW_REGISTER_TYPE_DF
:
204 case BRW_REGISTER_TYPE_HF
:
205 case BRW_REGISTER_TYPE_Q
:
208 case BRW_REGISTER_TYPE_UD
:
209 case BRW_REGISTER_TYPE_UW
:
210 case BRW_REGISTER_TYPE_UB
:
211 case BRW_REGISTER_TYPE_UV
:
212 case BRW_REGISTER_TYPE_UQ
:
216 unreachable("not reached");
221 * Construct a brw_reg.
222 * \param file one of the BRW_x_REGISTER_FILE values
223 * \param nr register number/index
224 * \param subnr register sub number
225 * \param negate register negate modifier
226 * \param abs register abs modifier
227 * \param type one of BRW_REGISTER_TYPE_x
228 * \param vstride one of BRW_VERTICAL_STRIDE_x
229 * \param width one of BRW_WIDTH_x
230 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
231 * \param swizzle one of BRW_SWIZZLE_x
232 * \param writemask WRITEMASK_X/Y/Z/W bitfield
234 static inline struct brw_reg
235 brw_reg(unsigned file
,
240 enum brw_reg_type type
,
248 if (file
== BRW_GENERAL_REGISTER_FILE
)
249 assert(nr
< BRW_MAX_GRF
);
250 else if (file
== BRW_MESSAGE_REGISTER_FILE
)
251 assert((nr
& ~(1 << 7)) < BRW_MAX_MRF
);
252 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
253 assert(nr
<= BRW_ARF_TIMESTAMP
);
258 reg
.subnr
= subnr
* type_sz(type
);
261 reg
.vstride
= vstride
;
263 reg
.hstride
= hstride
;
264 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
267 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
268 * set swizzle and writemask to W, as the lower bits of subnr will
269 * be lost when converted to align16. This is probably too much to
270 * keep track of as you'd want it adjusted by suboffset(), etc.
271 * Perhaps fix up when converting to align16?
273 reg
.dw1
.bits
.swizzle
= swizzle
;
274 reg
.dw1
.bits
.writemask
= writemask
;
275 reg
.dw1
.bits
.indirect_offset
= 0;
276 reg
.dw1
.bits
.pad1
= 0;
280 /** Construct float[16] register */
281 static inline struct brw_reg
282 brw_vec16_reg(unsigned file
, unsigned nr
, unsigned subnr
)
290 BRW_VERTICAL_STRIDE_16
,
292 BRW_HORIZONTAL_STRIDE_1
,
297 /** Construct float[8] register */
298 static inline struct brw_reg
299 brw_vec8_reg(unsigned file
, unsigned nr
, unsigned subnr
)
307 BRW_VERTICAL_STRIDE_8
,
309 BRW_HORIZONTAL_STRIDE_1
,
314 /** Construct float[4] register */
315 static inline struct brw_reg
316 brw_vec4_reg(unsigned file
, unsigned nr
, unsigned subnr
)
324 BRW_VERTICAL_STRIDE_4
,
326 BRW_HORIZONTAL_STRIDE_1
,
331 /** Construct float[2] register */
332 static inline struct brw_reg
333 brw_vec2_reg(unsigned file
, unsigned nr
, unsigned subnr
)
341 BRW_VERTICAL_STRIDE_2
,
343 BRW_HORIZONTAL_STRIDE_1
,
348 /** Construct float[1] register */
349 static inline struct brw_reg
350 brw_vec1_reg(unsigned file
, unsigned nr
, unsigned subnr
)
358 BRW_VERTICAL_STRIDE_0
,
360 BRW_HORIZONTAL_STRIDE_0
,
365 static inline struct brw_reg
366 brw_vecn_reg(unsigned width
, unsigned file
, unsigned nr
, unsigned subnr
)
370 return brw_vec1_reg(file
, nr
, subnr
);
372 return brw_vec2_reg(file
, nr
, subnr
);
374 return brw_vec4_reg(file
, nr
, subnr
);
376 return brw_vec8_reg(file
, nr
, subnr
);
378 return brw_vec16_reg(file
, nr
, subnr
);
380 unreachable("Invalid register width");
384 static inline struct brw_reg
385 retype(struct brw_reg reg
, enum brw_reg_type type
)
391 static inline struct brw_reg
392 firsthalf(struct brw_reg reg
)
397 static inline struct brw_reg
398 sechalf(struct brw_reg reg
)
405 static inline struct brw_reg
406 suboffset(struct brw_reg reg
, unsigned delta
)
408 reg
.subnr
+= delta
* type_sz(reg
.type
);
413 static inline struct brw_reg
414 offset(struct brw_reg reg
, unsigned delta
)
421 static inline struct brw_reg
422 byte_offset(struct brw_reg reg
, unsigned bytes
)
424 unsigned newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
425 reg
.nr
= newoffset
/ REG_SIZE
;
426 reg
.subnr
= newoffset
% REG_SIZE
;
431 /** Construct unsigned word[16] register */
432 static inline struct brw_reg
433 brw_uw16_reg(unsigned file
, unsigned nr
, unsigned subnr
)
435 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
438 /** Construct unsigned word[8] register */
439 static inline struct brw_reg
440 brw_uw8_reg(unsigned file
, unsigned nr
, unsigned subnr
)
442 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
445 /** Construct unsigned word[1] register */
446 static inline struct brw_reg
447 brw_uw1_reg(unsigned file
, unsigned nr
, unsigned subnr
)
449 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
452 static inline struct brw_reg
453 brw_imm_reg(enum brw_reg_type type
)
455 return brw_reg(BRW_IMMEDIATE_VALUE
,
461 BRW_VERTICAL_STRIDE_0
,
463 BRW_HORIZONTAL_STRIDE_0
,
468 /** Construct float immediate register */
469 static inline struct brw_reg
472 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
477 /** Construct integer immediate register */
478 static inline struct brw_reg
481 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
486 /** Construct uint immediate register */
487 static inline struct brw_reg
488 brw_imm_ud(unsigned ud
)
490 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
495 /** Construct ushort immediate register */
496 static inline struct brw_reg
497 brw_imm_uw(uint16_t uw
)
499 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
500 imm
.dw1
.ud
= uw
| (uw
<< 16);
504 /** Construct short immediate register */
505 static inline struct brw_reg
508 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
509 imm
.dw1
.d
= w
| (w
<< 16);
513 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
514 * numbers alias with _V and _VF below:
517 /** Construct vector of eight signed half-byte values */
518 static inline struct brw_reg
519 brw_imm_v(unsigned v
)
521 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
522 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
523 imm
.width
= BRW_WIDTH_8
;
524 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
529 /** Construct vector of four 8-bit float values */
530 static inline struct brw_reg
531 brw_imm_vf(unsigned v
)
533 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
534 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
535 imm
.width
= BRW_WIDTH_4
;
536 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
542 * Convert an integer into a "restricted" 8-bit float, used in vector
543 * immediates. The 8-bit floating point format has a sign bit, an
544 * excess-3 3-bit exponent, and a 4-bit mantissa. All integer values
545 * from -31 to 31 can be represented exactly.
547 static inline uint8_t
553 return 1 << 7 | int_to_float8(-x
);
555 const unsigned exponent
= _mesa_logbase2(x
);
556 const unsigned mantissa
= (x
- (1 << exponent
)) << (4 - exponent
);
557 assert(exponent
<= 4);
558 return (exponent
+ 3) << 4 | mantissa
;
563 * Construct a floating-point packed vector immediate from its integer
564 * values. \sa int_to_float8()
566 static inline struct brw_reg
567 brw_imm_vf4(int v0
, int v1
, int v2
, int v3
)
569 return brw_imm_vf((int_to_float8(v0
) << 0) |
570 (int_to_float8(v1
) << 8) |
571 (int_to_float8(v2
) << 16) |
572 (int_to_float8(v3
) << 24));
576 static inline struct brw_reg
577 brw_address(struct brw_reg reg
)
579 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
582 /** Construct float[1] general-purpose register */
583 static inline struct brw_reg
584 brw_vec1_grf(unsigned nr
, unsigned subnr
)
586 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
589 /** Construct float[2] general-purpose register */
590 static inline struct brw_reg
591 brw_vec2_grf(unsigned nr
, unsigned subnr
)
593 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
596 /** Construct float[4] general-purpose register */
597 static inline struct brw_reg
598 brw_vec4_grf(unsigned nr
, unsigned subnr
)
600 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
603 /** Construct float[8] general-purpose register */
604 static inline struct brw_reg
605 brw_vec8_grf(unsigned nr
, unsigned subnr
)
607 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
611 static inline struct brw_reg
612 brw_uw8_grf(unsigned nr
, unsigned subnr
)
614 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
617 static inline struct brw_reg
618 brw_uw16_grf(unsigned nr
, unsigned subnr
)
620 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
624 /** Construct null register (usually used for setting condition codes) */
625 static inline struct brw_reg
628 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
631 static inline struct brw_reg
632 brw_null_vec(unsigned width
)
634 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
637 static inline struct brw_reg
638 brw_address_reg(unsigned subnr
)
640 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_ADDRESS
, subnr
);
643 /* If/else instructions break in align16 mode if writemask & swizzle
644 * aren't xyzw. This goes against the convention for other scalar
647 static inline struct brw_reg
650 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
655 BRW_REGISTER_TYPE_UD
,
656 BRW_VERTICAL_STRIDE_4
, /* ? */
658 BRW_HORIZONTAL_STRIDE_0
,
659 BRW_SWIZZLE_XYZW
, /* NOTE! */
660 WRITEMASK_XYZW
); /* NOTE! */
663 static inline struct brw_reg
664 brw_acc_reg(unsigned width
)
666 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
,
667 BRW_ARF_ACCUMULATOR
, 0);
670 static inline struct brw_reg
671 brw_flag_reg(int reg
, int subreg
)
673 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
674 BRW_ARF_FLAG
+ reg
, subreg
);
678 static inline struct brw_reg
679 brw_mask_reg(unsigned subnr
)
681 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_MASK
, subnr
);
684 static inline struct brw_reg
685 brw_message_reg(unsigned nr
)
687 assert((nr
& ~(1 << 7)) < BRW_MAX_MRF
);
688 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, nr
, 0);
691 static inline struct brw_reg
692 brw_uvec_mrf(unsigned width
, unsigned nr
, unsigned subnr
)
694 return retype(brw_vecn_reg(width
, BRW_MESSAGE_REGISTER_FILE
, nr
, subnr
),
695 BRW_REGISTER_TYPE_UD
);
698 /* This is almost always called with a numeric constant argument, so
699 * make things easy to evaluate at compile time:
701 static inline unsigned cvt(unsigned val
)
715 static inline struct brw_reg
716 stride(struct brw_reg reg
, unsigned vstride
, unsigned width
, unsigned hstride
)
718 reg
.vstride
= cvt(vstride
);
719 reg
.width
= cvt(width
) - 1;
720 reg
.hstride
= cvt(hstride
);
725 * Multiply the vertical and horizontal stride of a register by the given
728 static inline struct brw_reg
729 spread(struct brw_reg reg
, unsigned s
)
732 assert(is_power_of_two(s
));
735 reg
.hstride
+= cvt(s
) - 1;
738 reg
.vstride
+= cvt(s
) - 1;
742 return stride(reg
, 0, 1, 0);
746 static inline struct brw_reg
747 vec16(struct brw_reg reg
)
749 return stride(reg
, 16,16,1);
752 static inline struct brw_reg
753 vec8(struct brw_reg reg
)
755 return stride(reg
, 8,8,1);
758 static inline struct brw_reg
759 vec4(struct brw_reg reg
)
761 return stride(reg
, 4,4,1);
764 static inline struct brw_reg
765 vec2(struct brw_reg reg
)
767 return stride(reg
, 2,2,1);
770 static inline struct brw_reg
771 vec1(struct brw_reg reg
)
773 return stride(reg
, 0,1,0);
777 static inline struct brw_reg
778 get_element(struct brw_reg reg
, unsigned elt
)
780 return vec1(suboffset(reg
, elt
));
783 static inline struct brw_reg
784 get_element_ud(struct brw_reg reg
, unsigned elt
)
786 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
789 static inline struct brw_reg
790 get_element_d(struct brw_reg reg
, unsigned elt
)
792 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
796 static inline struct brw_reg
797 brw_swizzle(struct brw_reg reg
, unsigned x
, unsigned y
, unsigned z
, unsigned w
)
799 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
801 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, x
),
802 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, y
),
803 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, z
),
804 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, w
));
809 static inline struct brw_reg
810 brw_swizzle1(struct brw_reg reg
, unsigned x
)
812 return brw_swizzle(reg
, x
, x
, x
, x
);
815 static inline struct brw_reg
816 brw_writemask(struct brw_reg reg
, unsigned mask
)
818 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
819 reg
.dw1
.bits
.writemask
&= mask
;
823 static inline struct brw_reg
824 brw_set_writemask(struct brw_reg reg
, unsigned mask
)
826 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
827 reg
.dw1
.bits
.writemask
= mask
;
831 static inline struct brw_reg
832 negate(struct brw_reg reg
)
838 static inline struct brw_reg
839 brw_abs(struct brw_reg reg
)
846 /************************************************************************/
848 static inline struct brw_reg
849 brw_vec4_indirect(unsigned subnr
, int offset
)
851 struct brw_reg reg
= brw_vec4_grf(0, 0);
853 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
854 reg
.dw1
.bits
.indirect_offset
= offset
;
858 static inline struct brw_reg
859 brw_vec1_indirect(unsigned subnr
, int offset
)
861 struct brw_reg reg
= brw_vec1_grf(0, 0);
863 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
864 reg
.dw1
.bits
.indirect_offset
= offset
;
868 static inline struct brw_reg
869 deref_4f(struct brw_indirect ptr
, int offset
)
871 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
874 static inline struct brw_reg
875 deref_1f(struct brw_indirect ptr
, int offset
)
877 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
880 static inline struct brw_reg
881 deref_4b(struct brw_indirect ptr
, int offset
)
883 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
886 static inline struct brw_reg
887 deref_1uw(struct brw_indirect ptr
, int offset
)
889 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
892 static inline struct brw_reg
893 deref_1d(struct brw_indirect ptr
, int offset
)
895 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
898 static inline struct brw_reg
899 deref_1ud(struct brw_indirect ptr
, int offset
)
901 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
904 static inline struct brw_reg
905 get_addr_reg(struct brw_indirect ptr
)
907 return brw_address_reg(ptr
.addr_subnr
);
910 static inline struct brw_indirect
911 brw_indirect_offset(struct brw_indirect ptr
, int offset
)
913 ptr
.addr_offset
+= offset
;
917 static inline struct brw_indirect
918 brw_indirect(unsigned addr_subnr
, int offset
)
920 struct brw_indirect ptr
;
921 ptr
.addr_subnr
= addr_subnr
;
922 ptr
.addr_offset
= offset
;
928 region_matches(struct brw_reg reg
, enum brw_vertical_stride v
,
929 enum brw_width w
, enum brw_horizontal_stride h
)
931 return reg
.vstride
== v
&&
936 #define has_scalar_region(reg) \
937 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
938 BRW_HORIZONTAL_STRIDE_0)
940 /* brw_packed_float.c */
941 int brw_float_to_vf(float f
);
942 float brw_vf_to_float(unsigned char vf
);