2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
46 #include "main/imports.h"
47 #include "main/compiler.h"
48 #include "main/macros.h"
49 #include "program/prog_instruction.h"
50 #include "brw_defines.h"
56 struct brw_device_info
;
58 /** Number of general purpose registers (VS, WM, etc) */
59 #define BRW_MAX_GRF 128
62 * First GRF used for the MRF hack.
64 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
65 * haven't converted our compiler to be aware of this, so it asks for MRFs and
66 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
67 * register allocators have to be careful of this to avoid corrupting the "MRF"s
68 * with actual GRF allocations.
70 #define GEN7_MRF_HACK_START 112
72 /** Number of message register file registers */
73 #define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)
75 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
76 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
78 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
79 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
80 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
81 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
82 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
83 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
84 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
85 #define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
86 #define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
87 #define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
90 brw_is_single_value_swizzle(unsigned swiz
)
92 return (swiz
== BRW_SWIZZLE_XXXX
||
93 swiz
== BRW_SWIZZLE_YYYY
||
94 swiz
== BRW_SWIZZLE_ZZZZ
||
95 swiz
== BRW_SWIZZLE_WWWW
);
99 * Compute the swizzle obtained from the application of \p swz0 on the result
100 * of \p swz1. The argument ordering is expected to match function
103 static inline unsigned
104 brw_compose_swizzle(unsigned swz0
, unsigned swz1
)
107 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 0)),
108 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 1)),
109 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 2)),
110 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 3)));
114 * Return the result of applying swizzle \p swz to shuffle the bits of \p mask
117 static inline unsigned
118 brw_apply_swizzle_to_mask(unsigned swz
, unsigned mask
)
122 for (unsigned i
= 0; i
< 4; i
++) {
123 if (mask
& (1 << BRW_GET_SWZ(swz
, i
)))
131 * Return the result of applying the inverse of swizzle \p swz to shuffle the
132 * bits of \p mask (AKA preimage). Useful to find out which components are
133 * read from a swizzled source given the instruction writemask.
135 static inline unsigned
136 brw_apply_inv_swizzle_to_mask(unsigned swz
, unsigned mask
)
140 for (unsigned i
= 0; i
< 4; i
++) {
142 result
|= 1 << BRW_GET_SWZ(swz
, i
);
149 * Construct an identity swizzle for the set of enabled channels given by \p
150 * mask. The result will only reference channels enabled in the provided \p
151 * mask, assuming that \p mask is non-zero. The constructed swizzle will
152 * satisfy the property that for any instruction OP and any mask:
154 * brw_OP(p, brw_writemask(dst, mask),
155 * brw_swizzle(src, brw_swizzle_for_mask(mask)));
157 * will be equivalent to the same instruction without swizzle:
159 * brw_OP(p, brw_writemask(dst, mask), src);
161 static inline unsigned
162 brw_swizzle_for_mask(unsigned mask
)
164 unsigned last
= (mask
? ffs(mask
) - 1 : 0);
167 for (unsigned i
= 0; i
< 4; i
++)
168 last
= swz
[i
] = (mask
& (1 << i
) ? i
: last
);
170 return BRW_SWIZZLE4(swz
[0], swz
[1], swz
[2], swz
[3]);
174 * Construct an identity swizzle for the first \p n components of a vector.
175 * When only a subset of channels of a vec4 are used we don't want to
176 * reference the other channels, as that will tell optimization passes that
177 * those other channels are used.
179 static inline unsigned
180 brw_swizzle_for_size(unsigned n
)
182 return brw_swizzle_for_mask((1 << n
) - 1);
186 * Converse of brw_swizzle_for_mask(). Returns the mask of components
187 * accessed by the specified swizzle \p swz.
189 static inline unsigned
190 brw_mask_for_swizzle(unsigned swz
)
192 return brw_apply_inv_swizzle_to_mask(swz
, ~0);
195 enum PACKED brw_reg_type
{
196 BRW_REGISTER_TYPE_UD
= 0,
198 BRW_REGISTER_TYPE_UW
,
202 /** Non-immediates only: @{ */
203 BRW_REGISTER_TYPE_UB
,
207 /** Immediates only: @{ */
208 BRW_REGISTER_TYPE_UV
,
210 BRW_REGISTER_TYPE_VF
,
213 BRW_REGISTER_TYPE_DF
, /* Gen7+ (no immediates until Gen8+) */
216 BRW_REGISTER_TYPE_HF
,
217 BRW_REGISTER_TYPE_UQ
,
221 unsigned brw_reg_type_to_hw_type(const struct brw_device_info
*devinfo
,
222 enum brw_reg_type type
, unsigned file
);
223 const char *brw_reg_type_letters(unsigned brw_reg_type
);
225 #define REG_SIZE (8*4)
227 /* These aren't hardware structs, just something useful for us to pass around:
229 * Align1 operation has a lot of control over input ranges. Used in
230 * WM programs to implement shaders decomposed into "channel serial"
231 * or "structure of array" form:
234 enum brw_reg_type type
:4;
237 unsigned subnr
:5; /* :1 in align16 */
238 unsigned negate
:1; /* source only */
239 unsigned abs
:1; /* source only */
240 unsigned vstride
:4; /* source only */
241 unsigned width
:3; /* src only, align1 only */
242 unsigned hstride
:2; /* align1 only */
243 unsigned address_mode
:1; /* relative addressing, hopefully! */
248 unsigned swizzle
:8; /* src only, align16 only */
249 unsigned writemask
:4; /* dest only, align16 only */
250 int indirect_offset
:10; /* relative addressing offset */
251 unsigned pad1
:10; /* two dwords total */
261 struct brw_indirect
{
262 unsigned addr_subnr
:4;
268 static inline unsigned
269 type_sz(unsigned type
)
272 case BRW_REGISTER_TYPE_UQ
:
273 case BRW_REGISTER_TYPE_Q
:
275 case BRW_REGISTER_TYPE_UD
:
276 case BRW_REGISTER_TYPE_D
:
277 case BRW_REGISTER_TYPE_F
:
279 case BRW_REGISTER_TYPE_UW
:
280 case BRW_REGISTER_TYPE_W
:
282 case BRW_REGISTER_TYPE_UB
:
283 case BRW_REGISTER_TYPE_B
:
291 type_is_signed(unsigned type
)
294 case BRW_REGISTER_TYPE_D
:
295 case BRW_REGISTER_TYPE_W
:
296 case BRW_REGISTER_TYPE_F
:
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_V
:
299 case BRW_REGISTER_TYPE_VF
:
300 case BRW_REGISTER_TYPE_DF
:
301 case BRW_REGISTER_TYPE_HF
:
302 case BRW_REGISTER_TYPE_Q
:
305 case BRW_REGISTER_TYPE_UD
:
306 case BRW_REGISTER_TYPE_UW
:
307 case BRW_REGISTER_TYPE_UB
:
308 case BRW_REGISTER_TYPE_UV
:
309 case BRW_REGISTER_TYPE_UQ
:
313 unreachable("not reached");
318 * Construct a brw_reg.
319 * \param file one of the BRW_x_REGISTER_FILE values
320 * \param nr register number/index
321 * \param subnr register sub number
322 * \param negate register negate modifier
323 * \param abs register abs modifier
324 * \param type one of BRW_REGISTER_TYPE_x
325 * \param vstride one of BRW_VERTICAL_STRIDE_x
326 * \param width one of BRW_WIDTH_x
327 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
328 * \param swizzle one of BRW_SWIZZLE_x
329 * \param writemask WRITEMASK_X/Y/Z/W bitfield
331 static inline struct brw_reg
332 brw_reg(unsigned file
,
337 enum brw_reg_type type
,
345 if (file
== BRW_GENERAL_REGISTER_FILE
)
346 assert(nr
< BRW_MAX_GRF
);
347 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
348 assert(nr
<= BRW_ARF_TIMESTAMP
);
349 /* Asserting on the MRF register number requires to know the hardware gen
350 * (gen6 has 24 MRF registers), which we don't know here, so we assert
351 * for that in the generators and in brw_eu_emit.c
357 reg
.subnr
= subnr
* type_sz(type
);
360 reg
.vstride
= vstride
;
362 reg
.hstride
= hstride
;
363 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
366 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
367 * set swizzle and writemask to W, as the lower bits of subnr will
368 * be lost when converted to align16. This is probably too much to
369 * keep track of as you'd want it adjusted by suboffset(), etc.
370 * Perhaps fix up when converting to align16?
372 reg
.dw1
.bits
.swizzle
= swizzle
;
373 reg
.dw1
.bits
.writemask
= writemask
;
374 reg
.dw1
.bits
.indirect_offset
= 0;
375 reg
.dw1
.bits
.pad1
= 0;
379 /** Construct float[16] register */
380 static inline struct brw_reg
381 brw_vec16_reg(unsigned file
, unsigned nr
, unsigned subnr
)
389 BRW_VERTICAL_STRIDE_16
,
391 BRW_HORIZONTAL_STRIDE_1
,
396 /** Construct float[8] register */
397 static inline struct brw_reg
398 brw_vec8_reg(unsigned file
, unsigned nr
, unsigned subnr
)
406 BRW_VERTICAL_STRIDE_8
,
408 BRW_HORIZONTAL_STRIDE_1
,
413 /** Construct float[4] register */
414 static inline struct brw_reg
415 brw_vec4_reg(unsigned file
, unsigned nr
, unsigned subnr
)
423 BRW_VERTICAL_STRIDE_4
,
425 BRW_HORIZONTAL_STRIDE_1
,
430 /** Construct float[2] register */
431 static inline struct brw_reg
432 brw_vec2_reg(unsigned file
, unsigned nr
, unsigned subnr
)
440 BRW_VERTICAL_STRIDE_2
,
442 BRW_HORIZONTAL_STRIDE_1
,
447 /** Construct float[1] register */
448 static inline struct brw_reg
449 brw_vec1_reg(unsigned file
, unsigned nr
, unsigned subnr
)
457 BRW_VERTICAL_STRIDE_0
,
459 BRW_HORIZONTAL_STRIDE_0
,
464 static inline struct brw_reg
465 brw_vecn_reg(unsigned width
, unsigned file
, unsigned nr
, unsigned subnr
)
469 return brw_vec1_reg(file
, nr
, subnr
);
471 return brw_vec2_reg(file
, nr
, subnr
);
473 return brw_vec4_reg(file
, nr
, subnr
);
475 return brw_vec8_reg(file
, nr
, subnr
);
477 return brw_vec16_reg(file
, nr
, subnr
);
479 unreachable("Invalid register width");
483 static inline struct brw_reg
484 retype(struct brw_reg reg
, enum brw_reg_type type
)
490 static inline struct brw_reg
491 firsthalf(struct brw_reg reg
)
496 static inline struct brw_reg
497 sechalf(struct brw_reg reg
)
504 static inline struct brw_reg
505 suboffset(struct brw_reg reg
, unsigned delta
)
507 reg
.subnr
+= delta
* type_sz(reg
.type
);
512 static inline struct brw_reg
513 offset(struct brw_reg reg
, unsigned delta
)
520 static inline struct brw_reg
521 byte_offset(struct brw_reg reg
, unsigned bytes
)
523 unsigned newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
524 reg
.nr
= newoffset
/ REG_SIZE
;
525 reg
.subnr
= newoffset
% REG_SIZE
;
530 /** Construct unsigned word[16] register */
531 static inline struct brw_reg
532 brw_uw16_reg(unsigned file
, unsigned nr
, unsigned subnr
)
534 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
537 /** Construct unsigned word[8] register */
538 static inline struct brw_reg
539 brw_uw8_reg(unsigned file
, unsigned nr
, unsigned subnr
)
541 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
544 /** Construct unsigned word[1] register */
545 static inline struct brw_reg
546 brw_uw1_reg(unsigned file
, unsigned nr
, unsigned subnr
)
548 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
551 static inline struct brw_reg
552 brw_imm_reg(enum brw_reg_type type
)
554 return brw_reg(BRW_IMMEDIATE_VALUE
,
560 BRW_VERTICAL_STRIDE_0
,
562 BRW_HORIZONTAL_STRIDE_0
,
567 /** Construct float immediate register */
568 static inline struct brw_reg
571 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
576 /** Construct integer immediate register */
577 static inline struct brw_reg
580 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
585 /** Construct uint immediate register */
586 static inline struct brw_reg
587 brw_imm_ud(unsigned ud
)
589 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
594 /** Construct ushort immediate register */
595 static inline struct brw_reg
596 brw_imm_uw(uint16_t uw
)
598 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
599 imm
.dw1
.ud
= uw
| (uw
<< 16);
603 /** Construct short immediate register */
604 static inline struct brw_reg
607 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
608 imm
.dw1
.d
= w
| (w
<< 16);
612 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
613 * numbers alias with _V and _VF below:
616 /** Construct vector of eight signed half-byte values */
617 static inline struct brw_reg
618 brw_imm_v(unsigned v
)
620 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
621 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
622 imm
.width
= BRW_WIDTH_8
;
623 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
628 /** Construct vector of four 8-bit float values */
629 static inline struct brw_reg
630 brw_imm_vf(unsigned v
)
632 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
633 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
634 imm
.width
= BRW_WIDTH_4
;
635 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
641 * Convert an integer into a "restricted" 8-bit float, used in vector
642 * immediates. The 8-bit floating point format has a sign bit, an
643 * excess-3 3-bit exponent, and a 4-bit mantissa. All integer values
644 * from -31 to 31 can be represented exactly.
646 static inline uint8_t
652 return 1 << 7 | int_to_float8(-x
);
654 const unsigned exponent
= _mesa_logbase2(x
);
655 const unsigned mantissa
= (x
- (1 << exponent
)) << (4 - exponent
);
656 assert(exponent
<= 4);
657 return (exponent
+ 3) << 4 | mantissa
;
662 * Construct a floating-point packed vector immediate from its integer
663 * values. \sa int_to_float8()
665 static inline struct brw_reg
666 brw_imm_vf4(int v0
, int v1
, int v2
, int v3
)
668 return brw_imm_vf((int_to_float8(v0
) << 0) |
669 (int_to_float8(v1
) << 8) |
670 (int_to_float8(v2
) << 16) |
671 (int_to_float8(v3
) << 24));
675 static inline struct brw_reg
676 brw_address(struct brw_reg reg
)
678 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
681 /** Construct float[1] general-purpose register */
682 static inline struct brw_reg
683 brw_vec1_grf(unsigned nr
, unsigned subnr
)
685 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
688 /** Construct float[2] general-purpose register */
689 static inline struct brw_reg
690 brw_vec2_grf(unsigned nr
, unsigned subnr
)
692 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
695 /** Construct float[4] general-purpose register */
696 static inline struct brw_reg
697 brw_vec4_grf(unsigned nr
, unsigned subnr
)
699 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
702 /** Construct float[8] general-purpose register */
703 static inline struct brw_reg
704 brw_vec8_grf(unsigned nr
, unsigned subnr
)
706 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
709 /** Construct float[16] general-purpose register */
710 static inline struct brw_reg
711 brw_vec16_grf(unsigned nr
, unsigned subnr
)
713 return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
717 static inline struct brw_reg
718 brw_uw8_grf(unsigned nr
, unsigned subnr
)
720 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
723 static inline struct brw_reg
724 brw_uw16_grf(unsigned nr
, unsigned subnr
)
726 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
730 /** Construct null register (usually used for setting condition codes) */
731 static inline struct brw_reg
734 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
737 static inline struct brw_reg
738 brw_null_vec(unsigned width
)
740 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
743 static inline struct brw_reg
744 brw_address_reg(unsigned subnr
)
746 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_ADDRESS
, subnr
);
749 /* If/else instructions break in align16 mode if writemask & swizzle
750 * aren't xyzw. This goes against the convention for other scalar
753 static inline struct brw_reg
756 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
761 BRW_REGISTER_TYPE_UD
,
762 BRW_VERTICAL_STRIDE_4
, /* ? */
764 BRW_HORIZONTAL_STRIDE_0
,
765 BRW_SWIZZLE_XYZW
, /* NOTE! */
766 WRITEMASK_XYZW
); /* NOTE! */
769 static inline struct brw_reg
770 brw_notification_reg(void)
772 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
773 BRW_ARF_NOTIFICATION_COUNT
,
777 BRW_REGISTER_TYPE_UD
,
778 BRW_VERTICAL_STRIDE_0
,
780 BRW_HORIZONTAL_STRIDE_0
,
785 static inline struct brw_reg
786 brw_acc_reg(unsigned width
)
788 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
,
789 BRW_ARF_ACCUMULATOR
, 0);
792 static inline struct brw_reg
793 brw_flag_reg(int reg
, int subreg
)
795 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
796 BRW_ARF_FLAG
+ reg
, subreg
);
800 * Return the mask register present in Gen4-5, or the related register present
801 * in Gen7.5 and later hardware referred to as "channel enable" register in
804 static inline struct brw_reg
805 brw_mask_reg(unsigned subnr
)
807 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_MASK
, subnr
);
810 static inline struct brw_reg
811 brw_message_reg(unsigned nr
)
813 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, nr
, 0);
816 static inline struct brw_reg
817 brw_uvec_mrf(unsigned width
, unsigned nr
, unsigned subnr
)
819 return retype(brw_vecn_reg(width
, BRW_MESSAGE_REGISTER_FILE
, nr
, subnr
),
820 BRW_REGISTER_TYPE_UD
);
823 /* This is almost always called with a numeric constant argument, so
824 * make things easy to evaluate at compile time:
826 static inline unsigned cvt(unsigned val
)
840 static inline struct brw_reg
841 stride(struct brw_reg reg
, unsigned vstride
, unsigned width
, unsigned hstride
)
843 reg
.vstride
= cvt(vstride
);
844 reg
.width
= cvt(width
) - 1;
845 reg
.hstride
= cvt(hstride
);
850 * Multiply the vertical and horizontal stride of a register by the given
853 static inline struct brw_reg
854 spread(struct brw_reg reg
, unsigned s
)
857 assert(_mesa_is_pow_two(s
));
860 reg
.hstride
+= cvt(s
) - 1;
863 reg
.vstride
+= cvt(s
) - 1;
867 return stride(reg
, 0, 1, 0);
871 static inline struct brw_reg
872 vec16(struct brw_reg reg
)
874 return stride(reg
, 16,16,1);
877 static inline struct brw_reg
878 vec8(struct brw_reg reg
)
880 return stride(reg
, 8,8,1);
883 static inline struct brw_reg
884 vec4(struct brw_reg reg
)
886 return stride(reg
, 4,4,1);
889 static inline struct brw_reg
890 vec2(struct brw_reg reg
)
892 return stride(reg
, 2,2,1);
895 static inline struct brw_reg
896 vec1(struct brw_reg reg
)
898 return stride(reg
, 0,1,0);
902 static inline struct brw_reg
903 get_element(struct brw_reg reg
, unsigned elt
)
905 return vec1(suboffset(reg
, elt
));
908 static inline struct brw_reg
909 get_element_ud(struct brw_reg reg
, unsigned elt
)
911 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
914 static inline struct brw_reg
915 get_element_d(struct brw_reg reg
, unsigned elt
)
917 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
921 static inline struct brw_reg
922 brw_swizzle(struct brw_reg reg
, unsigned x
, unsigned y
, unsigned z
, unsigned w
)
924 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
926 reg
.dw1
.bits
.swizzle
= brw_compose_swizzle(BRW_SWIZZLE4(x
, y
, z
, w
),
927 reg
.dw1
.bits
.swizzle
);
932 static inline struct brw_reg
933 brw_swizzle1(struct brw_reg reg
, unsigned x
)
935 return brw_swizzle(reg
, x
, x
, x
, x
);
938 static inline struct brw_reg
939 brw_writemask(struct brw_reg reg
, unsigned mask
)
941 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
942 reg
.dw1
.bits
.writemask
&= mask
;
946 static inline struct brw_reg
947 brw_set_writemask(struct brw_reg reg
, unsigned mask
)
949 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
950 reg
.dw1
.bits
.writemask
= mask
;
954 static inline unsigned
955 brw_writemask_for_size(unsigned n
)
960 static inline struct brw_reg
961 negate(struct brw_reg reg
)
967 static inline struct brw_reg
968 brw_abs(struct brw_reg reg
)
975 /************************************************************************/
977 static inline struct brw_reg
978 brw_vec4_indirect(unsigned subnr
, int offset
)
980 struct brw_reg reg
= brw_vec4_grf(0, 0);
982 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
983 reg
.dw1
.bits
.indirect_offset
= offset
;
987 static inline struct brw_reg
988 brw_vec1_indirect(unsigned subnr
, int offset
)
990 struct brw_reg reg
= brw_vec1_grf(0, 0);
992 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
993 reg
.dw1
.bits
.indirect_offset
= offset
;
997 static inline struct brw_reg
998 deref_4f(struct brw_indirect ptr
, int offset
)
1000 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1003 static inline struct brw_reg
1004 deref_1f(struct brw_indirect ptr
, int offset
)
1006 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1009 static inline struct brw_reg
1010 deref_4b(struct brw_indirect ptr
, int offset
)
1012 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
1015 static inline struct brw_reg
1016 deref_1uw(struct brw_indirect ptr
, int offset
)
1018 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
1021 static inline struct brw_reg
1022 deref_1d(struct brw_indirect ptr
, int offset
)
1024 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
1027 static inline struct brw_reg
1028 deref_1ud(struct brw_indirect ptr
, int offset
)
1030 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
1033 static inline struct brw_reg
1034 get_addr_reg(struct brw_indirect ptr
)
1036 return brw_address_reg(ptr
.addr_subnr
);
1039 static inline struct brw_indirect
1040 brw_indirect_offset(struct brw_indirect ptr
, int offset
)
1042 ptr
.addr_offset
+= offset
;
1046 static inline struct brw_indirect
1047 brw_indirect(unsigned addr_subnr
, int offset
)
1049 struct brw_indirect ptr
;
1050 ptr
.addr_subnr
= addr_subnr
;
1051 ptr
.addr_offset
= offset
;
1057 region_matches(struct brw_reg reg
, enum brw_vertical_stride v
,
1058 enum brw_width w
, enum brw_horizontal_stride h
)
1060 return reg
.vstride
== v
&&
1065 #define has_scalar_region(reg) \
1066 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
1067 BRW_HORIZONTAL_STRIDE_0)
1069 /* brw_packed_float.c */
1070 int brw_float_to_vf(float f
);
1071 float brw_vf_to_float(unsigned char vf
);