2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
46 #include "main/compiler.h"
47 #include "main/macros.h"
48 #include "program/prog_instruction.h"
49 #include "brw_defines.h"
55 struct brw_device_info
;
57 /** Number of general purpose registers (VS, WM, etc) */
58 #define BRW_MAX_GRF 128
61 * First GRF used for the MRF hack.
63 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
64 * haven't converted our compiler to be aware of this, so it asks for MRFs and
65 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
66 * register allocators have to be careful of this to avoid corrupting the "MRF"s
67 * with actual GRF allocations.
69 #define GEN7_MRF_HACK_START 112
71 /** Number of message register file registers */
72 #define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)
74 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
75 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
77 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
78 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
79 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
80 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
81 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
82 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
83 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
84 #define BRW_SWIZZLE_XZXZ BRW_SWIZZLE4(0,2,0,2)
85 #define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
86 #define BRW_SWIZZLE_YWYW BRW_SWIZZLE4(1,3,1,3)
87 #define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
88 #define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
89 #define BRW_SWIZZLE_WZYX BRW_SWIZZLE4(3,2,1,0)
92 brw_is_single_value_swizzle(unsigned swiz
)
94 return (swiz
== BRW_SWIZZLE_XXXX
||
95 swiz
== BRW_SWIZZLE_YYYY
||
96 swiz
== BRW_SWIZZLE_ZZZZ
||
97 swiz
== BRW_SWIZZLE_WWWW
);
101 * Compute the swizzle obtained from the application of \p swz0 on the result
102 * of \p swz1. The argument ordering is expected to match function
105 static inline unsigned
106 brw_compose_swizzle(unsigned swz0
, unsigned swz1
)
109 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 0)),
110 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 1)),
111 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 2)),
112 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 3)));
116 * Return the result of applying swizzle \p swz to shuffle the bits of \p mask
119 static inline unsigned
120 brw_apply_swizzle_to_mask(unsigned swz
, unsigned mask
)
124 for (unsigned i
= 0; i
< 4; i
++) {
125 if (mask
& (1 << BRW_GET_SWZ(swz
, i
)))
133 * Return the result of applying the inverse of swizzle \p swz to shuffle the
134 * bits of \p mask (AKA preimage). Useful to find out which components are
135 * read from a swizzled source given the instruction writemask.
137 static inline unsigned
138 brw_apply_inv_swizzle_to_mask(unsigned swz
, unsigned mask
)
142 for (unsigned i
= 0; i
< 4; i
++) {
144 result
|= 1 << BRW_GET_SWZ(swz
, i
);
151 * Construct an identity swizzle for the set of enabled channels given by \p
152 * mask. The result will only reference channels enabled in the provided \p
153 * mask, assuming that \p mask is non-zero. The constructed swizzle will
154 * satisfy the property that for any instruction OP and any mask:
156 * brw_OP(p, brw_writemask(dst, mask),
157 * brw_swizzle(src, brw_swizzle_for_mask(mask)));
159 * will be equivalent to the same instruction without swizzle:
161 * brw_OP(p, brw_writemask(dst, mask), src);
163 static inline unsigned
164 brw_swizzle_for_mask(unsigned mask
)
166 unsigned last
= (mask
? ffs(mask
) - 1 : 0);
169 for (unsigned i
= 0; i
< 4; i
++)
170 last
= swz
[i
] = (mask
& (1 << i
) ? i
: last
);
172 return BRW_SWIZZLE4(swz
[0], swz
[1], swz
[2], swz
[3]);
176 * Construct an identity swizzle for the first \p n components of a vector.
177 * When only a subset of channels of a vec4 are used we don't want to
178 * reference the other channels, as that will tell optimization passes that
179 * those other channels are used.
181 static inline unsigned
182 brw_swizzle_for_size(unsigned n
)
184 return brw_swizzle_for_mask((1 << n
) - 1);
188 * Converse of brw_swizzle_for_mask(). Returns the mask of components
189 * accessed by the specified swizzle \p swz.
191 static inline unsigned
192 brw_mask_for_swizzle(unsigned swz
)
194 return brw_apply_inv_swizzle_to_mask(swz
, ~0);
197 enum PACKED brw_reg_type
{
198 BRW_REGISTER_TYPE_UD
= 0,
200 BRW_REGISTER_TYPE_UW
,
204 /** Non-immediates only: @{ */
205 BRW_REGISTER_TYPE_UB
,
209 /** Immediates only: @{ */
210 BRW_REGISTER_TYPE_UV
, /* Gen6+ */
212 BRW_REGISTER_TYPE_VF
,
215 BRW_REGISTER_TYPE_DF
, /* Gen7+ (no immediates until Gen8+) */
218 BRW_REGISTER_TYPE_HF
,
219 BRW_REGISTER_TYPE_UQ
,
223 unsigned brw_reg_type_to_hw_type(const struct brw_device_info
*devinfo
,
224 enum brw_reg_type type
, enum brw_reg_file file
);
225 const char *brw_reg_type_letters(unsigned brw_reg_type
);
226 uint32_t brw_swizzle_immediate(enum brw_reg_type type
, uint32_t x
, unsigned swz
);
228 #define REG_SIZE (8*4)
230 /* These aren't hardware structs, just something useful for us to pass around:
232 * Align1 operation has a lot of control over input ranges. Used in
233 * WM programs to implement shaders decomposed into "channel serial"
234 * or "structure of array" form:
239 enum brw_reg_type type
:4;
240 enum brw_reg_file file
:3; /* :2 hardware format */
241 unsigned negate
:1; /* source only */
242 unsigned abs
:1; /* source only */
243 unsigned address_mode
:1; /* relative addressing, hopefully! */
245 unsigned subnr
:5; /* :1 in align16 */
253 unsigned swizzle
:8; /* src only, align16 only */
254 unsigned writemask
:4; /* dest only, align16 only */
255 int indirect_offset
:10; /* relative addressing offset */
256 unsigned vstride
:4; /* source only */
257 unsigned width
:3; /* src only, align1 only */
258 unsigned hstride
:2; /* align1 only */
271 brw_regs_equal(const struct brw_reg
*a
, const struct brw_reg
*b
)
273 const bool df
= a
->type
== BRW_REGISTER_TYPE_DF
&& a
->file
== IMM
;
274 return a
->bits
== b
->bits
&& (df
? a
->u64
== b
->u64
: a
->ud
== b
->ud
);
277 struct brw_indirect
{
278 unsigned addr_subnr
:4;
284 static inline unsigned
285 type_sz(unsigned type
)
288 case BRW_REGISTER_TYPE_UQ
:
289 case BRW_REGISTER_TYPE_Q
:
290 case BRW_REGISTER_TYPE_DF
:
292 case BRW_REGISTER_TYPE_UD
:
293 case BRW_REGISTER_TYPE_D
:
294 case BRW_REGISTER_TYPE_F
:
295 case BRW_REGISTER_TYPE_VF
:
297 case BRW_REGISTER_TYPE_UW
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_UV
:
300 case BRW_REGISTER_TYPE_V
:
301 case BRW_REGISTER_TYPE_HF
:
303 case BRW_REGISTER_TYPE_UB
:
304 case BRW_REGISTER_TYPE_B
:
307 unreachable("not reached");
312 * Return an integer type of the requested size and signedness.
314 static inline enum brw_reg_type
315 brw_int_type(unsigned sz
, bool is_signed
)
319 return (is_signed
? BRW_REGISTER_TYPE_B
: BRW_REGISTER_TYPE_UB
);
321 return (is_signed
? BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
323 return (is_signed
? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_UD
);
325 return (is_signed
? BRW_REGISTER_TYPE_Q
: BRW_REGISTER_TYPE_UQ
);
327 unreachable("Not reached.");
332 * Construct a brw_reg.
333 * \param file one of the BRW_x_REGISTER_FILE values
334 * \param nr register number/index
335 * \param subnr register sub number
336 * \param negate register negate modifier
337 * \param abs register abs modifier
338 * \param type one of BRW_REGISTER_TYPE_x
339 * \param vstride one of BRW_VERTICAL_STRIDE_x
340 * \param width one of BRW_WIDTH_x
341 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
342 * \param swizzle one of BRW_SWIZZLE_x
343 * \param writemask WRITEMASK_X/Y/Z/W bitfield
345 static inline struct brw_reg
346 brw_reg(enum brw_reg_file file
,
351 enum brw_reg_type type
,
359 if (file
== BRW_GENERAL_REGISTER_FILE
)
360 assert(nr
< BRW_MAX_GRF
);
361 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
362 assert(nr
<= BRW_ARF_TIMESTAMP
);
363 /* Asserting on the MRF register number requires to know the hardware gen
364 * (gen6 has 24 MRF registers), which we don't know here, so we assert
365 * for that in the generators and in brw_eu_emit.c
372 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
374 reg
.subnr
= subnr
* type_sz(type
);
377 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
378 * set swizzle and writemask to W, as the lower bits of subnr will
379 * be lost when converted to align16. This is probably too much to
380 * keep track of as you'd want it adjusted by suboffset(), etc.
381 * Perhaps fix up when converting to align16?
383 reg
.swizzle
= swizzle
;
384 reg
.writemask
= writemask
;
385 reg
.indirect_offset
= 0;
386 reg
.vstride
= vstride
;
388 reg
.hstride
= hstride
;
393 /** Construct float[16] register */
394 static inline struct brw_reg
395 brw_vec16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
403 BRW_VERTICAL_STRIDE_16
,
405 BRW_HORIZONTAL_STRIDE_1
,
410 /** Construct float[8] register */
411 static inline struct brw_reg
412 brw_vec8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
420 BRW_VERTICAL_STRIDE_8
,
422 BRW_HORIZONTAL_STRIDE_1
,
427 /** Construct float[4] register */
428 static inline struct brw_reg
429 brw_vec4_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
437 BRW_VERTICAL_STRIDE_4
,
439 BRW_HORIZONTAL_STRIDE_1
,
444 /** Construct float[2] register */
445 static inline struct brw_reg
446 brw_vec2_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
454 BRW_VERTICAL_STRIDE_2
,
456 BRW_HORIZONTAL_STRIDE_1
,
461 /** Construct float[1] register */
462 static inline struct brw_reg
463 brw_vec1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
471 BRW_VERTICAL_STRIDE_0
,
473 BRW_HORIZONTAL_STRIDE_0
,
478 static inline struct brw_reg
479 brw_vecn_reg(unsigned width
, enum brw_reg_file file
,
480 unsigned nr
, unsigned subnr
)
484 return brw_vec1_reg(file
, nr
, subnr
);
486 return brw_vec2_reg(file
, nr
, subnr
);
488 return brw_vec4_reg(file
, nr
, subnr
);
490 return brw_vec8_reg(file
, nr
, subnr
);
492 return brw_vec16_reg(file
, nr
, subnr
);
494 unreachable("Invalid register width");
498 static inline struct brw_reg
499 retype(struct brw_reg reg
, enum brw_reg_type type
)
505 static inline struct brw_reg
506 firsthalf(struct brw_reg reg
)
511 static inline struct brw_reg
512 sechalf(struct brw_reg reg
)
519 static inline struct brw_reg
520 suboffset(struct brw_reg reg
, unsigned delta
)
522 reg
.subnr
+= delta
* type_sz(reg
.type
);
527 static inline struct brw_reg
528 offset(struct brw_reg reg
, unsigned delta
)
535 static inline struct brw_reg
536 byte_offset(struct brw_reg reg
, unsigned bytes
)
538 unsigned newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
539 reg
.nr
= newoffset
/ REG_SIZE
;
540 reg
.subnr
= newoffset
% REG_SIZE
;
545 /** Construct unsigned word[16] register */
546 static inline struct brw_reg
547 brw_uw16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
549 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
552 /** Construct unsigned word[8] register */
553 static inline struct brw_reg
554 brw_uw8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
556 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
559 /** Construct unsigned word[1] register */
560 static inline struct brw_reg
561 brw_uw1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
563 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
566 static inline struct brw_reg
567 brw_imm_reg(enum brw_reg_type type
)
569 return brw_reg(BRW_IMMEDIATE_VALUE
,
575 BRW_VERTICAL_STRIDE_0
,
577 BRW_HORIZONTAL_STRIDE_0
,
582 /** Construct float immediate register */
583 static inline struct brw_reg
584 brw_imm_df(double df
)
586 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_DF
);
591 static inline struct brw_reg
594 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
599 /** Construct integer immediate register */
600 static inline struct brw_reg
603 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
608 /** Construct uint immediate register */
609 static inline struct brw_reg
610 brw_imm_ud(unsigned ud
)
612 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
617 /** Construct ushort immediate register */
618 static inline struct brw_reg
619 brw_imm_uw(uint16_t uw
)
621 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
622 imm
.ud
= uw
| (uw
<< 16);
626 /** Construct short immediate register */
627 static inline struct brw_reg
630 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
631 imm
.d
= w
| (w
<< 16);
635 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
636 * numbers alias with _V and _VF below:
639 /** Construct vector of eight signed half-byte values */
640 static inline struct brw_reg
641 brw_imm_v(unsigned v
)
643 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
648 /** Construct vector of eight unsigned half-byte values */
649 static inline struct brw_reg
650 brw_imm_uv(unsigned uv
)
652 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UV
);
657 /** Construct vector of four 8-bit float values */
658 static inline struct brw_reg
659 brw_imm_vf(unsigned v
)
661 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
666 static inline struct brw_reg
667 brw_imm_vf4(unsigned v0
, unsigned v1
, unsigned v2
, unsigned v3
)
669 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
670 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
671 imm
.width
= BRW_WIDTH_4
;
672 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
673 imm
.ud
= ((v0
<< 0) | (v1
<< 8) | (v2
<< 16) | (v3
<< 24));
678 static inline struct brw_reg
679 brw_address(struct brw_reg reg
)
681 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
684 /** Construct float[1] general-purpose register */
685 static inline struct brw_reg
686 brw_vec1_grf(unsigned nr
, unsigned subnr
)
688 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
691 /** Construct float[2] general-purpose register */
692 static inline struct brw_reg
693 brw_vec2_grf(unsigned nr
, unsigned subnr
)
695 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
698 /** Construct float[4] general-purpose register */
699 static inline struct brw_reg
700 brw_vec4_grf(unsigned nr
, unsigned subnr
)
702 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
705 /** Construct float[8] general-purpose register */
706 static inline struct brw_reg
707 brw_vec8_grf(unsigned nr
, unsigned subnr
)
709 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
712 /** Construct float[16] general-purpose register */
713 static inline struct brw_reg
714 brw_vec16_grf(unsigned nr
, unsigned subnr
)
716 return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
720 static inline struct brw_reg
721 brw_uw8_grf(unsigned nr
, unsigned subnr
)
723 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
726 static inline struct brw_reg
727 brw_uw16_grf(unsigned nr
, unsigned subnr
)
729 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
733 /** Construct null register (usually used for setting condition codes) */
734 static inline struct brw_reg
737 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
740 static inline struct brw_reg
741 brw_null_vec(unsigned width
)
743 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
746 static inline struct brw_reg
747 brw_address_reg(unsigned subnr
)
749 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_ADDRESS
, subnr
);
752 /* If/else instructions break in align16 mode if writemask & swizzle
753 * aren't xyzw. This goes against the convention for other scalar
756 static inline struct brw_reg
759 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
764 BRW_REGISTER_TYPE_UD
,
765 BRW_VERTICAL_STRIDE_4
, /* ? */
767 BRW_HORIZONTAL_STRIDE_0
,
768 BRW_SWIZZLE_XYZW
, /* NOTE! */
769 WRITEMASK_XYZW
); /* NOTE! */
772 static inline struct brw_reg
773 brw_notification_reg(void)
775 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
776 BRW_ARF_NOTIFICATION_COUNT
,
780 BRW_REGISTER_TYPE_UD
,
781 BRW_VERTICAL_STRIDE_0
,
783 BRW_HORIZONTAL_STRIDE_0
,
788 static inline struct brw_reg
791 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
796 BRW_REGISTER_TYPE_UD
,
797 BRW_VERTICAL_STRIDE_8
,
799 BRW_HORIZONTAL_STRIDE_1
,
804 static inline struct brw_reg
805 brw_acc_reg(unsigned width
)
807 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
,
808 BRW_ARF_ACCUMULATOR
, 0);
811 static inline struct brw_reg
812 brw_flag_reg(int reg
, int subreg
)
814 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
815 BRW_ARF_FLAG
+ reg
, subreg
);
819 * Return the mask register present in Gen4-5, or the related register present
820 * in Gen7.5 and later hardware referred to as "channel enable" register in
823 static inline struct brw_reg
824 brw_mask_reg(unsigned subnr
)
826 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_MASK
, subnr
);
829 static inline struct brw_reg
830 brw_message_reg(unsigned nr
)
832 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, nr
, 0);
835 static inline struct brw_reg
836 brw_uvec_mrf(unsigned width
, unsigned nr
, unsigned subnr
)
838 return retype(brw_vecn_reg(width
, BRW_MESSAGE_REGISTER_FILE
, nr
, subnr
),
839 BRW_REGISTER_TYPE_UD
);
842 /* This is almost always called with a numeric constant argument, so
843 * make things easy to evaluate at compile time:
845 static inline unsigned cvt(unsigned val
)
859 static inline struct brw_reg
860 stride(struct brw_reg reg
, unsigned vstride
, unsigned width
, unsigned hstride
)
862 reg
.vstride
= cvt(vstride
);
863 reg
.width
= cvt(width
) - 1;
864 reg
.hstride
= cvt(hstride
);
869 * Multiply the vertical and horizontal stride of a register by the given
872 static inline struct brw_reg
873 spread(struct brw_reg reg
, unsigned s
)
876 assert(_mesa_is_pow_two(s
));
879 reg
.hstride
+= cvt(s
) - 1;
882 reg
.vstride
+= cvt(s
) - 1;
886 return stride(reg
, 0, 1, 0);
890 static inline struct brw_reg
891 vec16(struct brw_reg reg
)
893 return stride(reg
, 16,16,1);
896 static inline struct brw_reg
897 vec8(struct brw_reg reg
)
899 return stride(reg
, 8,8,1);
902 static inline struct brw_reg
903 vec4(struct brw_reg reg
)
905 return stride(reg
, 4,4,1);
908 static inline struct brw_reg
909 vec2(struct brw_reg reg
)
911 return stride(reg
, 2,2,1);
914 static inline struct brw_reg
915 vec1(struct brw_reg reg
)
917 return stride(reg
, 0,1,0);
921 static inline struct brw_reg
922 get_element(struct brw_reg reg
, unsigned elt
)
924 return vec1(suboffset(reg
, elt
));
927 static inline struct brw_reg
928 get_element_ud(struct brw_reg reg
, unsigned elt
)
930 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
933 static inline struct brw_reg
934 get_element_d(struct brw_reg reg
, unsigned elt
)
936 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
939 static inline struct brw_reg
940 brw_swizzle(struct brw_reg reg
, unsigned swz
)
942 if (reg
.file
== BRW_IMMEDIATE_VALUE
)
943 reg
.ud
= brw_swizzle_immediate(reg
.type
, reg
.ud
, swz
);
945 reg
.swizzle
= brw_compose_swizzle(swz
, reg
.swizzle
);
950 static inline struct brw_reg
951 brw_writemask(struct brw_reg reg
, unsigned mask
)
953 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
954 reg
.writemask
&= mask
;
958 static inline struct brw_reg
959 brw_set_writemask(struct brw_reg reg
, unsigned mask
)
961 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
962 reg
.writemask
= mask
;
966 static inline unsigned
967 brw_writemask_for_size(unsigned n
)
972 static inline struct brw_reg
973 negate(struct brw_reg reg
)
979 static inline struct brw_reg
980 brw_abs(struct brw_reg reg
)
987 /************************************************************************/
989 static inline struct brw_reg
990 brw_vec4_indirect(unsigned subnr
, int offset
)
992 struct brw_reg reg
= brw_vec4_grf(0, 0);
994 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
995 reg
.indirect_offset
= offset
;
999 static inline struct brw_reg
1000 brw_vec1_indirect(unsigned subnr
, int offset
)
1002 struct brw_reg reg
= brw_vec1_grf(0, 0);
1004 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1005 reg
.indirect_offset
= offset
;
1009 static inline struct brw_reg
1010 brw_VxH_indirect(unsigned subnr
, int offset
)
1012 struct brw_reg reg
= brw_vec1_grf(0, 0);
1013 reg
.vstride
= BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL
;
1015 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1016 reg
.indirect_offset
= offset
;
1020 static inline struct brw_reg
1021 deref_4f(struct brw_indirect ptr
, int offset
)
1023 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1026 static inline struct brw_reg
1027 deref_1f(struct brw_indirect ptr
, int offset
)
1029 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1032 static inline struct brw_reg
1033 deref_4b(struct brw_indirect ptr
, int offset
)
1035 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
1038 static inline struct brw_reg
1039 deref_1uw(struct brw_indirect ptr
, int offset
)
1041 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
1044 static inline struct brw_reg
1045 deref_1d(struct brw_indirect ptr
, int offset
)
1047 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
1050 static inline struct brw_reg
1051 deref_1ud(struct brw_indirect ptr
, int offset
)
1053 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
1056 static inline struct brw_reg
1057 get_addr_reg(struct brw_indirect ptr
)
1059 return brw_address_reg(ptr
.addr_subnr
);
1062 static inline struct brw_indirect
1063 brw_indirect_offset(struct brw_indirect ptr
, int offset
)
1065 ptr
.addr_offset
+= offset
;
1069 static inline struct brw_indirect
1070 brw_indirect(unsigned addr_subnr
, int offset
)
1072 struct brw_indirect ptr
;
1073 ptr
.addr_subnr
= addr_subnr
;
1074 ptr
.addr_offset
= offset
;
1080 region_matches(struct brw_reg reg
, enum brw_vertical_stride v
,
1081 enum brw_width w
, enum brw_horizontal_stride h
)
1083 return reg
.vstride
== v
&&
1088 #define has_scalar_region(reg) \
1089 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
1090 BRW_HORIZONTAL_STRIDE_0)
1092 /* brw_packed_float.c */
1093 int brw_float_to_vf(float f
);
1094 float brw_vf_to_float(unsigned char vf
);