2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
46 #include "main/compiler.h"
47 #include "main/macros.h"
48 #include "program/prog_instruction.h"
49 #include "brw_defines.h"
55 struct brw_device_info
;
57 /** Number of general purpose registers (VS, WM, etc) */
58 #define BRW_MAX_GRF 128
61 * First GRF used for the MRF hack.
63 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
64 * haven't converted our compiler to be aware of this, so it asks for MRFs and
65 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
66 * register allocators have to be careful of this to avoid corrupting the "MRF"s
67 * with actual GRF allocations.
69 #define GEN7_MRF_HACK_START 112
71 /** Number of message register file registers */
72 #define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)
74 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
75 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
77 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
78 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
79 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
80 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
81 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
82 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
83 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
84 #define BRW_SWIZZLE_XZXZ BRW_SWIZZLE4(0,2,0,2)
85 #define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
86 #define BRW_SWIZZLE_YWYW BRW_SWIZZLE4(1,3,1,3)
87 #define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
88 #define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
89 #define BRW_SWIZZLE_WZYX BRW_SWIZZLE4(3,2,1,0)
92 brw_is_single_value_swizzle(unsigned swiz
)
94 return (swiz
== BRW_SWIZZLE_XXXX
||
95 swiz
== BRW_SWIZZLE_YYYY
||
96 swiz
== BRW_SWIZZLE_ZZZZ
||
97 swiz
== BRW_SWIZZLE_WWWW
);
101 * Compute the swizzle obtained from the application of \p swz0 on the result
102 * of \p swz1. The argument ordering is expected to match function
105 static inline unsigned
106 brw_compose_swizzle(unsigned swz0
, unsigned swz1
)
109 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 0)),
110 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 1)),
111 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 2)),
112 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 3)));
116 * Return the result of applying swizzle \p swz to shuffle the bits of \p mask
119 static inline unsigned
120 brw_apply_swizzle_to_mask(unsigned swz
, unsigned mask
)
124 for (unsigned i
= 0; i
< 4; i
++) {
125 if (mask
& (1 << BRW_GET_SWZ(swz
, i
)))
133 * Return the result of applying the inverse of swizzle \p swz to shuffle the
134 * bits of \p mask (AKA preimage). Useful to find out which components are
135 * read from a swizzled source given the instruction writemask.
137 static inline unsigned
138 brw_apply_inv_swizzle_to_mask(unsigned swz
, unsigned mask
)
142 for (unsigned i
= 0; i
< 4; i
++) {
144 result
|= 1 << BRW_GET_SWZ(swz
, i
);
151 * Construct an identity swizzle for the set of enabled channels given by \p
152 * mask. The result will only reference channels enabled in the provided \p
153 * mask, assuming that \p mask is non-zero. The constructed swizzle will
154 * satisfy the property that for any instruction OP and any mask:
156 * brw_OP(p, brw_writemask(dst, mask),
157 * brw_swizzle(src, brw_swizzle_for_mask(mask)));
159 * will be equivalent to the same instruction without swizzle:
161 * brw_OP(p, brw_writemask(dst, mask), src);
163 static inline unsigned
164 brw_swizzle_for_mask(unsigned mask
)
166 unsigned last
= (mask
? ffs(mask
) - 1 : 0);
169 for (unsigned i
= 0; i
< 4; i
++)
170 last
= swz
[i
] = (mask
& (1 << i
) ? i
: last
);
172 return BRW_SWIZZLE4(swz
[0], swz
[1], swz
[2], swz
[3]);
176 * Construct an identity swizzle for the first \p n components of a vector.
177 * When only a subset of channels of a vec4 are used we don't want to
178 * reference the other channels, as that will tell optimization passes that
179 * those other channels are used.
181 static inline unsigned
182 brw_swizzle_for_size(unsigned n
)
184 return brw_swizzle_for_mask((1 << n
) - 1);
188 * Converse of brw_swizzle_for_mask(). Returns the mask of components
189 * accessed by the specified swizzle \p swz.
191 static inline unsigned
192 brw_mask_for_swizzle(unsigned swz
)
194 return brw_apply_inv_swizzle_to_mask(swz
, ~0);
197 enum PACKED brw_reg_type
{
198 BRW_REGISTER_TYPE_UD
= 0,
200 BRW_REGISTER_TYPE_UW
,
204 /** Non-immediates only: @{ */
205 BRW_REGISTER_TYPE_UB
,
209 /** Immediates only: @{ */
210 BRW_REGISTER_TYPE_UV
, /* Gen6+ */
212 BRW_REGISTER_TYPE_VF
,
215 BRW_REGISTER_TYPE_DF
, /* Gen7+ (no immediates until Gen8+) */
218 BRW_REGISTER_TYPE_HF
,
219 BRW_REGISTER_TYPE_UQ
,
223 unsigned brw_reg_type_to_hw_type(const struct brw_device_info
*devinfo
,
224 enum brw_reg_type type
, enum brw_reg_file file
);
225 const char *brw_reg_type_letters(unsigned brw_reg_type
);
226 uint32_t brw_swizzle_immediate(enum brw_reg_type type
, uint32_t x
, unsigned swz
);
228 #define REG_SIZE (8*4)
230 /* These aren't hardware structs, just something useful for us to pass around:
232 * Align1 operation has a lot of control over input ranges. Used in
233 * WM programs to implement shaders decomposed into "channel serial"
234 * or "structure of array" form:
239 enum brw_reg_type type
:4;
240 enum brw_reg_file file
:3; /* :2 hardware format */
241 unsigned negate
:1; /* source only */
242 unsigned abs
:1; /* source only */
243 unsigned address_mode
:1; /* relative addressing, hopefully! */
245 unsigned subnr
:5; /* :1 in align16 */
253 unsigned swizzle
:8; /* src only, align16 only */
254 unsigned writemask
:4; /* dest only, align16 only */
255 int indirect_offset
:10; /* relative addressing offset */
256 unsigned vstride
:4; /* source only */
257 unsigned width
:3; /* src only, align1 only */
258 unsigned hstride
:2; /* align1 only */
271 brw_regs_equal(const struct brw_reg
*a
, const struct brw_reg
*b
)
273 const bool df
= a
->type
== BRW_REGISTER_TYPE_DF
&& a
->file
== IMM
;
274 return a
->bits
== b
->bits
&& (df
? a
->u64
== b
->u64
: a
->ud
== b
->ud
);
277 struct brw_indirect
{
278 unsigned addr_subnr
:4;
284 static inline unsigned
285 type_sz(unsigned type
)
288 case BRW_REGISTER_TYPE_UQ
:
289 case BRW_REGISTER_TYPE_Q
:
290 case BRW_REGISTER_TYPE_DF
:
292 case BRW_REGISTER_TYPE_UD
:
293 case BRW_REGISTER_TYPE_D
:
294 case BRW_REGISTER_TYPE_F
:
296 case BRW_REGISTER_TYPE_UW
:
297 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_UB
:
300 case BRW_REGISTER_TYPE_B
:
308 * Return an integer type of the requested size and signedness.
310 static inline enum brw_reg_type
311 brw_int_type(unsigned sz
, bool is_signed
)
315 return (is_signed
? BRW_REGISTER_TYPE_B
: BRW_REGISTER_TYPE_UB
);
317 return (is_signed
? BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
319 return (is_signed
? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_UD
);
321 return (is_signed
? BRW_REGISTER_TYPE_Q
: BRW_REGISTER_TYPE_UQ
);
323 unreachable("Not reached.");
328 * Construct a brw_reg.
329 * \param file one of the BRW_x_REGISTER_FILE values
330 * \param nr register number/index
331 * \param subnr register sub number
332 * \param negate register negate modifier
333 * \param abs register abs modifier
334 * \param type one of BRW_REGISTER_TYPE_x
335 * \param vstride one of BRW_VERTICAL_STRIDE_x
336 * \param width one of BRW_WIDTH_x
337 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
338 * \param swizzle one of BRW_SWIZZLE_x
339 * \param writemask WRITEMASK_X/Y/Z/W bitfield
341 static inline struct brw_reg
342 brw_reg(enum brw_reg_file file
,
347 enum brw_reg_type type
,
355 if (file
== BRW_GENERAL_REGISTER_FILE
)
356 assert(nr
< BRW_MAX_GRF
);
357 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
358 assert(nr
<= BRW_ARF_TIMESTAMP
);
359 /* Asserting on the MRF register number requires to know the hardware gen
360 * (gen6 has 24 MRF registers), which we don't know here, so we assert
361 * for that in the generators and in brw_eu_emit.c
368 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
370 reg
.subnr
= subnr
* type_sz(type
);
373 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
374 * set swizzle and writemask to W, as the lower bits of subnr will
375 * be lost when converted to align16. This is probably too much to
376 * keep track of as you'd want it adjusted by suboffset(), etc.
377 * Perhaps fix up when converting to align16?
379 reg
.swizzle
= swizzle
;
380 reg
.writemask
= writemask
;
381 reg
.indirect_offset
= 0;
382 reg
.vstride
= vstride
;
384 reg
.hstride
= hstride
;
389 /** Construct float[16] register */
390 static inline struct brw_reg
391 brw_vec16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
399 BRW_VERTICAL_STRIDE_16
,
401 BRW_HORIZONTAL_STRIDE_1
,
406 /** Construct float[8] register */
407 static inline struct brw_reg
408 brw_vec8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
416 BRW_VERTICAL_STRIDE_8
,
418 BRW_HORIZONTAL_STRIDE_1
,
423 /** Construct float[4] register */
424 static inline struct brw_reg
425 brw_vec4_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
433 BRW_VERTICAL_STRIDE_4
,
435 BRW_HORIZONTAL_STRIDE_1
,
440 /** Construct float[2] register */
441 static inline struct brw_reg
442 brw_vec2_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
450 BRW_VERTICAL_STRIDE_2
,
452 BRW_HORIZONTAL_STRIDE_1
,
457 /** Construct float[1] register */
458 static inline struct brw_reg
459 brw_vec1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
467 BRW_VERTICAL_STRIDE_0
,
469 BRW_HORIZONTAL_STRIDE_0
,
474 static inline struct brw_reg
475 brw_vecn_reg(unsigned width
, enum brw_reg_file file
,
476 unsigned nr
, unsigned subnr
)
480 return brw_vec1_reg(file
, nr
, subnr
);
482 return brw_vec2_reg(file
, nr
, subnr
);
484 return brw_vec4_reg(file
, nr
, subnr
);
486 return brw_vec8_reg(file
, nr
, subnr
);
488 return brw_vec16_reg(file
, nr
, subnr
);
490 unreachable("Invalid register width");
494 static inline struct brw_reg
495 retype(struct brw_reg reg
, enum brw_reg_type type
)
501 static inline struct brw_reg
502 firsthalf(struct brw_reg reg
)
507 static inline struct brw_reg
508 sechalf(struct brw_reg reg
)
515 static inline struct brw_reg
516 suboffset(struct brw_reg reg
, unsigned delta
)
518 reg
.subnr
+= delta
* type_sz(reg
.type
);
523 static inline struct brw_reg
524 offset(struct brw_reg reg
, unsigned delta
)
531 static inline struct brw_reg
532 byte_offset(struct brw_reg reg
, unsigned bytes
)
534 unsigned newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
535 reg
.nr
= newoffset
/ REG_SIZE
;
536 reg
.subnr
= newoffset
% REG_SIZE
;
541 /** Construct unsigned word[16] register */
542 static inline struct brw_reg
543 brw_uw16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
545 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
548 /** Construct unsigned word[8] register */
549 static inline struct brw_reg
550 brw_uw8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
552 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
555 /** Construct unsigned word[1] register */
556 static inline struct brw_reg
557 brw_uw1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
559 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
562 static inline struct brw_reg
563 brw_imm_reg(enum brw_reg_type type
)
565 return brw_reg(BRW_IMMEDIATE_VALUE
,
571 BRW_VERTICAL_STRIDE_0
,
573 BRW_HORIZONTAL_STRIDE_0
,
578 /** Construct float immediate register */
579 static inline struct brw_reg
580 brw_imm_df(double df
)
582 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_DF
);
587 static inline struct brw_reg
590 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
595 /** Construct integer immediate register */
596 static inline struct brw_reg
599 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
604 /** Construct uint immediate register */
605 static inline struct brw_reg
606 brw_imm_ud(unsigned ud
)
608 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
613 /** Construct ushort immediate register */
614 static inline struct brw_reg
615 brw_imm_uw(uint16_t uw
)
617 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
618 imm
.ud
= uw
| (uw
<< 16);
622 /** Construct short immediate register */
623 static inline struct brw_reg
626 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
627 imm
.d
= w
| (w
<< 16);
631 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
632 * numbers alias with _V and _VF below:
635 /** Construct vector of eight signed half-byte values */
636 static inline struct brw_reg
637 brw_imm_v(unsigned v
)
639 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
644 /** Construct vector of eight unsigned half-byte values */
645 static inline struct brw_reg
646 brw_imm_uv(unsigned uv
)
648 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UV
);
653 /** Construct vector of four 8-bit float values */
654 static inline struct brw_reg
655 brw_imm_vf(unsigned v
)
657 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
662 static inline struct brw_reg
663 brw_imm_vf4(unsigned v0
, unsigned v1
, unsigned v2
, unsigned v3
)
665 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
666 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
667 imm
.width
= BRW_WIDTH_4
;
668 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
669 imm
.ud
= ((v0
<< 0) | (v1
<< 8) | (v2
<< 16) | (v3
<< 24));
674 static inline struct brw_reg
675 brw_address(struct brw_reg reg
)
677 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
680 /** Construct float[1] general-purpose register */
681 static inline struct brw_reg
682 brw_vec1_grf(unsigned nr
, unsigned subnr
)
684 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
687 /** Construct float[2] general-purpose register */
688 static inline struct brw_reg
689 brw_vec2_grf(unsigned nr
, unsigned subnr
)
691 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
694 /** Construct float[4] general-purpose register */
695 static inline struct brw_reg
696 brw_vec4_grf(unsigned nr
, unsigned subnr
)
698 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
701 /** Construct float[8] general-purpose register */
702 static inline struct brw_reg
703 brw_vec8_grf(unsigned nr
, unsigned subnr
)
705 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
708 /** Construct float[16] general-purpose register */
709 static inline struct brw_reg
710 brw_vec16_grf(unsigned nr
, unsigned subnr
)
712 return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
716 static inline struct brw_reg
717 brw_uw8_grf(unsigned nr
, unsigned subnr
)
719 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
722 static inline struct brw_reg
723 brw_uw16_grf(unsigned nr
, unsigned subnr
)
725 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
729 /** Construct null register (usually used for setting condition codes) */
730 static inline struct brw_reg
733 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
736 static inline struct brw_reg
737 brw_null_vec(unsigned width
)
739 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
742 static inline struct brw_reg
743 brw_address_reg(unsigned subnr
)
745 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_ADDRESS
, subnr
);
748 /* If/else instructions break in align16 mode if writemask & swizzle
749 * aren't xyzw. This goes against the convention for other scalar
752 static inline struct brw_reg
755 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
760 BRW_REGISTER_TYPE_UD
,
761 BRW_VERTICAL_STRIDE_4
, /* ? */
763 BRW_HORIZONTAL_STRIDE_0
,
764 BRW_SWIZZLE_XYZW
, /* NOTE! */
765 WRITEMASK_XYZW
); /* NOTE! */
768 static inline struct brw_reg
769 brw_notification_reg(void)
771 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
772 BRW_ARF_NOTIFICATION_COUNT
,
776 BRW_REGISTER_TYPE_UD
,
777 BRW_VERTICAL_STRIDE_0
,
779 BRW_HORIZONTAL_STRIDE_0
,
784 static inline struct brw_reg
787 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
792 BRW_REGISTER_TYPE_UD
,
793 BRW_VERTICAL_STRIDE_8
,
795 BRW_HORIZONTAL_STRIDE_1
,
800 static inline struct brw_reg
801 brw_acc_reg(unsigned width
)
803 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
,
804 BRW_ARF_ACCUMULATOR
, 0);
807 static inline struct brw_reg
808 brw_flag_reg(int reg
, int subreg
)
810 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
811 BRW_ARF_FLAG
+ reg
, subreg
);
815 * Return the mask register present in Gen4-5, or the related register present
816 * in Gen7.5 and later hardware referred to as "channel enable" register in
819 static inline struct brw_reg
820 brw_mask_reg(unsigned subnr
)
822 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_MASK
, subnr
);
825 static inline struct brw_reg
826 brw_message_reg(unsigned nr
)
828 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, nr
, 0);
831 static inline struct brw_reg
832 brw_uvec_mrf(unsigned width
, unsigned nr
, unsigned subnr
)
834 return retype(brw_vecn_reg(width
, BRW_MESSAGE_REGISTER_FILE
, nr
, subnr
),
835 BRW_REGISTER_TYPE_UD
);
838 /* This is almost always called with a numeric constant argument, so
839 * make things easy to evaluate at compile time:
841 static inline unsigned cvt(unsigned val
)
855 static inline struct brw_reg
856 stride(struct brw_reg reg
, unsigned vstride
, unsigned width
, unsigned hstride
)
858 reg
.vstride
= cvt(vstride
);
859 reg
.width
= cvt(width
) - 1;
860 reg
.hstride
= cvt(hstride
);
865 * Multiply the vertical and horizontal stride of a register by the given
868 static inline struct brw_reg
869 spread(struct brw_reg reg
, unsigned s
)
872 assert(_mesa_is_pow_two(s
));
875 reg
.hstride
+= cvt(s
) - 1;
878 reg
.vstride
+= cvt(s
) - 1;
882 return stride(reg
, 0, 1, 0);
886 static inline struct brw_reg
887 vec16(struct brw_reg reg
)
889 return stride(reg
, 16,16,1);
892 static inline struct brw_reg
893 vec8(struct brw_reg reg
)
895 return stride(reg
, 8,8,1);
898 static inline struct brw_reg
899 vec4(struct brw_reg reg
)
901 return stride(reg
, 4,4,1);
904 static inline struct brw_reg
905 vec2(struct brw_reg reg
)
907 return stride(reg
, 2,2,1);
910 static inline struct brw_reg
911 vec1(struct brw_reg reg
)
913 return stride(reg
, 0,1,0);
917 static inline struct brw_reg
918 get_element(struct brw_reg reg
, unsigned elt
)
920 return vec1(suboffset(reg
, elt
));
923 static inline struct brw_reg
924 get_element_ud(struct brw_reg reg
, unsigned elt
)
926 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
929 static inline struct brw_reg
930 get_element_d(struct brw_reg reg
, unsigned elt
)
932 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
935 static inline struct brw_reg
936 brw_swizzle(struct brw_reg reg
, unsigned swz
)
938 if (reg
.file
== BRW_IMMEDIATE_VALUE
)
939 reg
.ud
= brw_swizzle_immediate(reg
.type
, reg
.ud
, swz
);
941 reg
.swizzle
= brw_compose_swizzle(swz
, reg
.swizzle
);
946 static inline struct brw_reg
947 brw_writemask(struct brw_reg reg
, unsigned mask
)
949 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
950 reg
.writemask
&= mask
;
954 static inline struct brw_reg
955 brw_set_writemask(struct brw_reg reg
, unsigned mask
)
957 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
958 reg
.writemask
= mask
;
962 static inline unsigned
963 brw_writemask_for_size(unsigned n
)
968 static inline struct brw_reg
969 negate(struct brw_reg reg
)
975 static inline struct brw_reg
976 brw_abs(struct brw_reg reg
)
983 /************************************************************************/
985 static inline struct brw_reg
986 brw_vec4_indirect(unsigned subnr
, int offset
)
988 struct brw_reg reg
= brw_vec4_grf(0, 0);
990 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
991 reg
.indirect_offset
= offset
;
995 static inline struct brw_reg
996 brw_vec1_indirect(unsigned subnr
, int offset
)
998 struct brw_reg reg
= brw_vec1_grf(0, 0);
1000 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1001 reg
.indirect_offset
= offset
;
1005 static inline struct brw_reg
1006 brw_VxH_indirect(unsigned subnr
, int offset
)
1008 struct brw_reg reg
= brw_vec1_grf(0, 0);
1009 reg
.vstride
= BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL
;
1011 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1012 reg
.indirect_offset
= offset
;
1016 static inline struct brw_reg
1017 deref_4f(struct brw_indirect ptr
, int offset
)
1019 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1022 static inline struct brw_reg
1023 deref_1f(struct brw_indirect ptr
, int offset
)
1025 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1028 static inline struct brw_reg
1029 deref_4b(struct brw_indirect ptr
, int offset
)
1031 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
1034 static inline struct brw_reg
1035 deref_1uw(struct brw_indirect ptr
, int offset
)
1037 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
1040 static inline struct brw_reg
1041 deref_1d(struct brw_indirect ptr
, int offset
)
1043 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
1046 static inline struct brw_reg
1047 deref_1ud(struct brw_indirect ptr
, int offset
)
1049 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
1052 static inline struct brw_reg
1053 get_addr_reg(struct brw_indirect ptr
)
1055 return brw_address_reg(ptr
.addr_subnr
);
1058 static inline struct brw_indirect
1059 brw_indirect_offset(struct brw_indirect ptr
, int offset
)
1061 ptr
.addr_offset
+= offset
;
1065 static inline struct brw_indirect
1066 brw_indirect(unsigned addr_subnr
, int offset
)
1068 struct brw_indirect ptr
;
1069 ptr
.addr_subnr
= addr_subnr
;
1070 ptr
.addr_offset
= offset
;
1076 region_matches(struct brw_reg reg
, enum brw_vertical_stride v
,
1077 enum brw_width w
, enum brw_horizontal_stride h
)
1079 return reg
.vstride
== v
&&
1084 #define has_scalar_region(reg) \
1085 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
1086 BRW_HORIZONTAL_STRIDE_0)
1088 /* brw_packed_float.c */
1089 int brw_float_to_vf(float f
);
1090 float brw_vf_to_float(unsigned char vf
);