2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
31 #include "brw_shader.h"
32 #include "glsl/glsl_types.h"
33 #include "glsl/ir_optimization.h"
37 /** @file brw_fs_schedule_instructions.cpp
39 * List scheduling of FS instructions.
41 * The basic model of the list scheduler is to take a basic block,
42 * compute a DAG of the dependencies (RAW ordering with latency, WAW
43 * ordering with latency, WAR ordering), and make a list of the DAG heads.
44 * Heuristically pick a DAG head, then put all the children that are
45 * now DAG heads into the list of things to schedule.
47 * The heuristic is the important part. We're trying to be cheap,
48 * since actually computing the optimal scheduling is NP complete.
49 * What we do is track a "current clock". When we schedule a node, we
50 * update the earliest-unblocked clock time of its children, and
51 * increment the clock. Then, when trying to schedule, we just pick
52 * the earliest-unblocked instruction to schedule.
54 * Note that often there will be many things which could execute
55 * immediately, and there are a range of heuristic options to choose
56 * from in picking among those.
59 static bool debug
= false;
61 class instruction_scheduler
;
63 class schedule_node
: public exec_node
66 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
67 void set_latency_gen4();
68 void set_latency_gen7(bool is_haswell
);
70 backend_instruction
*inst
;
71 schedule_node
**children
;
80 * Which iteration of pushing groups of children onto the candidates list
81 * this node was a part of.
83 unsigned cand_generation
;
86 * This is the sum of the instruction's latency plus the maximum delay of
87 * its children, or just the issue_time if it's a leaf node.
93 schedule_node::set_latency_gen4()
96 int math_latency
= 22;
98 switch (inst
->opcode
) {
99 case SHADER_OPCODE_RCP
:
100 this->latency
= 1 * chans
* math_latency
;
102 case SHADER_OPCODE_RSQ
:
103 this->latency
= 2 * chans
* math_latency
;
105 case SHADER_OPCODE_INT_QUOTIENT
:
106 case SHADER_OPCODE_SQRT
:
107 case SHADER_OPCODE_LOG2
:
108 /* full precision log. partial is 2. */
109 this->latency
= 3 * chans
* math_latency
;
111 case SHADER_OPCODE_INT_REMAINDER
:
112 case SHADER_OPCODE_EXP2
:
113 /* full precision. partial is 3, same throughput. */
114 this->latency
= 4 * chans
* math_latency
;
116 case SHADER_OPCODE_POW
:
117 this->latency
= 8 * chans
* math_latency
;
119 case SHADER_OPCODE_SIN
:
120 case SHADER_OPCODE_COS
:
121 /* minimum latency, max is 12 rounds. */
122 this->latency
= 5 * chans
* math_latency
;
131 schedule_node::set_latency_gen7(bool is_haswell
)
133 switch (inst
->opcode
) {
136 * (since the last two src operands are in different register banks):
137 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
139 * 3 cycles on IVB, 4 on HSW
140 * (since the last two src operands are in the same register bank):
141 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
143 * 18 cycles on IVB, 16 on HSW
144 * (since the last two src operands are in different register banks):
145 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
146 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
148 * 20 cycles on IVB, 18 on HSW
149 * (since the last two src operands are in the same register bank):
150 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
151 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
154 /* Our register allocator doesn't know about register banks, so use the
157 latency
= is_haswell
? 16 : 18;
162 * (since the last two src operands are in different register banks):
163 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
165 * 3 cycles on IVB, 4 on HSW
166 * (since the last two src operands are in the same register bank):
167 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
169 * 16 cycles on IVB, 14 on HSW
170 * (since the last two src operands are in different register banks):
171 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
172 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
175 * (since the last two src operands are in the same register bank):
176 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
177 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
180 /* Our register allocator doesn't know about register banks, so use the
186 case SHADER_OPCODE_RCP
:
187 case SHADER_OPCODE_RSQ
:
188 case SHADER_OPCODE_SQRT
:
189 case SHADER_OPCODE_LOG2
:
190 case SHADER_OPCODE_EXP2
:
191 case SHADER_OPCODE_SIN
:
192 case SHADER_OPCODE_COS
:
194 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
197 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
198 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
200 * Same for exp2, log2, rsq, sqrt, sin, cos.
202 latency
= is_haswell
? 14 : 16;
205 case SHADER_OPCODE_POW
:
207 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
210 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
211 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
213 latency
= is_haswell
? 22 : 24;
216 case SHADER_OPCODE_TEX
:
217 case SHADER_OPCODE_TXD
:
218 case SHADER_OPCODE_TXF
:
219 case SHADER_OPCODE_TXL
:
221 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
222 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
223 * send(8) g4<1>UW g114<8,8,1>F
224 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
226 * 697 +/-49 cycles (min 610, n=26):
227 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
228 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
229 * send(8) g4<1>UW g114<8,8,1>F
230 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
231 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
233 * So the latency on our first texture load of the batchbuffer takes
234 * ~700 cycles, since the caches are cold at that point.
236 * 840 +/- 92 cycles (min 720, n=25):
237 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
238 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
239 * send(8) g4<1>UW g114<8,8,1>F
240 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
241 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
242 * send(8) g4<1>UW g114<8,8,1>F
243 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
244 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
246 * On the second load, it takes just an extra ~140 cycles, and after
247 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
249 * 683 +/- 49 cycles (min = 602, n=47):
250 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
251 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
252 * send(8) g4<1>UW g114<8,8,1>F
253 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
254 * send(8) g50<1>UW g114<8,8,1>F
255 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
256 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
258 * The unit appears to be pipelined, since this matches up with the
259 * cache-cold case, despite there being two loads here. If you replace
260 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
262 * So, take some number between the cache-hot 140 cycles and the
263 * cache-cold 700 cycles. No particular tuning was done on this.
265 * I haven't done significant testing of the non-TEX opcodes. TXL at
266 * least looked about the same as TEX.
271 case SHADER_OPCODE_TXS
:
272 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
274 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
275 * send(8) g6<1>UW g114<8,8,1>F
276 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
277 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
280 * Two loads was 535 +/- 30 cycles (n=19):
281 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
282 * send(16) g6<1>UW g114<8,8,1>F
283 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
284 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
285 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
286 * send(16) g8<1>UW g114<8,8,1>F
287 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
288 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
289 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
291 * Since the only caches that should matter are just the
292 * instruction/state cache containing the surface state, assume that we
293 * always have hot caches.
298 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
299 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
300 case VS_OPCODE_PULL_CONSTANT_LOAD
:
301 /* testing using varying-index pull constants:
304 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
305 * send(8) g4<1>F g4<8,8,1>D
306 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
309 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
310 * send(8) g4<1>F g4<8,8,1>D
311 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
312 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
315 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
316 * send(8) g4<1>F g4<8,8,1>D
317 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
318 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
319 * send(8) g4<1>F g4<8,8,1>D
320 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
321 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
323 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
324 * about 460. We expect to mostly be cache hot, so pick something more
330 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
331 /* Testing a load from offset 0, that had been previously written:
333 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
334 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
336 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
337 * then around 140. Presumably this is cache hit vs miss.
342 case SHADER_OPCODE_UNTYPED_ATOMIC
:
344 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
345 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
346 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
347 * send(8) g4<1>ud g112<8,8,1>ud
348 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
350 * Running it 100 times as fragment shader on a 128x128 quad
351 * gives an average latency of 13867 cycles per atomic op,
352 * standard deviation 3%. Note that this is a rather
353 * pessimistic estimate, the actual latency in cases with few
354 * collisions between threads and favorable pipelining has been
355 * seen to be reduced by a factor of 100.
360 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
362 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
363 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
364 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
365 * send(8) g4<1>UD g112<8,8,1>UD
366 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
368 * . [repeats 8 times]
370 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
371 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
372 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
373 * send(8) g4<1>UD g112<8,8,1>UD
374 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
376 * Running it 100 times as fragment shader on a 128x128 quad
377 * gives an average latency of 583 cycles per surface read,
378 * standard deviation 0.9%.
380 latency
= is_haswell
? 300 : 600;
385 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
388 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
389 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
396 class instruction_scheduler
{
398 instruction_scheduler(backend_visitor
*v
, int grf_count
,
399 instruction_scheduler_mode mode
)
402 this->mem_ctx
= ralloc_context(NULL
);
403 this->grf_count
= grf_count
;
404 this->instructions
.make_empty();
405 this->instructions_to_schedule
= 0;
406 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
409 if (!post_reg_alloc
) {
410 this->remaining_grf_uses
= rzalloc_array(mem_ctx
, int, grf_count
);
411 this->grf_active
= rzalloc_array(mem_ctx
, bool, grf_count
);
413 this->remaining_grf_uses
= NULL
;
414 this->grf_active
= NULL
;
418 ~instruction_scheduler()
420 ralloc_free(this->mem_ctx
);
422 void add_barrier_deps(schedule_node
*n
);
423 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
424 void add_dep(schedule_node
*before
, schedule_node
*after
);
426 void run(cfg_t
*cfg
);
427 void add_insts_from_block(bblock_t
*block
);
428 void compute_delay(schedule_node
*node
);
429 virtual void calculate_deps() = 0;
430 virtual schedule_node
*choose_instruction_to_schedule() = 0;
433 * Returns how many cycles it takes the instruction to issue.
435 * Instructions in gen hardware are handled one simd4 vector at a time,
436 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
437 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
439 virtual int issue_time(backend_instruction
*inst
) = 0;
441 virtual void count_remaining_grf_uses(backend_instruction
*inst
) = 0;
442 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
443 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
445 void schedule_instructions(bblock_t
*block
);
450 int instructions_to_schedule
;
453 exec_list instructions
;
456 instruction_scheduler_mode mode
;
459 * Number of instructions left to schedule that reference each vgrf.
461 * Used so that we can prefer scheduling instructions that will end the
462 * live intervals of multiple variables, to reduce register pressure.
464 int *remaining_grf_uses
;
467 * Tracks whether each VGRF has had an instruction scheduled that uses it.
469 * This is used to estimate whether scheduling a new instruction will
470 * increase register pressure.
475 class fs_instruction_scheduler
: public instruction_scheduler
478 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
,
479 instruction_scheduler_mode mode
);
480 void calculate_deps();
481 bool is_compressed(fs_inst
*inst
);
482 schedule_node
*choose_instruction_to_schedule();
483 int issue_time(backend_instruction
*inst
);
486 void count_remaining_grf_uses(backend_instruction
*inst
);
487 void update_register_pressure(backend_instruction
*inst
);
488 int get_register_pressure_benefit(backend_instruction
*inst
);
491 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
493 instruction_scheduler_mode mode
)
494 : instruction_scheduler(v
, grf_count
, mode
),
500 fs_instruction_scheduler::count_remaining_grf_uses(backend_instruction
*be
)
502 fs_inst
*inst
= (fs_inst
*)be
;
504 if (!remaining_grf_uses
)
507 if (inst
->dst
.file
== GRF
)
508 remaining_grf_uses
[inst
->dst
.reg
]++;
510 for (int i
= 0; i
< inst
->sources
; i
++) {
511 if (inst
->src
[i
].file
!= GRF
)
514 remaining_grf_uses
[inst
->src
[i
].reg
]++;
519 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
521 fs_inst
*inst
= (fs_inst
*)be
;
523 if (!remaining_grf_uses
)
526 if (inst
->dst
.file
== GRF
) {
527 remaining_grf_uses
[inst
->dst
.reg
]--;
528 grf_active
[inst
->dst
.reg
] = true;
531 for (int i
= 0; i
< inst
->sources
; i
++) {
532 if (inst
->src
[i
].file
== GRF
) {
533 remaining_grf_uses
[inst
->src
[i
].reg
]--;
534 grf_active
[inst
->src
[i
].reg
] = true;
540 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
542 fs_inst
*inst
= (fs_inst
*)be
;
545 if (inst
->dst
.file
== GRF
) {
546 if (remaining_grf_uses
[inst
->dst
.reg
] == 1)
547 benefit
+= v
->virtual_grf_sizes
[inst
->dst
.reg
];
548 if (!grf_active
[inst
->dst
.reg
])
549 benefit
-= v
->virtual_grf_sizes
[inst
->dst
.reg
];
552 for (int i
= 0; i
< inst
->sources
; i
++) {
553 if (inst
->src
[i
].file
!= GRF
)
556 if (remaining_grf_uses
[inst
->src
[i
].reg
] == 1)
557 benefit
+= v
->virtual_grf_sizes
[inst
->src
[i
].reg
];
558 if (!grf_active
[inst
->src
[i
].reg
])
559 benefit
-= v
->virtual_grf_sizes
[inst
->src
[i
].reg
];
565 class vec4_instruction_scheduler
: public instruction_scheduler
568 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
569 void calculate_deps();
570 schedule_node
*choose_instruction_to_schedule();
571 int issue_time(backend_instruction
*inst
);
574 void count_remaining_grf_uses(backend_instruction
*inst
);
575 void update_register_pressure(backend_instruction
*inst
);
576 int get_register_pressure_benefit(backend_instruction
*inst
);
579 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
581 : instruction_scheduler(v
, grf_count
, SCHEDULE_POST
),
587 vec4_instruction_scheduler::count_remaining_grf_uses(backend_instruction
*be
)
592 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
597 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
602 schedule_node::schedule_node(backend_instruction
*inst
,
603 instruction_scheduler
*sched
)
605 struct brw_context
*brw
= sched
->bv
->brw
;
608 this->child_array_size
= 0;
609 this->children
= NULL
;
610 this->child_latency
= NULL
;
611 this->child_count
= 0;
612 this->parent_count
= 0;
613 this->unblocked_time
= 0;
614 this->cand_generation
= 0;
617 /* We can't measure Gen6 timings directly but expect them to be much
618 * closer to Gen7 than Gen4.
620 if (!sched
->post_reg_alloc
)
622 else if (brw
->gen
>= 6)
623 set_latency_gen7(brw
->is_haswell
);
629 instruction_scheduler::add_insts_from_block(bblock_t
*block
)
631 /* Removing the last instruction from a basic block removes the block as
632 * well, so put a NOP at the end to keep it alive.
634 if (!block
->end()->is_control_flow()) {
635 backend_instruction
*nop
= new(mem_ctx
) backend_instruction();
636 nop
->opcode
= BRW_OPCODE_NOP
;
637 block
->end()->insert_after(block
, nop
);
640 foreach_inst_in_block_safe(backend_instruction
, inst
, block
) {
641 if (inst
->opcode
== BRW_OPCODE_NOP
|| inst
->is_control_flow())
644 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
646 this->instructions_to_schedule
++;
649 instructions
.push_tail(n
);
653 /** Recursive computation of the delay member of a node. */
655 instruction_scheduler::compute_delay(schedule_node
*n
)
657 if (!n
->child_count
) {
658 n
->delay
= issue_time(n
->inst
);
660 for (int i
= 0; i
< n
->child_count
; i
++) {
661 if (!n
->children
[i
]->delay
)
662 compute_delay(n
->children
[i
]);
663 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
669 * Add a dependency between two instruction nodes.
671 * The @after node will be scheduled after @before. We will try to
672 * schedule it @latency cycles after @before, but no guarantees there.
675 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
678 if (!before
|| !after
)
681 assert(before
!= after
);
683 for (int i
= 0; i
< before
->child_count
; i
++) {
684 if (before
->children
[i
] == after
) {
685 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
690 if (before
->child_array_size
<= before
->child_count
) {
691 if (before
->child_array_size
< 16)
692 before
->child_array_size
= 16;
694 before
->child_array_size
*= 2;
696 before
->children
= reralloc(mem_ctx
, before
->children
,
698 before
->child_array_size
);
699 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
700 int, before
->child_array_size
);
703 before
->children
[before
->child_count
] = after
;
704 before
->child_latency
[before
->child_count
] = latency
;
705 before
->child_count
++;
706 after
->parent_count
++;
710 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
715 add_dep(before
, after
, before
->latency
);
719 * Sometimes we really want this node to execute after everything that
720 * was before it and before everything that followed it. This adds
724 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
726 schedule_node
*prev
= (schedule_node
*)n
->prev
;
727 schedule_node
*next
= (schedule_node
*)n
->next
;
730 while (!prev
->is_head_sentinel()) {
732 prev
= (schedule_node
*)prev
->prev
;
737 while (!next
->is_tail_sentinel()) {
739 next
= (schedule_node
*)next
->next
;
744 /* instruction scheduling needs to be aware of when an MRF write
745 * actually writes 2 MRFs.
748 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
750 return inst
->exec_size
== 16;
754 fs_instruction_scheduler::calculate_deps()
756 /* Pre-register-allocation, this tracks the last write per VGRF offset.
757 * After register allocation, reg_offsets are gone and we track individual
760 schedule_node
*last_grf_write
[grf_count
* 16];
761 schedule_node
*last_mrf_write
[BRW_MAX_MRF
];
762 schedule_node
*last_conditional_mod
[2] = { NULL
, NULL
};
763 schedule_node
*last_accumulator_write
= NULL
;
764 /* Fixed HW registers are assumed to be separate from the virtual
765 * GRFs, so they can be tracked separately. We don't really write
766 * to fixed GRFs much, so don't bother tracking them on a more
769 schedule_node
*last_fixed_grf_write
= NULL
;
770 int reg_width
= v
->dispatch_width
/ 8;
772 /* The last instruction always needs to still be the last
773 * instruction. Either it's flow control (IF, ELSE, ENDIF, DO,
774 * WHILE) and scheduling other things after it would disturb the
775 * basic block, or it's FB_WRITE and we should do a better job at
776 * dead code elimination anyway.
778 schedule_node
*last
= (schedule_node
*)instructions
.get_tail();
779 add_barrier_deps(last
);
781 memset(last_grf_write
, 0, sizeof(last_grf_write
));
782 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
784 /* top-to-bottom dependencies: RAW and WAW. */
785 foreach_in_list(schedule_node
, n
, &instructions
) {
786 fs_inst
*inst
= (fs_inst
*)n
->inst
;
788 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
789 inst
->has_side_effects())
792 /* read-after-write deps. */
793 for (int i
= 0; i
< inst
->sources
; i
++) {
794 if (inst
->src
[i
].file
== GRF
) {
795 if (post_reg_alloc
) {
796 for (int r
= 0; r
< inst
->regs_read(v
, i
); r
++)
797 add_dep(last_grf_write
[inst
->src
[i
].reg
+ r
], n
);
799 for (int r
= 0; r
< inst
->regs_read(v
, i
); r
++) {
800 add_dep(last_grf_write
[inst
->src
[i
].reg
* 16 + inst
->src
[i
].reg_offset
+ r
], n
);
803 } else if (inst
->src
[i
].file
== HW_REG
&&
804 (inst
->src
[i
].fixed_hw_reg
.file
==
805 BRW_GENERAL_REGISTER_FILE
)) {
806 if (post_reg_alloc
) {
807 int size
= reg_width
;
808 if (inst
->src
[i
].fixed_hw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
)
810 for (int r
= 0; r
< size
; r
++)
811 add_dep(last_grf_write
[inst
->src
[i
].fixed_hw_reg
.nr
+ r
], n
);
813 add_dep(last_fixed_grf_write
, n
);
815 } else if (inst
->src
[i
].is_accumulator()) {
816 add_dep(last_accumulator_write
, n
);
817 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
818 inst
->src
[i
].file
!= IMM
&&
819 inst
->src
[i
].file
!= UNIFORM
&&
820 (inst
->src
[i
].file
!= HW_REG
||
821 inst
->src
[i
].fixed_hw_reg
.file
!= IMM
)) {
822 assert(inst
->src
[i
].file
!= MRF
);
827 if (inst
->base_mrf
!= -1) {
828 for (int i
= 0; i
< inst
->mlen
; i
++) {
829 /* It looks like the MRF regs are released in the send
830 * instruction once it's sent, not when the result comes
833 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
837 if (inst
->reads_flag()) {
838 add_dep(last_conditional_mod
[inst
->flag_subreg
], n
);
841 if (inst
->reads_accumulator_implicitly()) {
842 add_dep(last_accumulator_write
, n
);
845 /* write-after-write deps. */
846 if (inst
->dst
.file
== GRF
) {
847 if (post_reg_alloc
) {
848 for (int r
= 0; r
< inst
->regs_written
; r
++) {
849 add_dep(last_grf_write
[inst
->dst
.reg
+ r
], n
);
850 last_grf_write
[inst
->dst
.reg
+ r
] = n
;
853 for (int r
= 0; r
< inst
->regs_written
; r
++) {
854 add_dep(last_grf_write
[inst
->dst
.reg
* 16 + inst
->dst
.reg_offset
+ r
], n
);
855 last_grf_write
[inst
->dst
.reg
* 16 + inst
->dst
.reg_offset
+ r
] = n
;
858 } else if (inst
->dst
.file
== MRF
) {
859 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
861 add_dep(last_mrf_write
[reg
], n
);
862 last_mrf_write
[reg
] = n
;
863 if (is_compressed(inst
)) {
864 if (inst
->dst
.reg
& BRW_MRF_COMPR4
)
868 add_dep(last_mrf_write
[reg
], n
);
869 last_mrf_write
[reg
] = n
;
871 } else if (inst
->dst
.file
== HW_REG
&&
872 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
873 if (post_reg_alloc
) {
874 for (int r
= 0; r
< reg_width
; r
++)
875 last_grf_write
[inst
->dst
.fixed_hw_reg
.nr
+ r
] = n
;
877 last_fixed_grf_write
= n
;
879 } else if (inst
->dst
.is_accumulator()) {
880 add_dep(last_accumulator_write
, n
);
881 last_accumulator_write
= n
;
882 } else if (inst
->dst
.file
!= BAD_FILE
) {
886 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
887 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
888 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
889 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
893 if (inst
->writes_flag()) {
894 add_dep(last_conditional_mod
[inst
->flag_subreg
], n
, 0);
895 last_conditional_mod
[inst
->flag_subreg
] = n
;
898 if (inst
->writes_accumulator_implicitly(v
->brw
) &&
899 !inst
->dst
.is_accumulator()) {
900 add_dep(last_accumulator_write
, n
);
901 last_accumulator_write
= n
;
905 /* bottom-to-top dependencies: WAR */
906 memset(last_grf_write
, 0, sizeof(last_grf_write
));
907 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
908 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
909 last_accumulator_write
= NULL
;
910 last_fixed_grf_write
= NULL
;
914 for (node
= instructions
.get_tail(), prev
= node
->prev
;
915 !node
->is_head_sentinel();
916 node
= prev
, prev
= node
->prev
) {
917 schedule_node
*n
= (schedule_node
*)node
;
918 fs_inst
*inst
= (fs_inst
*)n
->inst
;
920 /* write-after-read deps. */
921 for (int i
= 0; i
< inst
->sources
; i
++) {
922 if (inst
->src
[i
].file
== GRF
) {
923 if (post_reg_alloc
) {
924 for (int r
= 0; r
< inst
->regs_read(v
, i
); r
++)
925 add_dep(n
, last_grf_write
[inst
->src
[i
].reg
+ r
]);
927 for (int r
= 0; r
< inst
->regs_read(v
, i
); r
++) {
928 add_dep(n
, last_grf_write
[inst
->src
[i
].reg
* 16 + inst
->src
[i
].reg_offset
+ r
]);
931 } else if (inst
->src
[i
].file
== HW_REG
&&
932 (inst
->src
[i
].fixed_hw_reg
.file
==
933 BRW_GENERAL_REGISTER_FILE
)) {
934 if (post_reg_alloc
) {
935 int size
= reg_width
;
936 if (inst
->src
[i
].fixed_hw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
)
938 for (int r
= 0; r
< size
; r
++)
939 add_dep(n
, last_grf_write
[inst
->src
[i
].fixed_hw_reg
.nr
+ r
]);
941 add_dep(n
, last_fixed_grf_write
);
943 } else if (inst
->src
[i
].is_accumulator()) {
944 add_dep(n
, last_accumulator_write
);
945 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
946 inst
->src
[i
].file
!= IMM
&&
947 inst
->src
[i
].file
!= UNIFORM
&&
948 (inst
->src
[i
].file
!= HW_REG
||
949 inst
->src
[i
].fixed_hw_reg
.file
!= IMM
)) {
950 assert(inst
->src
[i
].file
!= MRF
);
955 if (inst
->base_mrf
!= -1) {
956 for (int i
= 0; i
< inst
->mlen
; i
++) {
957 /* It looks like the MRF regs are released in the send
958 * instruction once it's sent, not when the result comes
961 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
965 if (inst
->reads_flag()) {
966 add_dep(n
, last_conditional_mod
[inst
->flag_subreg
]);
969 if (inst
->reads_accumulator_implicitly()) {
970 add_dep(n
, last_accumulator_write
);
973 /* Update the things this instruction wrote, so earlier reads
974 * can mark this as WAR dependency.
976 if (inst
->dst
.file
== GRF
) {
977 if (post_reg_alloc
) {
978 for (int r
= 0; r
< inst
->regs_written
; r
++)
979 last_grf_write
[inst
->dst
.reg
+ r
] = n
;
981 for (int r
= 0; r
< inst
->regs_written
; r
++) {
982 last_grf_write
[inst
->dst
.reg
* 16 + inst
->dst
.reg_offset
+ r
] = n
;
985 } else if (inst
->dst
.file
== MRF
) {
986 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
988 last_mrf_write
[reg
] = n
;
990 if (is_compressed(inst
)) {
991 if (inst
->dst
.reg
& BRW_MRF_COMPR4
)
996 last_mrf_write
[reg
] = n
;
998 } else if (inst
->dst
.file
== HW_REG
&&
999 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
1000 if (post_reg_alloc
) {
1001 for (int r
= 0; r
< reg_width
; r
++)
1002 last_grf_write
[inst
->dst
.fixed_hw_reg
.nr
+ r
] = n
;
1004 last_fixed_grf_write
= n
;
1006 } else if (inst
->dst
.is_accumulator()) {
1007 last_accumulator_write
= n
;
1008 } else if (inst
->dst
.file
!= BAD_FILE
) {
1009 add_barrier_deps(n
);
1012 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1013 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1014 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1018 if (inst
->writes_flag()) {
1019 last_conditional_mod
[inst
->flag_subreg
] = n
;
1022 if (inst
->writes_accumulator_implicitly(v
->brw
)) {
1023 last_accumulator_write
= n
;
1029 vec4_instruction_scheduler::calculate_deps()
1031 schedule_node
*last_grf_write
[grf_count
];
1032 schedule_node
*last_mrf_write
[BRW_MAX_MRF
];
1033 schedule_node
*last_conditional_mod
= NULL
;
1034 schedule_node
*last_accumulator_write
= NULL
;
1035 /* Fixed HW registers are assumed to be separate from the virtual
1036 * GRFs, so they can be tracked separately. We don't really write
1037 * to fixed GRFs much, so don't bother tracking them on a more
1040 schedule_node
*last_fixed_grf_write
= NULL
;
1042 /* The last instruction always needs to still be the last instruction.
1043 * Either it's flow control (IF, ELSE, ENDIF, DO, WHILE) and scheduling
1044 * other things after it would disturb the basic block, or it's the EOT
1045 * URB_WRITE and we should do a better job at dead code eliminating
1046 * anything that could have been scheduled after it.
1048 schedule_node
*last
= (schedule_node
*)instructions
.get_tail();
1049 add_barrier_deps(last
);
1051 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1052 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1054 /* top-to-bottom dependencies: RAW and WAW. */
1055 foreach_in_list(schedule_node
, n
, &instructions
) {
1056 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1058 if (inst
->has_side_effects())
1059 add_barrier_deps(n
);
1061 /* read-after-write deps. */
1062 for (int i
= 0; i
< 3; i
++) {
1063 if (inst
->src
[i
].file
== GRF
) {
1064 add_dep(last_grf_write
[inst
->src
[i
].reg
], n
);
1065 } else if (inst
->src
[i
].file
== HW_REG
&&
1066 (inst
->src
[i
].fixed_hw_reg
.file
==
1067 BRW_GENERAL_REGISTER_FILE
)) {
1068 add_dep(last_fixed_grf_write
, n
);
1069 } else if (inst
->src
[i
].is_accumulator()) {
1070 assert(last_accumulator_write
);
1071 add_dep(last_accumulator_write
, n
);
1072 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
1073 inst
->src
[i
].file
!= IMM
&&
1074 inst
->src
[i
].file
!= UNIFORM
&&
1075 (inst
->src
[i
].file
!= HW_REG
||
1076 inst
->src
[i
].fixed_hw_reg
.file
!= IMM
)) {
1077 /* No reads from MRF, and ATTR is already translated away */
1078 assert(inst
->src
[i
].file
!= MRF
&&
1079 inst
->src
[i
].file
!= ATTR
);
1080 add_barrier_deps(n
);
1084 for (int i
= 0; i
< inst
->mlen
; i
++) {
1085 /* It looks like the MRF regs are released in the send
1086 * instruction once it's sent, not when the result comes
1089 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1092 if (inst
->reads_flag()) {
1093 assert(last_conditional_mod
);
1094 add_dep(last_conditional_mod
, n
);
1097 if (inst
->reads_accumulator_implicitly()) {
1098 assert(last_accumulator_write
);
1099 add_dep(last_accumulator_write
, n
);
1102 /* write-after-write deps. */
1103 if (inst
->dst
.file
== GRF
) {
1104 add_dep(last_grf_write
[inst
->dst
.reg
], n
);
1105 last_grf_write
[inst
->dst
.reg
] = n
;
1106 } else if (inst
->dst
.file
== MRF
) {
1107 add_dep(last_mrf_write
[inst
->dst
.reg
], n
);
1108 last_mrf_write
[inst
->dst
.reg
] = n
;
1109 } else if (inst
->dst
.file
== HW_REG
&&
1110 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
1111 last_fixed_grf_write
= n
;
1112 } else if (inst
->dst
.is_accumulator()) {
1113 add_dep(last_accumulator_write
, n
);
1114 last_accumulator_write
= n
;
1115 } else if (inst
->dst
.file
!= BAD_FILE
) {
1116 add_barrier_deps(n
);
1119 if (inst
->mlen
> 0) {
1120 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1121 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1122 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1126 if (inst
->writes_flag()) {
1127 add_dep(last_conditional_mod
, n
, 0);
1128 last_conditional_mod
= n
;
1131 if (inst
->writes_accumulator_implicitly(v
->brw
) &&
1132 !inst
->dst
.is_accumulator()) {
1133 add_dep(last_accumulator_write
, n
);
1134 last_accumulator_write
= n
;
1138 /* bottom-to-top dependencies: WAR */
1139 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1140 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1141 last_conditional_mod
= NULL
;
1142 last_accumulator_write
= NULL
;
1143 last_fixed_grf_write
= NULL
;
1147 for (node
= instructions
.get_tail(), prev
= node
->prev
;
1148 !node
->is_head_sentinel();
1149 node
= prev
, prev
= node
->prev
) {
1150 schedule_node
*n
= (schedule_node
*)node
;
1151 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1153 /* write-after-read deps. */
1154 for (int i
= 0; i
< 3; i
++) {
1155 if (inst
->src
[i
].file
== GRF
) {
1156 add_dep(n
, last_grf_write
[inst
->src
[i
].reg
]);
1157 } else if (inst
->src
[i
].file
== HW_REG
&&
1158 (inst
->src
[i
].fixed_hw_reg
.file
==
1159 BRW_GENERAL_REGISTER_FILE
)) {
1160 add_dep(n
, last_fixed_grf_write
);
1161 } else if (inst
->src
[i
].is_accumulator()) {
1162 add_dep(n
, last_accumulator_write
);
1163 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
1164 inst
->src
[i
].file
!= IMM
&&
1165 inst
->src
[i
].file
!= UNIFORM
&&
1166 (inst
->src
[i
].file
!= HW_REG
||
1167 inst
->src
[i
].fixed_hw_reg
.file
!= IMM
)) {
1168 assert(inst
->src
[i
].file
!= MRF
&&
1169 inst
->src
[i
].file
!= ATTR
);
1170 add_barrier_deps(n
);
1174 for (int i
= 0; i
< inst
->mlen
; i
++) {
1175 /* It looks like the MRF regs are released in the send
1176 * instruction once it's sent, not when the result comes
1179 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1182 if (inst
->reads_flag()) {
1183 add_dep(n
, last_conditional_mod
);
1186 if (inst
->reads_accumulator_implicitly()) {
1187 add_dep(n
, last_accumulator_write
);
1190 /* Update the things this instruction wrote, so earlier reads
1191 * can mark this as WAR dependency.
1193 if (inst
->dst
.file
== GRF
) {
1194 last_grf_write
[inst
->dst
.reg
] = n
;
1195 } else if (inst
->dst
.file
== MRF
) {
1196 last_mrf_write
[inst
->dst
.reg
] = n
;
1197 } else if (inst
->dst
.file
== HW_REG
&&
1198 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
1199 last_fixed_grf_write
= n
;
1200 } else if (inst
->dst
.is_accumulator()) {
1201 last_accumulator_write
= n
;
1202 } else if (inst
->dst
.file
!= BAD_FILE
) {
1203 add_barrier_deps(n
);
1206 if (inst
->mlen
> 0) {
1207 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1208 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1212 if (inst
->writes_flag()) {
1213 last_conditional_mod
= n
;
1216 if (inst
->writes_accumulator_implicitly(v
->brw
)) {
1217 last_accumulator_write
= n
;
1223 fs_instruction_scheduler::choose_instruction_to_schedule()
1225 struct brw_context
*brw
= v
->brw
;
1226 schedule_node
*chosen
= NULL
;
1228 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1229 int chosen_time
= 0;
1231 /* Of the instructions ready to execute or the closest to
1232 * being ready, choose the oldest one.
1234 foreach_in_list(schedule_node
, n
, &instructions
) {
1235 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1237 chosen_time
= n
->unblocked_time
;
1241 /* Before register allocation, we don't care about the latencies of
1242 * instructions. All we care about is reducing live intervals of
1243 * variables so that we can avoid register spilling, or get SIMD16
1244 * shaders which naturally do a better job of hiding instruction
1247 foreach_in_list(schedule_node
, n
, &instructions
) {
1248 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1255 /* Most important: If we can definitely reduce register pressure, do
1258 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1259 int chosen_register_pressure_benefit
=
1260 get_register_pressure_benefit(chosen
->inst
);
1262 if (register_pressure_benefit
> 0 &&
1263 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1266 } else if (chosen_register_pressure_benefit
> 0 &&
1267 (register_pressure_benefit
<
1268 chosen_register_pressure_benefit
)) {
1272 if (mode
== SCHEDULE_PRE_LIFO
) {
1273 /* Prefer instructions that recently became available for
1274 * scheduling. These are the things that are most likely to
1275 * (eventually) make a variable dead and reduce register pressure.
1276 * Typical register pressure estimates don't work for us because
1277 * most of our pressure comes from texturing, where no single
1278 * instruction to schedule will make a vec4 value dead.
1280 if (n
->cand_generation
> chosen
->cand_generation
) {
1283 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1287 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1288 * do this, then because we prefer instructions that just became
1289 * candidates, we'll end up in a pattern of scheduling a SEND,
1290 * then the MRFs for the next SEND, then the next SEND, then the
1291 * MRFs, etc., without ever consuming the results of a send.
1294 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1296 /* We use regs_written > 1 as our test for the kind of send
1297 * instruction to avoid -- only sends generate many regs, and a
1298 * single-result send is probably actually reducing register
1301 if (inst
->regs_written
<= inst
->dst
.width
/ 8 &&
1302 chosen_inst
->regs_written
> chosen_inst
->dst
.width
/ 8) {
1305 } else if (inst
->regs_written
> chosen_inst
->regs_written
) {
1311 /* For instructions pushed on the cands list at the same time, prefer
1312 * the one with the highest delay to the end of the program. This is
1313 * most likely to have its values able to be consumed first (such as
1314 * for a large tree of lowered ubo loads, which appear reversed in
1315 * the instruction stream with respect to when they can be consumed).
1317 if (n
->delay
> chosen
->delay
) {
1320 } else if (n
->delay
< chosen
->delay
) {
1324 /* If all other metrics are equal, we prefer the first instruction in
1325 * the list (program execution).
1334 vec4_instruction_scheduler::choose_instruction_to_schedule()
1336 schedule_node
*chosen
= NULL
;
1337 int chosen_time
= 0;
1339 /* Of the instructions ready to execute or the closest to being ready,
1340 * choose the oldest one.
1342 foreach_in_list(schedule_node
, n
, &instructions
) {
1343 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1345 chosen_time
= n
->unblocked_time
;
1353 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1355 if (is_compressed((fs_inst
*)inst
))
1362 vec4_instruction_scheduler::issue_time(backend_instruction
*inst
)
1364 /* We always execute as two vec4s in parallel. */
1369 instruction_scheduler::schedule_instructions(bblock_t
*block
)
1371 struct brw_context
*brw
= bv
->brw
;
1372 backend_instruction
*inst
= block
->end();
1375 /* Remove non-DAG heads from the list. */
1376 foreach_in_list_safe(schedule_node
, n
, &instructions
) {
1377 if (n
->parent_count
!= 0)
1381 unsigned cand_generation
= 1;
1382 while (!instructions
.is_empty()) {
1383 schedule_node
*chosen
= choose_instruction_to_schedule();
1385 /* Schedule this instruction. */
1388 inst
->insert_before(block
, chosen
->inst
);
1389 instructions_to_schedule
--;
1390 update_register_pressure(chosen
->inst
);
1392 /* Update the clock for how soon an instruction could start after the
1395 time
+= issue_time(chosen
->inst
);
1397 /* If we expected a delay for scheduling, then bump the clock to reflect
1398 * that as well. In reality, the hardware will switch to another
1399 * hyperthread and may not return to dispatching our thread for a while
1400 * even after we're unblocked.
1402 time
= MAX2(time
, chosen
->unblocked_time
);
1405 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1406 bv
->dump_instruction(chosen
->inst
);
1409 /* Now that we've scheduled a new instruction, some of its
1410 * children can be promoted to the list of instructions ready to
1411 * be scheduled. Update the children's unblocked time for this
1412 * DAG edge as we do so.
1414 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1415 schedule_node
*child
= chosen
->children
[i
];
1417 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1418 time
+ chosen
->child_latency
[i
]);
1421 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1422 bv
->dump_instruction(child
->inst
);
1425 child
->cand_generation
= cand_generation
;
1426 child
->parent_count
--;
1427 if (child
->parent_count
== 0) {
1429 fprintf(stderr
, "\t\tnow available\n");
1431 instructions
.push_head(child
);
1436 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1437 * but it's more limited pre-gen6, so if we send something off to it then
1438 * the next math instruction isn't going to make progress until the first
1441 if (brw
->gen
< 6 && chosen
->inst
->is_math()) {
1442 foreach_in_list(schedule_node
, n
, &instructions
) {
1443 if (n
->inst
->is_math())
1444 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1445 time
+ chosen
->latency
);
1450 if (block
->end()->opcode
== BRW_OPCODE_NOP
)
1451 block
->end()->remove(block
);
1452 assert(instructions_to_schedule
== 0);
1456 instruction_scheduler::run(cfg_t
*cfg
)
1459 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1461 bv
->dump_instructions();
1464 /* Populate the remaining GRF uses array to improve the pre-regalloc
1467 if (remaining_grf_uses
) {
1468 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1469 count_remaining_grf_uses(inst
);
1473 foreach_block(block
, cfg
) {
1474 if (block
->end_ip
- block
->start_ip
<= 1)
1477 add_insts_from_block(block
);
1481 foreach_in_list(schedule_node
, n
, &instructions
) {
1485 schedule_instructions(block
);
1489 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1491 bv
->dump_instructions();
1496 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1499 if (mode
== SCHEDULE_POST
)
1500 grf_count
= grf_used
;
1502 grf_count
= virtual_grf_count
;
1504 fs_instruction_scheduler
sched(this, grf_count
, mode
);
1507 if (unlikely(INTEL_DEBUG
& DEBUG_WM
) && mode
== SCHEDULE_POST
) {
1508 fprintf(stderr
, "fs%d estimated execution time: %d cycles\n",
1509 dispatch_width
, sched
.time
);
1512 invalidate_live_intervals();
1516 vec4_visitor::opt_schedule_instructions()
1518 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1521 if (unlikely(debug_flag
)) {
1522 fprintf(stderr
, "vec4 estimated execution time: %d cycles\n", sched
.time
);
1525 invalidate_live_intervals();