1b79cc0022b318c304d893b56ae16fb4277039cc
[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33
34 #include "main/mtypes.h"
35 #include "main/macros.h"
36 #include "main/fbobject.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
39 #include "brw_defines.h"
40 #include "brw_sf.h"
41
42 static void upload_sf_vp(struct brw_context *brw)
43 {
44 struct gl_context *ctx = &brw->ctx;
45 const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
46 struct brw_sf_viewport *sfv;
47 GLfloat y_scale, y_bias;
48 const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
49 const GLfloat *v = ctx->ViewportArray[0]._WindowMap.m;
50
51 sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
52 sizeof(*sfv), 32, &brw->sf.vp_offset);
53 memset(sfv, 0, sizeof(*sfv));
54
55 if (render_to_fbo) {
56 y_scale = 1.0;
57 y_bias = 0;
58 }
59 else {
60 y_scale = -1.0;
61 y_bias = ctx->DrawBuffer->Height;
62 }
63
64 /* _NEW_VIEWPORT */
65
66 sfv->viewport.m00 = v[MAT_SX];
67 sfv->viewport.m11 = v[MAT_SY] * y_scale;
68 sfv->viewport.m22 = v[MAT_SZ] * depth_scale;
69 sfv->viewport.m30 = v[MAT_TX];
70 sfv->viewport.m31 = v[MAT_TY] * y_scale + y_bias;
71 sfv->viewport.m32 = v[MAT_TZ] * depth_scale;
72
73 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
74 * for DrawBuffer->_[XY]{min,max}
75 */
76
77 /* The scissor only needs to handle the intersection of drawable
78 * and scissor rect, since there are no longer cliprects for shared
79 * buffers with DRI2.
80 *
81 * Note that the hardware's coordinates are inclusive, while Mesa's min is
82 * inclusive but max is exclusive.
83 */
84
85 if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
86 ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
87 /* If the scissor was out of bounds and got clamped to 0
88 * width/height at the bounds, the subtraction of 1 from
89 * maximums could produce a negative number and thus not clip
90 * anything. Instead, just provide a min > max scissor inside
91 * the bounds, which produces the expected no rendering.
92 */
93 sfv->scissor.xmin = 1;
94 sfv->scissor.xmax = 0;
95 sfv->scissor.ymin = 1;
96 sfv->scissor.ymax = 0;
97 } else if (render_to_fbo) {
98 /* texmemory: Y=0=bottom */
99 sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
100 sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
101 sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
102 sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
103 }
104 else {
105 /* memory: Y=0=top */
106 sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
107 sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
108 sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
109 sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
110 }
111
112 brw->state.dirty.brw |= BRW_NEW_SF_VP;
113 }
114
115 const struct brw_tracked_state brw_sf_vp = {
116 .dirty = {
117 .mesa = _NEW_BUFFERS |
118 _NEW_SCISSOR |
119 _NEW_VIEWPORT,
120 .brw = BRW_NEW_BATCH,
121 .cache = 0
122 },
123 .emit = upload_sf_vp
124 };
125
126 static void upload_sf_unit( struct brw_context *brw )
127 {
128 struct gl_context *ctx = &brw->ctx;
129 struct brw_sf_unit_state *sf;
130 drm_intel_bo *bo = brw->batch.bo;
131 int chipset_max_threads;
132 bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
133
134 sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
135 sizeof(*sf), 64, &brw->sf.state_offset);
136
137 memset(sf, 0, sizeof(*sf));
138
139 /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
140 sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
141 sf->thread0.kernel_start_pointer =
142 brw_program_reloc(brw,
143 brw->sf.state_offset +
144 offsetof(struct brw_sf_unit_state, thread0),
145 brw->sf.prog_offset +
146 (sf->thread0.grf_reg_count << 1)) >> 6;
147
148 sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
149
150 sf->thread3.dispatch_grf_start_reg = 3;
151 sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
152
153 /* CACHE_NEW_SF_PROG */
154 sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
155
156 /* BRW_NEW_URB_FENCE */
157 sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
158 sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
159
160 /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
161 * 48 (Ironlake) threads.
162 */
163 if (brw->gen == 5)
164 chipset_max_threads = 48;
165 else
166 chipset_max_threads = 24;
167
168 /* BRW_NEW_URB_FENCE */
169 sf->thread4.max_threads = MIN2(chipset_max_threads,
170 brw->urb.nr_sf_entries) - 1;
171
172 if (unlikely(INTEL_DEBUG & DEBUG_STATS))
173 sf->thread4.stats_enable = 1;
174
175 /* BRW_NEW_SF_VP */
176 sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
177 brw->sf.vp_offset) >> 5; /* reloc */
178
179 sf->sf5.viewport_transform = 1;
180
181 /* _NEW_SCISSOR */
182 if (ctx->Scissor.EnableFlags)
183 sf->sf6.scissor = 1;
184
185 /* _NEW_POLYGON */
186 if (ctx->Polygon.FrontFace == GL_CCW)
187 sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
188 else
189 sf->sf5.front_winding = BRW_FRONTWINDING_CW;
190
191 /* _NEW_BUFFERS
192 * The viewport is inverted for rendering to a FBO, and that inverts
193 * polygon front/back orientation.
194 */
195 sf->sf5.front_winding ^= render_to_fbo;
196
197 /* _NEW_POLYGON */
198 switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
199 case GL_FRONT:
200 sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
201 break;
202 case GL_BACK:
203 sf->sf6.cull_mode = BRW_CULLMODE_BACK;
204 break;
205 case GL_FRONT_AND_BACK:
206 sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
207 break;
208 case GL_NONE:
209 sf->sf6.cull_mode = BRW_CULLMODE_NONE;
210 break;
211 default:
212 unreachable("not reached");
213 }
214
215 /* _NEW_LINE */
216 sf->sf6.line_width =
217 CLAMP(ctx->Line.Width, 1.0, ctx->Const.MaxLineWidth) * (1<<1);
218
219 sf->sf6.line_endcap_aa_region_width = 1;
220 if (ctx->Line.SmoothFlag)
221 sf->sf6.aa_enable = 1;
222 else if (sf->sf6.line_width <= 0x2)
223 sf->sf6.line_width = 0;
224
225 /* _NEW_BUFFERS */
226 if (!render_to_fbo) {
227 /* Rendering to an OpenGL window */
228 sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
229 }
230 else {
231 /* If rendering to an FBO, the pixel coordinate system is
232 * inverted with respect to the normal OpenGL coordinate
233 * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
234 * But this value is listed as "Reserved, but not seen as useful"
235 * in Intel documentation (page 212, "Point Rasterization Rule",
236 * section 7.4 "SF Pipeline State Summary", of document
237 * "IntelĀ® 965 Express Chipset Family and IntelĀ® G35 Express
238 * Chipset Graphics Controller Programmer's Reference Manual,
239 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
240 * available at
241 * http://intellinuxgraphics.org/documentation.html
242 * at the time of this writing).
243 *
244 * It does work on at least some devices, if not all;
245 * if devices that don't support it can be identified,
246 * the likely failure case is that points are rasterized
247 * incorrectly, which is no worse than occurs without
248 * the value, so we're using it here.
249 */
250 sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
251 }
252 /* XXX clamp max depends on AA vs. non-AA */
253
254 /* _NEW_POINT */
255 sf->sf7.sprite_point = ctx->Point.PointSprite;
256 sf->sf7.point_size = CLAMP(rint(CLAMP(ctx->Point.Size,
257 ctx->Point.MinSize,
258 ctx->Point.MaxSize)), 1, 255) * (1<<3);
259 /* _NEW_PROGRAM | _NEW_POINT */
260 sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
261 ctx->Point._Attenuated);
262 sf->sf7.aa_line_distance_mode = 0;
263
264 /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
265 * _NEW_LIGHT
266 */
267 if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
268 sf->sf7.trifan_pv = 2;
269 sf->sf7.linestrip_pv = 1;
270 sf->sf7.tristrip_pv = 2;
271 } else {
272 sf->sf7.trifan_pv = 1;
273 sf->sf7.linestrip_pv = 0;
274 sf->sf7.tristrip_pv = 0;
275 }
276 sf->sf7.line_last_pixel_enable = 0;
277
278 /* Set bias for OpenGL rasterization rules:
279 */
280 sf->sf6.dest_org_vbias = 0x8;
281 sf->sf6.dest_org_hbias = 0x8;
282
283 /* STATE_PREFETCH command description describes this state as being
284 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
285 */
286
287 /* Emit SF viewport relocation */
288 drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
289 offsetof(struct brw_sf_unit_state, sf5)),
290 brw->batch.bo, (brw->sf.vp_offset |
291 sf->sf5.front_winding |
292 (sf->sf5.viewport_transform << 1)),
293 I915_GEM_DOMAIN_INSTRUCTION, 0);
294
295 brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
296 }
297
298 const struct brw_tracked_state brw_sf_unit = {
299 .dirty = {
300 .mesa = _NEW_BUFFERS |
301 _NEW_LIGHT |
302 _NEW_LINE |
303 _NEW_POINT |
304 _NEW_POLYGON |
305 _NEW_PROGRAM |
306 _NEW_SCISSOR,
307 .brw = BRW_NEW_BATCH |
308 BRW_NEW_PROGRAM_CACHE |
309 BRW_NEW_SF_VP |
310 BRW_NEW_URB_FENCE,
311 .cache = CACHE_NEW_SF_PROG,
312 },
313 .emit = upload_sf_unit,
314 };