src/mesa/drivers/dri/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "main/mtypes.h"
  35 #include "main/macros.h"
  36 #include "main/fbobject.h"
  37 #include "main/viewport.h"
  38 #include "intel_batchbuffer.h"
  39 #include "brw_context.h"
  40 #include "brw_state.h"
  41 #include "brw_defines.h"
  42
  43 static void upload_sf_unit( struct brw_context *brw )
  44 {
  45    struct gl_context *ctx = &brw->ctx;
  46    struct brw_sf_unit_state *sf;
  47    int chipset_max_threads;
  48    bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
  49
  50    sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
  51
  52    memset(sf, 0, sizeof(*sf));
  53
  54    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_SF_PROG_DATA */
  55    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
  56    sf->thread0.kernel_start_pointer =
  57       brw_program_reloc(brw,
  58                         brw->sf.state_offset +
  59                         offsetof(struct brw_sf_unit_state, thread0),
  60                         brw->sf.prog_offset +
  61                         (sf->thread0.grf_reg_count << 1)) >> 6;
  62
  63    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  64
  65    sf->thread3.dispatch_grf_start_reg = 3;
  66    sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
  67
  68    /* BRW_NEW_SF_PROG_DATA */
  69    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
  70
  71    /* BRW_NEW_URB_FENCE */
  72    sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
  73    sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
  74
  75    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
  76     * 48 (Ironlake) threads.
  77     */
  78    if (brw->gen == 5)
  79       chipset_max_threads = 48;
  80    else
  81       chipset_max_threads = 24;
  82
  83    /* BRW_NEW_URB_FENCE */
  84    sf->thread4.max_threads = MIN2(chipset_max_threads,
  85                                   brw->urb.nr_sf_entries) - 1;
  86
  87    /* BRW_NEW_SF_VP */
  88    sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
  89                                        brw->sf.vp_offset) >> 5; /* reloc */
  90
  91    sf->sf5.viewport_transform = 1;
  92
  93    sf->sf6.scissor = 1;
  94
  95    /* _NEW_POLYGON */
  96    if (ctx->Polygon._FrontBit)
  97       sf->sf5.front_winding = BRW_FRONTWINDING_CW;
  98    else
  99       sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
 100
 101    /* _NEW_BUFFERS
 102     * The viewport is inverted for rendering to a FBO, and that inverts
 103     * polygon front/back orientation.
 104     */
 105    sf->sf5.front_winding ^= render_to_fbo;
 106
 107    /* _NEW_POLYGON */
 108    switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
 109    case GL_FRONT:
 110       sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
 111       break;
 112    case GL_BACK:
 113       sf->sf6.cull_mode = BRW_CULLMODE_BACK;
 114       break;
 115    case GL_FRONT_AND_BACK:
 116       sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
 117       break;
 118    case GL_NONE:
 119       sf->sf6.cull_mode = BRW_CULLMODE_NONE;
 120       break;
 121    default:
 122       unreachable("not reached");
 123    }
 124
 125    /* _NEW_LINE */
 126    sf->sf6.line_width =
 127       CLAMP(ctx->Line.Width, 1.0f, ctx->Const.MaxLineWidth) * (1<<1);
 128
 129    sf->sf6.line_endcap_aa_region_width = 1;
 130    if (ctx->Line.SmoothFlag)
 131       sf->sf6.aa_enable = 1;
 132    else if (sf->sf6.line_width <= 0x2)
 133        sf->sf6.line_width = 0;
 134
 135    /* _NEW_BUFFERS */
 136    if (!render_to_fbo) {
 137       /* Rendering to an OpenGL window */
 138       sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 139    }
 140    else {
 141       /* If rendering to an FBO, the pixel coordinate system is
 142        * inverted with respect to the normal OpenGL coordinate
 143        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 144        * But this value is listed as "Reserved, but not seen as useful"
 145        * in Intel documentation (page 212, "Point Rasterization Rule",
 146        * section 7.4 "SF Pipeline State Summary", of document
 147        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 148        * Chipset Graphics Controller Programmer's Reference Manual,
 149        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 150        * available at
 151        *     https://01.org/linuxgraphics/documentation/hardware-specification-prms
 152        * at the time of this writing).
 153        *
 154        * It does work on at least some devices, if not all;
 155        * if devices that don't support it can be identified,
 156        * the likely failure case is that points are rasterized
 157        * incorrectly, which is no worse than occurs without
 158        * the value, so we're using it here.
 159        */
 160       sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 161    }
 162
 163    /* _NEW_POINT */
 164    sf->sf7.sprite_point = ctx->Point.PointSprite;
 165
 166    float point_sz;
 167    point_sz = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
 168    point_sz = CLAMP(point_sz, 0.125f, 255.875f);
 169    sf->sf7.point_size = U_FIXED(point_sz, 3);
 170
 171    /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
 172    sf->sf7.use_point_size_state = use_state_point_size(brw);
 173    sf->sf7.aa_line_distance_mode = brw->is_g4x || brw->gen == 5;
 174
 175    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 176     * _NEW_LIGHT
 177     */
 178    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 179       sf->sf7.trifan_pv = 2;
 180       sf->sf7.linestrip_pv = 1;
 181       sf->sf7.tristrip_pv = 2;
 182    } else {
 183       sf->sf7.trifan_pv = 1;
 184       sf->sf7.linestrip_pv = 0;
 185       sf->sf7.tristrip_pv = 0;
 186    }
 187    sf->sf7.line_last_pixel_enable = 0;
 188
 189    /* Set bias for OpenGL rasterization rules:
 190     */
 191    sf->sf6.dest_org_vbias = 0x8;
 192    sf->sf6.dest_org_hbias = 0x8;
 193
 194    /* STATE_PREFETCH command description describes this state as being
 195     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 196     */
 197
 198    /* Emit SF viewport relocation */
 199    brw_emit_reloc(&brw->batch,
 200                   brw->sf.state_offset +
 201                   offsetof(struct brw_sf_unit_state, sf5),
 202                   brw->batch.bo,
 203                   brw->sf.vp_offset | sf->sf5.front_winding |
 204                   (sf->sf5.viewport_transform << 1),
 205                   I915_GEM_DOMAIN_INSTRUCTION, 0);
 206
 207    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 208 }
 209
 210 const struct brw_tracked_state brw_sf_unit = {
 211    .dirty = {
 212       .mesa  = _NEW_BUFFERS |
 213                _NEW_LIGHT |
 214                _NEW_LINE |
 215                _NEW_POINT |
 216                _NEW_POLYGON |
 217                _NEW_PROGRAM,
 218       .brw   = BRW_NEW_BATCH |
 219                BRW_NEW_BLORP |
 220                BRW_NEW_PROGRAM_CACHE |
 221                BRW_NEW_SF_PROG_DATA |
 222                BRW_NEW_SF_VP |
 223                BRW_NEW_VUE_MAP_GEOM_OUT |
 224                BRW_NEW_URB_FENCE,
 225    },
 226    .emit = upload_sf_unit,
 227 };