src/mesa/drivers/dri/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38 #include "brw_sf.h"
  39
  40 static void upload_sf_vp(struct brw_context *brw)
  41 {
  42    struct intel_context *intel = &brw->intel;
  43    struct gl_context *ctx = &intel->ctx;
  44    const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
  45    struct brw_sf_viewport *sfv;
  46    GLfloat y_scale, y_bias;
  47    const bool render_to_fbo = (ctx->DrawBuffer->Name != 0);
  48    const GLfloat *v = ctx->Viewport._WindowMap.m;
  49
  50    sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
  51                          sizeof(*sfv), 32, &brw->sf.vp_offset);
  52    memset(sfv, 0, sizeof(*sfv));
  53
  54    if (render_to_fbo) {
  55       y_scale = 1.0;
  56       y_bias = 0;
  57    }
  58    else {
  59       y_scale = -1.0;
  60       y_bias = ctx->DrawBuffer->Height;
  61    }
  62
  63    /* _NEW_VIEWPORT */
  64
  65    sfv->viewport.m00 = v[MAT_SX];
  66    sfv->viewport.m11 = v[MAT_SY] * y_scale;
  67    sfv->viewport.m22 = v[MAT_SZ] * depth_scale;
  68    sfv->viewport.m30 = v[MAT_TX];
  69    sfv->viewport.m31 = v[MAT_TY] * y_scale + y_bias;
  70    sfv->viewport.m32 = v[MAT_TZ] * depth_scale;
  71
  72    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
  73     * for DrawBuffer->_[XY]{min,max}
  74     */
  75
  76    /* The scissor only needs to handle the intersection of drawable
  77     * and scissor rect, since there are no longer cliprects for shared
  78     * buffers with DRI2.
  79     *
  80     * Note that the hardware's coordinates are inclusive, while Mesa's min is
  81     * inclusive but max is exclusive.
  82     */
  83
  84    if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
  85        ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
  86       /* If the scissor was out of bounds and got clamped to 0
  87        * width/height at the bounds, the subtraction of 1 from
  88        * maximums could produce a negative number and thus not clip
  89        * anything.  Instead, just provide a min > max scissor inside
  90        * the bounds, which produces the expected no rendering.
  91        */
  92       sfv->scissor.xmin = 1;
  93       sfv->scissor.xmax = 0;
  94       sfv->scissor.ymin = 1;
  95       sfv->scissor.ymax = 0;
  96    } else if (render_to_fbo) {
  97       /* texmemory: Y=0=bottom */
  98       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
  99       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 100       sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
 101       sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
 102    }
 103    else {
 104       /* memory: Y=0=top */
 105       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 106       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 107       sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
 108       sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
 109    }
 110
 111    brw->state.dirty.cache |= CACHE_NEW_SF_VP;
 112 }
 113
 114 const struct brw_tracked_state brw_sf_vp = {
 115    .dirty = {
 116       .mesa  = (_NEW_VIEWPORT |
 117                 _NEW_SCISSOR |
 118                 _NEW_BUFFERS),
 119       .brw   = BRW_NEW_BATCH,
 120       .cache = 0
 121    },
 122    .prepare = upload_sf_vp
 123 };
 124
 125 /**
 126  * Compute the offset within the URB (expressed in 256-bit register
 127  * increments) that should be used to read the VUE in th efragment shader.
 128  */
 129 int
 130 brw_sf_compute_urb_entry_read_offset(struct intel_context *intel)
 131 {
 132    if (intel->gen == 5)
 133       return 3;
 134    else
 135       return 1;
 136 }
 137
 138 static void upload_sf_unit( struct brw_context *brw )
 139 {
 140    struct intel_context *intel = &brw->intel;
 141    struct gl_context *ctx = &intel->ctx;
 142    struct brw_sf_unit_state *sf;
 143    drm_intel_bo *bo = intel->batch.bo;
 144    int chipset_max_threads;
 145    bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
 146
 147    sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
 148                         sizeof(*sf), 64, &brw->sf.state_offset);
 149
 150    memset(sf, 0, sizeof(*sf));
 151
 152    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
 153    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
 154    sf->thread0.kernel_start_pointer =
 155       brw_program_reloc(brw,
 156                         brw->sf.state_offset +
 157                         offsetof(struct brw_sf_unit_state, thread0),
 158                         brw->sf.prog_offset +
 159                         (sf->thread0.grf_reg_count << 1)) >> 6;
 160
 161    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 162
 163    sf->thread3.dispatch_grf_start_reg = 3;
 164
 165    sf->thread3.urb_entry_read_offset =
 166       brw_sf_compute_urb_entry_read_offset(intel);
 167
 168    /* CACHE_NEW_SF_PROG */
 169    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 170
 171    /* BRW_NEW_URB_FENCE */
 172    sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
 173    sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
 174
 175    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
 176     * 48 (Ironlake) threads.
 177     */
 178    if (intel->gen == 5)
 179       chipset_max_threads = 48;
 180    else
 181       chipset_max_threads = 24;
 182
 183    /* BRW_NEW_URB_FENCE */
 184    sf->thread4.max_threads = MIN2(chipset_max_threads,
 185                                   brw->urb.nr_sf_entries) - 1;
 186
 187    if (unlikely(INTEL_DEBUG & DEBUG_SINGLE_THREAD))
 188       sf->thread4.max_threads = 0;
 189
 190    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 191       sf->thread4.stats_enable = 1;
 192
 193    /* CACHE_NEW_SF_VP */
 194    sf->sf5.sf_viewport_state_offset = (intel->batch.bo->offset +
 195                                        brw->sf.vp_offset) >> 5; /* reloc */
 196
 197    sf->sf5.viewport_transform = 1;
 198
 199    /* _NEW_SCISSOR */
 200    if (ctx->Scissor.Enabled)
 201       sf->sf6.scissor = 1;
 202
 203    /* _NEW_POLYGON */
 204    if (ctx->Polygon.FrontFace == GL_CCW)
 205       sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
 206    else
 207       sf->sf5.front_winding = BRW_FRONTWINDING_CW;
 208
 209    /* _NEW_BUFFERS
 210     * The viewport is inverted for rendering to a FBO, and that inverts
 211     * polygon front/back orientation.
 212     */
 213    sf->sf5.front_winding ^= render_to_fbo;
 214
 215    /* _NEW_POLYGON */
 216    switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
 217    case GL_FRONT:
 218       sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
 219       break;
 220    case GL_BACK:
 221       sf->sf6.cull_mode = BRW_CULLMODE_BACK;
 222       break;
 223    case GL_FRONT_AND_BACK:
 224       sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
 225       break;
 226    case GL_NONE:
 227       sf->sf6.cull_mode = BRW_CULLMODE_NONE;
 228       break;
 229    default:
 230       assert(0);
 231       break;
 232    }
 233
 234    /* _NEW_LINE */
 235    /* XXX use ctx->Const.Min/MaxLineWidth here */
 236    sf->sf6.line_width = CLAMP(ctx->Line.Width, 1.0, 5.0) * (1<<1);
 237
 238    sf->sf6.line_endcap_aa_region_width = 1;
 239    if (ctx->Line.SmoothFlag)
 240       sf->sf6.aa_enable = 1;
 241    else if (sf->sf6.line_width <= 0x2)
 242        sf->sf6.line_width = 0;
 243
 244    /* _NEW_BUFFERS */
 245    if (!render_to_fbo) {
 246       /* Rendering to an OpenGL window */
 247       sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 248    }
 249    else {
 250       /* If rendering to an FBO, the pixel coordinate system is
 251        * inverted with respect to the normal OpenGL coordinate
 252        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 253        * But this value is listed as "Reserved, but not seen as useful"
 254        * in Intel documentation (page 212, "Point Rasterization Rule",
 255        * section 7.4 "SF Pipeline State Summary", of document
 256        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 257        * Chipset Graphics Controller Programmer's Reference Manual,
 258        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 259        * available at
 260        *     http://intellinuxgraphics.org/documentation.html
 261        * at the time of this writing).
 262        *
 263        * It does work on at least some devices, if not all;
 264        * if devices that don't support it can be identified,
 265        * the likely failure case is that points are rasterized
 266        * incorrectly, which is no worse than occurs without
 267        * the value, so we're using it here.
 268        */
 269       sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 270    }
 271    /* XXX clamp max depends on AA vs. non-AA */
 272
 273    /* _NEW_POINT */
 274    sf->sf7.sprite_point = ctx->Point.PointSprite;
 275    sf->sf7.point_size = CLAMP(rint(CLAMP(ctx->Point.Size,
 276                                          ctx->Point.MinSize,
 277                                          ctx->Point.MaxSize)), 1, 255) * (1<<3);
 278    sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
 279                                     ctx->Point._Attenuated);
 280    sf->sf7.aa_line_distance_mode = 0;
 281
 282    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 283     * _NEW_LIGHT
 284     */
 285    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 286       sf->sf7.trifan_pv = 2;
 287       sf->sf7.linestrip_pv = 1;
 288       sf->sf7.tristrip_pv = 2;
 289    } else {
 290       sf->sf7.trifan_pv = 1;
 291       sf->sf7.linestrip_pv = 0;
 292       sf->sf7.tristrip_pv = 0;
 293    }
 294    sf->sf7.line_last_pixel_enable = 0;
 295
 296    /* Set bias for OpenGL rasterization rules:
 297     */
 298    sf->sf6.dest_org_vbias = 0x8;
 299    sf->sf6.dest_org_hbias = 0x8;
 300
 301    /* STATE_PREFETCH command description describes this state as being
 302     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 303     */
 304
 305    /* Emit SF viewport relocation */
 306    drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
 307                                 offsetof(struct brw_sf_unit_state, sf5)),
 308                            intel->batch.bo, (brw->sf.vp_offset |
 309                                              sf->sf5.front_winding |
 310                                              (sf->sf5.viewport_transform << 1)),
 311                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 312
 313    brw->state.dirty.cache |= CACHE_NEW_SF_UNIT;
 314 }
 315
 316 const struct brw_tracked_state brw_sf_unit = {
 317    .dirty = {
 318       .mesa  = (_NEW_POLYGON |
 319                 _NEW_LIGHT |
 320                 _NEW_LINE |
 321                 _NEW_POINT |
 322                 _NEW_SCISSOR |
 323                 _NEW_BUFFERS),
 324       .brw   = (BRW_NEW_BATCH |
 325                 BRW_NEW_PROGRAM_CACHE |
 326                 BRW_NEW_URB_FENCE),
 327       .cache = (CACHE_NEW_SF_VP |
 328                 CACHE_NEW_SF_PROG)
 329    },
 330    .prepare = upload_sf_unit,
 331 };