src/mesa/drivers/dri/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "main/mtypes.h"
  35 #include "main/macros.h"
  36 #include "main/fbobject.h"
  37 #include "main/viewport.h"
  38 #include "intel_batchbuffer.h"
  39 #include "brw_context.h"
  40 #include "brw_state.h"
  41 #include "brw_defines.h"
  42
  43 static void upload_sf_vp(struct brw_context *brw)
  44 {
  45    struct gl_context *ctx = &brw->ctx;
  46    struct brw_sf_viewport *sfv;
  47    GLfloat y_scale, y_bias;
  48    float scale[3], translate[3];
  49    const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
  50
  51    sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
  52    memset(sfv, 0, sizeof(*sfv));
  53
  54    /* Accessing the fields Width and Height of gl_framebuffer to produce the
  55     * values to program the viewport and scissor is fine as long as the
  56     * gl_framebuffer has atleast one attachment.
  57     */
  58    assert(ctx->DrawBuffer->_HasAttachments);
  59
  60    if (render_to_fbo) {
  61       y_scale = 1.0;
  62       y_bias = 0;
  63    }
  64    else {
  65       y_scale = -1.0;
  66       y_bias = ctx->DrawBuffer->Height;
  67    }
  68
  69    /* _NEW_VIEWPORT */
  70
  71    _mesa_get_viewport_xform(ctx, 0, scale, translate);
  72    sfv->viewport.m00 = scale[0];
  73    sfv->viewport.m11 = scale[1] * y_scale;
  74    sfv->viewport.m22 = scale[2];
  75    sfv->viewport.m30 = translate[0];
  76    sfv->viewport.m31 = translate[1] * y_scale + y_bias;
  77    sfv->viewport.m32 = translate[2];
  78
  79    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
  80     * for DrawBuffer->_[XY]{min,max}
  81     */
  82
  83    /* The scissor only needs to handle the intersection of drawable
  84     * and scissor rect, since there are no longer cliprects for shared
  85     * buffers with DRI2.
  86     *
  87     * Note that the hardware's coordinates are inclusive, while Mesa's min is
  88     * inclusive but max is exclusive.
  89     */
  90
  91    if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
  92        ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
  93       /* If the scissor was out of bounds and got clamped to 0
  94        * width/height at the bounds, the subtraction of 1 from
  95        * maximums could produce a negative number and thus not clip
  96        * anything.  Instead, just provide a min > max scissor inside
  97        * the bounds, which produces the expected no rendering.
  98        */
  99       sfv->scissor.xmin = 1;
 100       sfv->scissor.xmax = 0;
 101       sfv->scissor.ymin = 1;
 102       sfv->scissor.ymax = 0;
 103    } else if (render_to_fbo) {
 104       /* texmemory: Y=0=bottom */
 105       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 106       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 107       sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
 108       sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
 109    }
 110    else {
 111       /* memory: Y=0=top */
 112       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 113       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 114       sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
 115       sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
 116    }
 117
 118    brw->ctx.NewDriverState |= BRW_NEW_SF_VP;
 119 }
 120
 121 const struct brw_tracked_state brw_sf_vp = {
 122    .dirty = {
 123       .mesa  = _NEW_BUFFERS |
 124                _NEW_SCISSOR |
 125                _NEW_VIEWPORT,
 126       .brw   = BRW_NEW_BATCH |
 127                BRW_NEW_BLORP,
 128    },
 129    .emit = upload_sf_vp
 130 };
 131
 132 static void upload_sf_unit( struct brw_context *brw )
 133 {
 134    struct gl_context *ctx = &brw->ctx;
 135    struct brw_sf_unit_state *sf;
 136    int chipset_max_threads;
 137    bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 138
 139    sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
 140
 141    memset(sf, 0, sizeof(*sf));
 142
 143    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_SF_PROG_DATA */
 144    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
 145    sf->thread0.kernel_start_pointer =
 146       brw_program_reloc(brw,
 147                         brw->sf.state_offset +
 148                         offsetof(struct brw_sf_unit_state, thread0),
 149                         brw->sf.prog_offset +
 150                         (sf->thread0.grf_reg_count << 1)) >> 6;
 151
 152    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 153
 154    sf->thread3.dispatch_grf_start_reg = 3;
 155    sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
 156
 157    /* BRW_NEW_SF_PROG_DATA */
 158    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 159
 160    /* BRW_NEW_URB_FENCE */
 161    sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
 162    sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
 163
 164    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
 165     * 48 (Ironlake) threads.
 166     */
 167    if (brw->gen == 5)
 168       chipset_max_threads = 48;
 169    else
 170       chipset_max_threads = 24;
 171
 172    /* BRW_NEW_URB_FENCE */
 173    sf->thread4.max_threads = MIN2(chipset_max_threads,
 174                                   brw->urb.nr_sf_entries) - 1;
 175
 176    /* BRW_NEW_SF_VP */
 177    sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
 178                                        brw->sf.vp_offset) >> 5; /* reloc */
 179
 180    sf->sf5.viewport_transform = 1;
 181
 182    /* _NEW_SCISSOR */
 183    if (ctx->Scissor.EnableFlags)
 184       sf->sf6.scissor = 1;
 185
 186    /* _NEW_POLYGON */
 187    if (ctx->Polygon._FrontBit)
 188       sf->sf5.front_winding = BRW_FRONTWINDING_CW;
 189    else
 190       sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
 191
 192    /* _NEW_BUFFERS
 193     * The viewport is inverted for rendering to a FBO, and that inverts
 194     * polygon front/back orientation.
 195     */
 196    sf->sf5.front_winding ^= render_to_fbo;
 197
 198    /* _NEW_POLYGON */
 199    switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
 200    case GL_FRONT:
 201       sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
 202       break;
 203    case GL_BACK:
 204       sf->sf6.cull_mode = BRW_CULLMODE_BACK;
 205       break;
 206    case GL_FRONT_AND_BACK:
 207       sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
 208       break;
 209    case GL_NONE:
 210       sf->sf6.cull_mode = BRW_CULLMODE_NONE;
 211       break;
 212    default:
 213       unreachable("not reached");
 214    }
 215
 216    /* _NEW_LINE */
 217    sf->sf6.line_width =
 218       CLAMP(ctx->Line.Width, 1.0f, ctx->Const.MaxLineWidth) * (1<<1);
 219
 220    sf->sf6.line_endcap_aa_region_width = 1;
 221    if (ctx->Line.SmoothFlag)
 222       sf->sf6.aa_enable = 1;
 223    else if (sf->sf6.line_width <= 0x2)
 224        sf->sf6.line_width = 0;
 225
 226    /* _NEW_BUFFERS */
 227    if (!render_to_fbo) {
 228       /* Rendering to an OpenGL window */
 229       sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 230    }
 231    else {
 232       /* If rendering to an FBO, the pixel coordinate system is
 233        * inverted with respect to the normal OpenGL coordinate
 234        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 235        * But this value is listed as "Reserved, but not seen as useful"
 236        * in Intel documentation (page 212, "Point Rasterization Rule",
 237        * section 7.4 "SF Pipeline State Summary", of document
 238        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 239        * Chipset Graphics Controller Programmer's Reference Manual,
 240        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 241        * available at
 242        *     https://01.org/linuxgraphics/documentation/hardware-specification-prms
 243        * at the time of this writing).
 244        *
 245        * It does work on at least some devices, if not all;
 246        * if devices that don't support it can be identified,
 247        * the likely failure case is that points are rasterized
 248        * incorrectly, which is no worse than occurs without
 249        * the value, so we're using it here.
 250        */
 251       sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 252    }
 253    /* XXX clamp max depends on AA vs. non-AA */
 254
 255    /* _NEW_POINT */
 256    sf->sf7.sprite_point = ctx->Point.PointSprite;
 257    sf->sf7.point_size = CLAMP(rintf(CLAMP(ctx->Point.Size,
 258                                           ctx->Point.MinSize,
 259                                           ctx->Point.MaxSize)), 1.0f, 255.0f) *
 260                         (1<<3);
 261    /* _NEW_PROGRAM | _NEW_POINT */
 262    sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
 263                                     ctx->Point._Attenuated);
 264    sf->sf7.aa_line_distance_mode = brw->is_g4x || brw->gen == 5;
 265
 266    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 267     * _NEW_LIGHT
 268     */
 269    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 270       sf->sf7.trifan_pv = 2;
 271       sf->sf7.linestrip_pv = 1;
 272       sf->sf7.tristrip_pv = 2;
 273    } else {
 274       sf->sf7.trifan_pv = 1;
 275       sf->sf7.linestrip_pv = 0;
 276       sf->sf7.tristrip_pv = 0;
 277    }
 278    sf->sf7.line_last_pixel_enable = 0;
 279
 280    /* Set bias for OpenGL rasterization rules:
 281     */
 282    sf->sf6.dest_org_vbias = 0x8;
 283    sf->sf6.dest_org_hbias = 0x8;
 284
 285    /* STATE_PREFETCH command description describes this state as being
 286     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 287     */
 288
 289    /* Emit SF viewport relocation */
 290    brw_emit_reloc(&brw->batch,
 291                   brw->sf.state_offset +
 292                   offsetof(struct brw_sf_unit_state, sf5),
 293                   brw->batch.bo,
 294                   brw->sf.vp_offset | sf->sf5.front_winding |
 295                   (sf->sf5.viewport_transform << 1),
 296                   I915_GEM_DOMAIN_INSTRUCTION, 0);
 297
 298    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 299 }
 300
 301 const struct brw_tracked_state brw_sf_unit = {
 302    .dirty = {
 303       .mesa  = _NEW_BUFFERS |
 304                _NEW_LIGHT |
 305                _NEW_LINE |
 306                _NEW_POINT |
 307                _NEW_POLYGON |
 308                _NEW_PROGRAM |
 309                _NEW_SCISSOR,
 310       .brw   = BRW_NEW_BATCH |
 311                BRW_NEW_BLORP |
 312                BRW_NEW_PROGRAM_CACHE |
 313                BRW_NEW_SF_PROG_DATA |
 314                BRW_NEW_SF_VP |
 315                BRW_NEW_URB_FENCE,
 316    },
 317    .emit = upload_sf_unit,
 318 };