src/mesa/drivers/dri/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "main/mtypes.h"
  35 #include "main/macros.h"
  36 #include "main/fbobject.h"
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40 #include "brw_sf.h"
  41
  42 static void upload_sf_vp(struct brw_context *brw)
  43 {
  44    struct intel_context *intel = &brw->intel;
  45    struct gl_context *ctx = &intel->ctx;
  46    const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
  47    struct brw_sf_viewport *sfv;
  48    GLfloat y_scale, y_bias;
  49    const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
  50    const GLfloat *v = ctx->Viewport._WindowMap.m;
  51
  52    sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
  53                          sizeof(*sfv), 32, &brw->sf.vp_offset);
  54    memset(sfv, 0, sizeof(*sfv));
  55
  56    if (render_to_fbo) {
  57       y_scale = 1.0;
  58       y_bias = 0;
  59    }
  60    else {
  61       y_scale = -1.0;
  62       y_bias = ctx->DrawBuffer->Height;
  63    }
  64
  65    /* _NEW_VIEWPORT */
  66
  67    sfv->viewport.m00 = v[MAT_SX];
  68    sfv->viewport.m11 = v[MAT_SY] * y_scale;
  69    sfv->viewport.m22 = v[MAT_SZ] * depth_scale;
  70    sfv->viewport.m30 = v[MAT_TX];
  71    sfv->viewport.m31 = v[MAT_TY] * y_scale + y_bias;
  72    sfv->viewport.m32 = v[MAT_TZ] * depth_scale;
  73
  74    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
  75     * for DrawBuffer->_[XY]{min,max}
  76     */
  77
  78    /* The scissor only needs to handle the intersection of drawable
  79     * and scissor rect, since there are no longer cliprects for shared
  80     * buffers with DRI2.
  81     *
  82     * Note that the hardware's coordinates are inclusive, while Mesa's min is
  83     * inclusive but max is exclusive.
  84     */
  85
  86    if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
  87        ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
  88       /* If the scissor was out of bounds and got clamped to 0
  89        * width/height at the bounds, the subtraction of 1 from
  90        * maximums could produce a negative number and thus not clip
  91        * anything.  Instead, just provide a min > max scissor inside
  92        * the bounds, which produces the expected no rendering.
  93        */
  94       sfv->scissor.xmin = 1;
  95       sfv->scissor.xmax = 0;
  96       sfv->scissor.ymin = 1;
  97       sfv->scissor.ymax = 0;
  98    } else if (render_to_fbo) {
  99       /* texmemory: Y=0=bottom */
 100       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 101       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 102       sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
 103       sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
 104    }
 105    else {
 106       /* memory: Y=0=top */
 107       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 108       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 109       sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
 110       sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
 111    }
 112
 113    brw->state.dirty.cache |= CACHE_NEW_SF_VP;
 114 }
 115
 116 const struct brw_tracked_state brw_sf_vp = {
 117    .dirty = {
 118       .mesa  = (_NEW_VIEWPORT |
 119                 _NEW_SCISSOR |
 120                 _NEW_BUFFERS),
 121       .brw   = BRW_NEW_BATCH,
 122       .cache = 0
 123    },
 124    .emit = upload_sf_vp
 125 };
 126
 127 static void upload_sf_unit( struct brw_context *brw )
 128 {
 129    struct intel_context *intel = &brw->intel;
 130    struct gl_context *ctx = &intel->ctx;
 131    struct brw_sf_unit_state *sf;
 132    drm_intel_bo *bo = brw->batch.bo;
 133    int chipset_max_threads;
 134    bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 135
 136    sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
 137                         sizeof(*sf), 64, &brw->sf.state_offset);
 138
 139    memset(sf, 0, sizeof(*sf));
 140
 141    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
 142    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
 143    sf->thread0.kernel_start_pointer =
 144       brw_program_reloc(brw,
 145                         brw->sf.state_offset +
 146                         offsetof(struct brw_sf_unit_state, thread0),
 147                         brw->sf.prog_offset +
 148                         (sf->thread0.grf_reg_count << 1)) >> 6;
 149
 150    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 151
 152    sf->thread3.dispatch_grf_start_reg = 3;
 153    sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
 154
 155    /* CACHE_NEW_SF_PROG */
 156    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 157
 158    /* BRW_NEW_URB_FENCE */
 159    sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
 160    sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
 161
 162    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
 163     * 48 (Ironlake) threads.
 164     */
 165    if (brw->gen == 5)
 166       chipset_max_threads = 48;
 167    else
 168       chipset_max_threads = 24;
 169
 170    /* BRW_NEW_URB_FENCE */
 171    sf->thread4.max_threads = MIN2(chipset_max_threads,
 172                                   brw->urb.nr_sf_entries) - 1;
 173
 174    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 175       sf->thread4.stats_enable = 1;
 176
 177    /* CACHE_NEW_SF_VP */
 178    sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset +
 179                                        brw->sf.vp_offset) >> 5; /* reloc */
 180
 181    sf->sf5.viewport_transform = 1;
 182
 183    /* _NEW_SCISSOR */
 184    if (ctx->Scissor.Enabled)
 185       sf->sf6.scissor = 1;
 186
 187    /* _NEW_POLYGON */
 188    if (ctx->Polygon.FrontFace == GL_CCW)
 189       sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
 190    else
 191       sf->sf5.front_winding = BRW_FRONTWINDING_CW;
 192
 193    /* _NEW_BUFFERS
 194     * The viewport is inverted for rendering to a FBO, and that inverts
 195     * polygon front/back orientation.
 196     */
 197    sf->sf5.front_winding ^= render_to_fbo;
 198
 199    /* _NEW_POLYGON */
 200    switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
 201    case GL_FRONT:
 202       sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
 203       break;
 204    case GL_BACK:
 205       sf->sf6.cull_mode = BRW_CULLMODE_BACK;
 206       break;
 207    case GL_FRONT_AND_BACK:
 208       sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
 209       break;
 210    case GL_NONE:
 211       sf->sf6.cull_mode = BRW_CULLMODE_NONE;
 212       break;
 213    default:
 214       assert(0);
 215       break;
 216    }
 217
 218    /* _NEW_LINE */
 219    /* XXX use ctx->Const.Min/MaxLineWidth here */
 220    sf->sf6.line_width = CLAMP(ctx->Line.Width, 1.0, 5.0) * (1<<1);
 221
 222    sf->sf6.line_endcap_aa_region_width = 1;
 223    if (ctx->Line.SmoothFlag)
 224       sf->sf6.aa_enable = 1;
 225    else if (sf->sf6.line_width <= 0x2)
 226        sf->sf6.line_width = 0;
 227
 228    /* _NEW_BUFFERS */
 229    if (!render_to_fbo) {
 230       /* Rendering to an OpenGL window */
 231       sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 232    }
 233    else {
 234       /* If rendering to an FBO, the pixel coordinate system is
 235        * inverted with respect to the normal OpenGL coordinate
 236        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 237        * But this value is listed as "Reserved, but not seen as useful"
 238        * in Intel documentation (page 212, "Point Rasterization Rule",
 239        * section 7.4 "SF Pipeline State Summary", of document
 240        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 241        * Chipset Graphics Controller Programmer's Reference Manual,
 242        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 243        * available at
 244        *     http://intellinuxgraphics.org/documentation.html
 245        * at the time of this writing).
 246        *
 247        * It does work on at least some devices, if not all;
 248        * if devices that don't support it can be identified,
 249        * the likely failure case is that points are rasterized
 250        * incorrectly, which is no worse than occurs without
 251        * the value, so we're using it here.
 252        */
 253       sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 254    }
 255    /* XXX clamp max depends on AA vs. non-AA */
 256
 257    /* _NEW_POINT */
 258    sf->sf7.sprite_point = ctx->Point.PointSprite;
 259    sf->sf7.point_size = CLAMP(rint(CLAMP(ctx->Point.Size,
 260                                          ctx->Point.MinSize,
 261                                          ctx->Point.MaxSize)), 1, 255) * (1<<3);
 262    /* _NEW_PROGRAM | _NEW_POINT */
 263    sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
 264                                     ctx->Point._Attenuated);
 265    sf->sf7.aa_line_distance_mode = 0;
 266
 267    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 268     * _NEW_LIGHT
 269     */
 270    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 271       sf->sf7.trifan_pv = 2;
 272       sf->sf7.linestrip_pv = 1;
 273       sf->sf7.tristrip_pv = 2;
 274    } else {
 275       sf->sf7.trifan_pv = 1;
 276       sf->sf7.linestrip_pv = 0;
 277       sf->sf7.tristrip_pv = 0;
 278    }
 279    sf->sf7.line_last_pixel_enable = 0;
 280
 281    /* Set bias for OpenGL rasterization rules:
 282     */
 283    sf->sf6.dest_org_vbias = 0x8;
 284    sf->sf6.dest_org_hbias = 0x8;
 285
 286    /* STATE_PREFETCH command description describes this state as being
 287     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 288     */
 289
 290    /* Emit SF viewport relocation */
 291    drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
 292                                 offsetof(struct brw_sf_unit_state, sf5)),
 293                            brw->batch.bo, (brw->sf.vp_offset |
 294                                              sf->sf5.front_winding |
 295                                              (sf->sf5.viewport_transform << 1)),
 296                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 297
 298    brw->state.dirty.cache |= CACHE_NEW_SF_UNIT;
 299 }
 300
 301 const struct brw_tracked_state brw_sf_unit = {
 302    .dirty = {
 303       .mesa  = (_NEW_POLYGON |
 304                 _NEW_PROGRAM |
 305                 _NEW_LIGHT |
 306                 _NEW_LINE |
 307                 _NEW_POINT |
 308                 _NEW_SCISSOR |
 309                 _NEW_BUFFERS),
 310       .brw   = (BRW_NEW_BATCH |
 311                 BRW_NEW_PROGRAM_CACHE |
 312                 BRW_NEW_URB_FENCE),
 313       .cache = (CACHE_NEW_SF_VP |
 314                 CACHE_NEW_SF_PROG)
 315    },
 316    .emit = upload_sf_unit,
 317 };