src/mesa/drivers/dri/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "main/mtypes.h"
  35 #include "main/macros.h"
  36 #include "main/fbobject.h"
  37 #include "main/viewport.h"
  38 #include "intel_batchbuffer.h"
  39 #include "brw_context.h"
  40 #include "brw_state.h"
  41 #include "brw_defines.h"
  42 #include "brw_sf.h"
  43
  44 static void upload_sf_vp(struct brw_context *brw)
  45 {
  46    struct gl_context *ctx = &brw->ctx;
  47    struct brw_sf_viewport *sfv;
  48    GLfloat y_scale, y_bias;
  49    float scale[3], translate[3];
  50    const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
  51
  52    sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
  53    memset(sfv, 0, sizeof(*sfv));
  54
  55    /* Accessing the fields Width and Height of gl_framebuffer to produce the
  56     * values to program the viewport and scissor is fine as long as the
  57     * gl_framebuffer has atleast one attachment.
  58     */
  59    assert(ctx->DrawBuffer->_HasAttachments);
  60
  61    if (render_to_fbo) {
  62       y_scale = 1.0;
  63       y_bias = 0;
  64    }
  65    else {
  66       y_scale = -1.0;
  67       y_bias = ctx->DrawBuffer->Height;
  68    }
  69
  70    /* _NEW_VIEWPORT */
  71
  72    _mesa_get_viewport_xform(ctx, 0, scale, translate);
  73    sfv->viewport.m00 = scale[0];
  74    sfv->viewport.m11 = scale[1] * y_scale;
  75    sfv->viewport.m22 = scale[2];
  76    sfv->viewport.m30 = translate[0];
  77    sfv->viewport.m31 = translate[1] * y_scale + y_bias;
  78    sfv->viewport.m32 = translate[2];
  79
  80    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
  81     * for DrawBuffer->_[XY]{min,max}
  82     */
  83
  84    /* The scissor only needs to handle the intersection of drawable
  85     * and scissor rect, since there are no longer cliprects for shared
  86     * buffers with DRI2.
  87     *
  88     * Note that the hardware's coordinates are inclusive, while Mesa's min is
  89     * inclusive but max is exclusive.
  90     */
  91
  92    if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
  93        ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
  94       /* If the scissor was out of bounds and got clamped to 0
  95        * width/height at the bounds, the subtraction of 1 from
  96        * maximums could produce a negative number and thus not clip
  97        * anything.  Instead, just provide a min > max scissor inside
  98        * the bounds, which produces the expected no rendering.
  99        */
 100       sfv->scissor.xmin = 1;
 101       sfv->scissor.xmax = 0;
 102       sfv->scissor.ymin = 1;
 103       sfv->scissor.ymax = 0;
 104    } else if (render_to_fbo) {
 105       /* texmemory: Y=0=bottom */
 106       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 107       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 108       sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
 109       sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
 110    }
 111    else {
 112       /* memory: Y=0=top */
 113       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 114       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 115       sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
 116       sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
 117    }
 118
 119    brw->ctx.NewDriverState |= BRW_NEW_SF_VP;
 120 }
 121
 122 const struct brw_tracked_state brw_sf_vp = {
 123    .dirty = {
 124       .mesa  = _NEW_BUFFERS |
 125                _NEW_SCISSOR |
 126                _NEW_VIEWPORT,
 127       .brw   = BRW_NEW_BATCH |
 128                BRW_NEW_BLORP,
 129    },
 130    .emit = upload_sf_vp
 131 };
 132
 133 static void upload_sf_unit( struct brw_context *brw )
 134 {
 135    struct gl_context *ctx = &brw->ctx;
 136    struct brw_sf_unit_state *sf;
 137    int chipset_max_threads;
 138    bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 139
 140    sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
 141
 142    memset(sf, 0, sizeof(*sf));
 143
 144    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_SF_PROG_DATA */
 145    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
 146    sf->thread0.kernel_start_pointer =
 147       brw_program_reloc(brw,
 148                         brw->sf.state_offset +
 149                         offsetof(struct brw_sf_unit_state, thread0),
 150                         brw->sf.prog_offset +
 151                         (sf->thread0.grf_reg_count << 1)) >> 6;
 152
 153    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 154
 155    sf->thread3.dispatch_grf_start_reg = 3;
 156    sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
 157
 158    /* BRW_NEW_SF_PROG_DATA */
 159    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 160
 161    /* BRW_NEW_URB_FENCE */
 162    sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
 163    sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
 164
 165    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
 166     * 48 (Ironlake) threads.
 167     */
 168    if (brw->gen == 5)
 169       chipset_max_threads = 48;
 170    else
 171       chipset_max_threads = 24;
 172
 173    /* BRW_NEW_URB_FENCE */
 174    sf->thread4.max_threads = MIN2(chipset_max_threads,
 175                                   brw->urb.nr_sf_entries) - 1;
 176
 177    /* BRW_NEW_SF_VP */
 178    sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
 179                                        brw->sf.vp_offset) >> 5; /* reloc */
 180
 181    sf->sf5.viewport_transform = 1;
 182
 183    /* _NEW_SCISSOR */
 184    if (ctx->Scissor.EnableFlags)
 185       sf->sf6.scissor = 1;
 186
 187    /* _NEW_POLYGON */
 188    if (ctx->Polygon._FrontBit)
 189       sf->sf5.front_winding = BRW_FRONTWINDING_CW;
 190    else
 191       sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
 192
 193    /* _NEW_BUFFERS
 194     * The viewport is inverted for rendering to a FBO, and that inverts
 195     * polygon front/back orientation.
 196     */
 197    sf->sf5.front_winding ^= render_to_fbo;
 198
 199    /* _NEW_POLYGON */
 200    switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
 201    case GL_FRONT:
 202       sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
 203       break;
 204    case GL_BACK:
 205       sf->sf6.cull_mode = BRW_CULLMODE_BACK;
 206       break;
 207    case GL_FRONT_AND_BACK:
 208       sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
 209       break;
 210    case GL_NONE:
 211       sf->sf6.cull_mode = BRW_CULLMODE_NONE;
 212       break;
 213    default:
 214       unreachable("not reached");
 215    }
 216
 217    /* _NEW_LINE */
 218    sf->sf6.line_width =
 219       CLAMP(ctx->Line.Width, 1.0f, ctx->Const.MaxLineWidth) * (1<<1);
 220
 221    sf->sf6.line_endcap_aa_region_width = 1;
 222    if (ctx->Line.SmoothFlag)
 223       sf->sf6.aa_enable = 1;
 224    else if (sf->sf6.line_width <= 0x2)
 225        sf->sf6.line_width = 0;
 226
 227    /* _NEW_BUFFERS */
 228    if (!render_to_fbo) {
 229       /* Rendering to an OpenGL window */
 230       sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 231    }
 232    else {
 233       /* If rendering to an FBO, the pixel coordinate system is
 234        * inverted with respect to the normal OpenGL coordinate
 235        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 236        * But this value is listed as "Reserved, but not seen as useful"
 237        * in Intel documentation (page 212, "Point Rasterization Rule",
 238        * section 7.4 "SF Pipeline State Summary", of document
 239        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 240        * Chipset Graphics Controller Programmer's Reference Manual,
 241        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 242        * available at
 243        *     https://01.org/linuxgraphics/documentation/hardware-specification-prms
 244        * at the time of this writing).
 245        *
 246        * It does work on at least some devices, if not all;
 247        * if devices that don't support it can be identified,
 248        * the likely failure case is that points are rasterized
 249        * incorrectly, which is no worse than occurs without
 250        * the value, so we're using it here.
 251        */
 252       sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 253    }
 254    /* XXX clamp max depends on AA vs. non-AA */
 255
 256    /* _NEW_POINT */
 257    sf->sf7.sprite_point = ctx->Point.PointSprite;
 258    sf->sf7.point_size = CLAMP(rintf(CLAMP(ctx->Point.Size,
 259                                           ctx->Point.MinSize,
 260                                           ctx->Point.MaxSize)), 1.0f, 255.0f) *
 261                         (1<<3);
 262    /* _NEW_PROGRAM | _NEW_POINT */
 263    sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
 264                                     ctx->Point._Attenuated);
 265    sf->sf7.aa_line_distance_mode = brw->is_g4x || brw->gen == 5;
 266
 267    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 268     * _NEW_LIGHT
 269     */
 270    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 271       sf->sf7.trifan_pv = 2;
 272       sf->sf7.linestrip_pv = 1;
 273       sf->sf7.tristrip_pv = 2;
 274    } else {
 275       sf->sf7.trifan_pv = 1;
 276       sf->sf7.linestrip_pv = 0;
 277       sf->sf7.tristrip_pv = 0;
 278    }
 279    sf->sf7.line_last_pixel_enable = 0;
 280
 281    /* Set bias for OpenGL rasterization rules:
 282     */
 283    sf->sf6.dest_org_vbias = 0x8;
 284    sf->sf6.dest_org_hbias = 0x8;
 285
 286    /* STATE_PREFETCH command description describes this state as being
 287     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 288     */
 289
 290    /* Emit SF viewport relocation */
 291    brw_emit_reloc(&brw->batch,
 292                   brw->sf.state_offset +
 293                   offsetof(struct brw_sf_unit_state, sf5),
 294                   brw->batch.bo,
 295                   brw->sf.vp_offset | sf->sf5.front_winding |
 296                   (sf->sf5.viewport_transform << 1),
 297                   I915_GEM_DOMAIN_INSTRUCTION, 0);
 298
 299    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 300 }
 301
 302 const struct brw_tracked_state brw_sf_unit = {
 303    .dirty = {
 304       .mesa  = _NEW_BUFFERS |
 305                _NEW_LIGHT |
 306                _NEW_LINE |
 307                _NEW_POINT |
 308                _NEW_POLYGON |
 309                _NEW_PROGRAM |
 310                _NEW_SCISSOR,
 311       .brw   = BRW_NEW_BATCH |
 312                BRW_NEW_BLORP |
 313                BRW_NEW_PROGRAM_CACHE |
 314                BRW_NEW_SF_PROG_DATA |
 315                BRW_NEW_SF_VP |
 316                BRW_NEW_URB_FENCE,
 317    },
 318    .emit = upload_sf_unit,
 319 };