i965: Allow for variable-sized auxdata in the state cache.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "main/macros.h"
38 #include "intel_fbo.h"
39
40 static void upload_sf_vp(struct brw_context *brw)
41 {
42 GLcontext *ctx = &brw->intel.ctx;
43 const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
44 struct brw_sf_viewport sfv;
45 GLfloat y_scale, y_bias;
46 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
47 const GLfloat *v = ctx->Viewport._WindowMap.m;
48
49 memset(&sfv, 0, sizeof(sfv));
50
51 if (render_to_fbo) {
52 y_scale = 1.0;
53 y_bias = 0;
54 }
55 else {
56 y_scale = -1.0;
57 y_bias = ctx->DrawBuffer->Height;
58 }
59
60 /* _NEW_VIEWPORT */
61
62 sfv.viewport.m00 = v[MAT_SX];
63 sfv.viewport.m11 = v[MAT_SY] * y_scale;
64 sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
65 sfv.viewport.m30 = v[MAT_TX];
66 sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
67 sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
68
69 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
70 * for DrawBuffer->_[XY]{min,max}
71 */
72
73 /* The scissor only needs to handle the intersection of drawable and
74 * scissor rect. Clipping to the boundaries of static shared buffers
75 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
76 *
77 * Note that the hardware's coordinates are inclusive, while Mesa's min is
78 * inclusive but max is exclusive.
79 */
80 if (render_to_fbo) {
81 /* texmemory: Y=0=bottom */
82 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
83 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
84 sfv.scissor.ymin = ctx->DrawBuffer->_Ymin;
85 sfv.scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
86 }
87 else {
88 /* memory: Y=0=top */
89 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
90 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
91 sfv.scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
92 sfv.scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
93 }
94
95 dri_bo_unreference(brw->sf.vp_bo);
96 brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP, &sfv, sizeof(sfv),
97 NULL, 0);
98 }
99
100 const struct brw_tracked_state brw_sf_vp = {
101 .dirty = {
102 .mesa = (_NEW_VIEWPORT |
103 _NEW_SCISSOR |
104 _NEW_BUFFERS),
105 .brw = 0,
106 .cache = 0
107 },
108 .prepare = upload_sf_vp
109 };
110
111 struct brw_sf_unit_key {
112 unsigned int total_grf;
113 unsigned int urb_entry_read_length;
114
115 unsigned int nr_urb_entries, urb_size, sfsize;
116
117 GLenum front_face, cull_face;
118 unsigned pv_first:1;
119 unsigned scissor:1;
120 unsigned line_smooth:1;
121 unsigned point_sprite:1;
122 unsigned point_attenuated:1;
123 unsigned render_to_fbo:1;
124 float line_width;
125 float point_size;
126 };
127
128 static void
129 sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
130 {
131 GLcontext *ctx = &brw->intel.ctx;
132 memset(key, 0, sizeof(*key));
133
134 /* CACHE_NEW_SF_PROG */
135 key->total_grf = brw->sf.prog_data->total_grf;
136 key->urb_entry_read_length = brw->sf.prog_data->urb_read_length;
137
138 /* BRW_NEW_URB_FENCE */
139 key->nr_urb_entries = brw->urb.nr_sf_entries;
140 key->urb_size = brw->urb.vsize;
141 key->sfsize = brw->urb.sfsize;
142
143 key->scissor = ctx->Scissor.Enabled;
144 key->front_face = ctx->Polygon.FrontFace;
145
146 if (ctx->Polygon.CullFlag)
147 key->cull_face = ctx->Polygon.CullFaceMode;
148 else
149 key->cull_face = GL_NONE;
150
151 key->line_width = ctx->Line.Width;
152 key->line_smooth = ctx->Line.SmoothFlag;
153
154 key->point_sprite = ctx->Point.PointSprite;
155 key->point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
156 key->point_attenuated = ctx->Point._Attenuated;
157
158 /* _NEW_LIGHT */
159 key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
160
161 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
162 }
163
164 static dri_bo *
165 sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
166 dri_bo **reloc_bufs)
167 {
168 struct intel_context *intel = &brw->intel;
169 struct brw_sf_unit_state sf;
170 dri_bo *bo;
171 int chipset_max_threads;
172 memset(&sf, 0, sizeof(sf));
173
174 sf.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
175 sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
176
177 sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
178
179 sf.thread3.dispatch_grf_start_reg = 3;
180
181 if (intel->is_ironlake)
182 sf.thread3.urb_entry_read_offset = 3;
183 else
184 sf.thread3.urb_entry_read_offset = 1;
185
186 sf.thread3.urb_entry_read_length = key->urb_entry_read_length;
187
188 sf.thread4.nr_urb_entries = key->nr_urb_entries;
189 sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
190
191 /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
192 * 48 (Ironlake) threads.
193 */
194 if (intel->is_ironlake)
195 chipset_max_threads = 48;
196 else
197 chipset_max_threads = 24;
198
199 sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
200
201 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
202 sf.thread4.max_threads = 0;
203
204 if (INTEL_DEBUG & DEBUG_STATS)
205 sf.thread4.stats_enable = 1;
206
207 /* CACHE_NEW_SF_VP */
208 sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset >> 5; /* reloc */
209
210 sf.sf5.viewport_transform = 1;
211
212 /* _NEW_SCISSOR */
213 if (key->scissor)
214 sf.sf6.scissor = 1;
215
216 /* _NEW_POLYGON */
217 if (key->front_face == GL_CCW)
218 sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
219 else
220 sf.sf5.front_winding = BRW_FRONTWINDING_CW;
221
222 /* The viewport is inverted for rendering to a FBO, and that inverts
223 * polygon front/back orientation.
224 */
225 sf.sf5.front_winding ^= key->render_to_fbo;
226
227 switch (key->cull_face) {
228 case GL_FRONT:
229 sf.sf6.cull_mode = BRW_CULLMODE_FRONT;
230 break;
231 case GL_BACK:
232 sf.sf6.cull_mode = BRW_CULLMODE_BACK;
233 break;
234 case GL_FRONT_AND_BACK:
235 sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
236 break;
237 case GL_NONE:
238 sf.sf6.cull_mode = BRW_CULLMODE_NONE;
239 break;
240 default:
241 assert(0);
242 break;
243 }
244
245 /* _NEW_LINE */
246 /* XXX use ctx->Const.Min/MaxLineWidth here */
247 sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1);
248
249 sf.sf6.line_endcap_aa_region_width = 1;
250 if (key->line_smooth)
251 sf.sf6.aa_enable = 1;
252 else if (sf.sf6.line_width <= 0x2)
253 sf.sf6.line_width = 0;
254
255 /* _NEW_BUFFERS */
256 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
257 if (!key->render_to_fbo) {
258 /* Rendering to an OpenGL window */
259 sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
260 }
261 else {
262 /* If rendering to an FBO, the pixel coordinate system is
263 * inverted with respect to the normal OpenGL coordinate
264 * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
265 * But this value is listed as "Reserved, but not seen as useful"
266 * in Intel documentation (page 212, "Point Rasterization Rule",
267 * section 7.4 "SF Pipeline State Summary", of document
268 * "IntelĀ® 965 Express Chipset Family and IntelĀ® G35 Express
269 * Chipset Graphics Controller Programmer's Reference Manual,
270 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
271 * available at
272 * http://intellinuxgraphics.org/documentation.html
273 * at the time of this writing).
274 *
275 * It does work on at least some devices, if not all;
276 * if devices that don't support it can be identified,
277 * the likely failure case is that points are rasterized
278 * incorrectly, which is no worse than occurs without
279 * the value, so we're using it here.
280 */
281 sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
282 }
283 /* XXX clamp max depends on AA vs. non-AA */
284
285 /* _NEW_POINT */
286 sf.sf7.sprite_point = key->point_sprite;
287 sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
288 sf.sf7.use_point_size_state = !key->point_attenuated;
289 sf.sf7.aa_line_distance_mode = 0;
290
291 /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
292 */
293 if (!key->pv_first) {
294 sf.sf7.trifan_pv = 2;
295 sf.sf7.linestrip_pv = 1;
296 sf.sf7.tristrip_pv = 2;
297 } else {
298 sf.sf7.trifan_pv = 1;
299 sf.sf7.linestrip_pv = 0;
300 sf.sf7.tristrip_pv = 0;
301 }
302 sf.sf7.line_last_pixel_enable = 0;
303
304 /* Set bias for OpenGL rasterization rules:
305 */
306 sf.sf6.dest_org_vbias = 0x8;
307 sf.sf6.dest_org_hbias = 0x8;
308
309 bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
310 key, sizeof(*key),
311 reloc_bufs, 2,
312 &sf, sizeof(sf));
313
314 /* STATE_PREFETCH command description describes this state as being
315 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
316 */
317 /* Emit SF program relocation */
318 dri_bo_emit_reloc(bo,
319 I915_GEM_DOMAIN_INSTRUCTION, 0,
320 sf.thread0.grf_reg_count << 1,
321 offsetof(struct brw_sf_unit_state, thread0),
322 brw->sf.prog_bo);
323
324 /* Emit SF viewport relocation */
325 dri_bo_emit_reloc(bo,
326 I915_GEM_DOMAIN_INSTRUCTION, 0,
327 sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
328 offsetof(struct brw_sf_unit_state, sf5),
329 brw->sf.vp_bo);
330
331 return bo;
332 }
333
334 static void upload_sf_unit( struct brw_context *brw )
335 {
336 struct brw_sf_unit_key key;
337 dri_bo *reloc_bufs[2];
338
339 sf_unit_populate_key(brw, &key);
340
341 reloc_bufs[0] = brw->sf.prog_bo;
342 reloc_bufs[1] = brw->sf.vp_bo;
343
344 dri_bo_unreference(brw->sf.state_bo);
345 brw->sf.state_bo = brw_search_cache(&brw->cache, BRW_SF_UNIT,
346 &key, sizeof(key),
347 reloc_bufs, 2,
348 NULL);
349 if (brw->sf.state_bo == NULL) {
350 brw->sf.state_bo = sf_unit_create_from_key(brw, &key, reloc_bufs);
351 }
352 }
353
354 const struct brw_tracked_state brw_sf_unit = {
355 .dirty = {
356 .mesa = (_NEW_POLYGON |
357 _NEW_LIGHT |
358 _NEW_LINE |
359 _NEW_POINT |
360 _NEW_SCISSOR |
361 _NEW_BUFFERS),
362 .brw = BRW_NEW_URB_FENCE,
363 .cache = (CACHE_NEW_SF_VP |
364 CACHE_NEW_SF_PROG)
365 },
366 .prepare = upload_sf_unit,
367 };