src/mesa/drivers/dri/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 static void upload_sf_vp(struct brw_context *brw)
  40 {
  41    struct intel_context *intel = &brw->intel;
  42    struct gl_context *ctx = &intel->ctx;
  43    const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
  44    struct brw_sf_viewport *sfv;
  45    GLfloat y_scale, y_bias;
  46    const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
  47    const GLfloat *v = ctx->Viewport._WindowMap.m;
  48
  49    sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
  50                          sizeof(*sfv), 32, &brw->sf.vp_offset);
  51    memset(sfv, 0, sizeof(*sfv));
  52
  53    if (render_to_fbo) {
  54       y_scale = 1.0;
  55       y_bias = 0;
  56    }
  57    else {
  58       y_scale = -1.0;
  59       y_bias = ctx->DrawBuffer->Height;
  60    }
  61
  62    /* _NEW_VIEWPORT */
  63
  64    sfv->viewport.m00 = v[MAT_SX];
  65    sfv->viewport.m11 = v[MAT_SY] * y_scale;
  66    sfv->viewport.m22 = v[MAT_SZ] * depth_scale;
  67    sfv->viewport.m30 = v[MAT_TX];
  68    sfv->viewport.m31 = v[MAT_TY] * y_scale + y_bias;
  69    sfv->viewport.m32 = v[MAT_TZ] * depth_scale;
  70
  71    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
  72     * for DrawBuffer->_[XY]{min,max}
  73     */
  74
  75    /* The scissor only needs to handle the intersection of drawable
  76     * and scissor rect, since there are no longer cliprects for shared
  77     * buffers with DRI2.
  78     *
  79     * Note that the hardware's coordinates are inclusive, while Mesa's min is
  80     * inclusive but max is exclusive.
  81     */
  82
  83    if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
  84        ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
  85       /* If the scissor was out of bounds and got clamped to 0
  86        * width/height at the bounds, the subtraction of 1 from
  87        * maximums could produce a negative number and thus not clip
  88        * anything.  Instead, just provide a min > max scissor inside
  89        * the bounds, which produces the expected no rendering.
  90        */
  91       sfv->scissor.xmin = 1;
  92       sfv->scissor.xmax = 0;
  93       sfv->scissor.ymin = 1;
  94       sfv->scissor.ymax = 0;
  95    } else if (render_to_fbo) {
  96       /* texmemory: Y=0=bottom */
  97       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
  98       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
  99       sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
 100       sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
 101    }
 102    else {
 103       /* memory: Y=0=top */
 104       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 105       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 106       sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
 107       sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
 108    }
 109
 110    brw->state.dirty.cache |= CACHE_NEW_SF_VP;
 111 }
 112
 113 const struct brw_tracked_state brw_sf_vp = {
 114    .dirty = {
 115       .mesa  = (_NEW_VIEWPORT |
 116                 _NEW_SCISSOR |
 117                 _NEW_BUFFERS),
 118       .brw   = BRW_NEW_BATCH,
 119       .cache = 0
 120    },
 121    .prepare = upload_sf_vp
 122 };
 123
 124 static void upload_sf_unit( struct brw_context *brw )
 125 {
 126    struct intel_context *intel = &brw->intel;
 127    struct gl_context *ctx = &intel->ctx;
 128    struct brw_sf_unit_state *sf;
 129    drm_intel_bo *bo = intel->batch.bo;
 130    int chipset_max_threads;
 131    bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
 132
 133    sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
 134                         sizeof(*sf), 64, &brw->sf.state_offset);
 135
 136    memset(sf, 0, sizeof(*sf));
 137
 138    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
 139    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
 140    sf->thread0.kernel_start_pointer =
 141       brw_program_reloc(brw,
 142                         brw->sf.state_offset +
 143                         offsetof(struct brw_sf_unit_state, thread0),
 144                         brw->sf.prog_offset +
 145                         (sf->thread0.grf_reg_count << 1)) >> 6;
 146
 147    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 148
 149    sf->thread3.dispatch_grf_start_reg = 3;
 150
 151    if (intel->gen == 5)
 152        sf->thread3.urb_entry_read_offset = 3;
 153    else
 154        sf->thread3.urb_entry_read_offset = 1;
 155
 156    /* CACHE_NEW_SF_PROG */
 157    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 158
 159    /* BRW_NEW_URB_FENCE */
 160    sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
 161    sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
 162
 163    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
 164     * 48 (Ironlake) threads.
 165     */
 166    if (intel->gen == 5)
 167       chipset_max_threads = 48;
 168    else
 169       chipset_max_threads = 24;
 170
 171    /* BRW_NEW_URB_FENCE */
 172    sf->thread4.max_threads = MIN2(chipset_max_threads,
 173                                   brw->urb.nr_sf_entries) - 1;
 174
 175    if (unlikely(INTEL_DEBUG & DEBUG_SINGLE_THREAD))
 176       sf->thread4.max_threads = 0;
 177
 178    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 179       sf->thread4.stats_enable = 1;
 180
 181    /* CACHE_NEW_SF_VP */
 182    sf->sf5.sf_viewport_state_offset = (intel->batch.bo->offset +
 183                                        brw->sf.vp_offset) >> 5; /* reloc */
 184
 185    sf->sf5.viewport_transform = 1;
 186
 187    /* _NEW_SCISSOR */
 188    if (ctx->Scissor.Enabled)
 189       sf->sf6.scissor = 1;
 190
 191    /* _NEW_POLYGON */
 192    if (ctx->Polygon.FrontFace == GL_CCW)
 193       sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
 194    else
 195       sf->sf5.front_winding = BRW_FRONTWINDING_CW;
 196
 197    /* _NEW_BUFFERS
 198     * The viewport is inverted for rendering to a FBO, and that inverts
 199     * polygon front/back orientation.
 200     */
 201    sf->sf5.front_winding ^= render_to_fbo;
 202
 203    /* _NEW_POLYGON */
 204    switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
 205    case GL_FRONT:
 206       sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
 207       break;
 208    case GL_BACK:
 209       sf->sf6.cull_mode = BRW_CULLMODE_BACK;
 210       break;
 211    case GL_FRONT_AND_BACK:
 212       sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
 213       break;
 214    case GL_NONE:
 215       sf->sf6.cull_mode = BRW_CULLMODE_NONE;
 216       break;
 217    default:
 218       assert(0);
 219       break;
 220    }
 221
 222    /* _NEW_LINE */
 223    /* XXX use ctx->Const.Min/MaxLineWidth here */
 224    sf->sf6.line_width = CLAMP(ctx->Line.Width, 1.0, 5.0) * (1<<1);
 225
 226    sf->sf6.line_endcap_aa_region_width = 1;
 227    if (ctx->Line.SmoothFlag)
 228       sf->sf6.aa_enable = 1;
 229    else if (sf->sf6.line_width <= 0x2)
 230        sf->sf6.line_width = 0;
 231
 232    /* _NEW_BUFFERS */
 233    if (!render_to_fbo) {
 234       /* Rendering to an OpenGL window */
 235       sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 236    }
 237    else {
 238       /* If rendering to an FBO, the pixel coordinate system is
 239        * inverted with respect to the normal OpenGL coordinate
 240        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 241        * But this value is listed as "Reserved, but not seen as useful"
 242        * in Intel documentation (page 212, "Point Rasterization Rule",
 243        * section 7.4 "SF Pipeline State Summary", of document
 244        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 245        * Chipset Graphics Controller Programmer's Reference Manual,
 246        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 247        * available at
 248        *     http://intellinuxgraphics.org/documentation.html
 249        * at the time of this writing).
 250        *
 251        * It does work on at least some devices, if not all;
 252        * if devices that don't support it can be identified,
 253        * the likely failure case is that points are rasterized
 254        * incorrectly, which is no worse than occurs without
 255        * the value, so we're using it here.
 256        */
 257       sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 258    }
 259    /* XXX clamp max depends on AA vs. non-AA */
 260
 261    /* _NEW_POINT */
 262    sf->sf7.sprite_point = ctx->Point.PointSprite;
 263    sf->sf7.point_size = CLAMP(rint(CLAMP(ctx->Point.Size,
 264                                          ctx->Point.MinSize,
 265                                          ctx->Point.MaxSize)), 1, 255) * (1<<3);
 266    sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
 267                                     ctx->Point._Attenuated);
 268    sf->sf7.aa_line_distance_mode = 0;
 269
 270    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 271     * _NEW_LIGHT
 272     */
 273    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 274       sf->sf7.trifan_pv = 2;
 275       sf->sf7.linestrip_pv = 1;
 276       sf->sf7.tristrip_pv = 2;
 277    } else {
 278       sf->sf7.trifan_pv = 1;
 279       sf->sf7.linestrip_pv = 0;
 280       sf->sf7.tristrip_pv = 0;
 281    }
 282    sf->sf7.line_last_pixel_enable = 0;
 283
 284    /* Set bias for OpenGL rasterization rules:
 285     */
 286    sf->sf6.dest_org_vbias = 0x8;
 287    sf->sf6.dest_org_hbias = 0x8;
 288
 289    /* STATE_PREFETCH command description describes this state as being
 290     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 291     */
 292
 293    /* Emit SF viewport relocation */
 294    drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
 295                                 offsetof(struct brw_sf_unit_state, sf5)),
 296                            intel->batch.bo, (brw->sf.vp_offset |
 297                                              sf->sf5.front_winding |
 298                                              (sf->sf5.viewport_transform << 1)),
 299                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 300
 301    brw->state.dirty.cache |= CACHE_NEW_SF_UNIT;
 302 }
 303
 304 const struct brw_tracked_state brw_sf_unit = {
 305    .dirty = {
 306       .mesa  = (_NEW_POLYGON |
 307                 _NEW_LIGHT |
 308                 _NEW_LINE |
 309                 _NEW_POINT |
 310                 _NEW_SCISSOR |
 311                 _NEW_BUFFERS),
 312       .brw   = (BRW_NEW_BATCH |
 313                 BRW_NEW_PROGRAM_CACHE |
 314                 BRW_NEW_URB_FENCE),
 315       .cache = (CACHE_NEW_SF_VP |
 316                 CACHE_NEW_SF_PROG)
 317    },
 318    .prepare = upload_sf_unit,
 319 };