2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "main/macros.h"
39 static void upload_sf_vp(struct brw_context
*brw
)
41 GLcontext
*ctx
= &brw
->intel
.ctx
;
42 const GLfloat depth_scale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
43 struct brw_sf_viewport sfv
;
44 GLfloat y_scale
, y_bias
;
45 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
46 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
48 memset(&sfv
, 0, sizeof(sfv
));
56 y_bias
= ctx
->DrawBuffer
->Height
;
61 sfv
.viewport
.m00
= v
[MAT_SX
];
62 sfv
.viewport
.m11
= v
[MAT_SY
] * y_scale
;
63 sfv
.viewport
.m22
= v
[MAT_SZ
] * depth_scale
;
64 sfv
.viewport
.m30
= v
[MAT_TX
];
65 sfv
.viewport
.m31
= v
[MAT_TY
] * y_scale
+ y_bias
;
66 sfv
.viewport
.m32
= v
[MAT_TZ
] * depth_scale
;
68 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
69 * for DrawBuffer->_[XY]{min,max}
72 /* The scissor only needs to handle the intersection of drawable
73 * and scissor rect, since there are no longer cliprects for shared
76 * Note that the hardware's coordinates are inclusive, while Mesa's min is
77 * inclusive but max is exclusive.
80 if (ctx
->DrawBuffer
->_Xmin
== ctx
->DrawBuffer
->_Xmax
||
81 ctx
->DrawBuffer
->_Ymin
== ctx
->DrawBuffer
->_Ymax
) {
82 /* If the scissor was out of bounds and got clamped to 0
83 * width/height at the bounds, the subtraction of 1 from
84 * maximums could produce a negative number and thus not clip
85 * anything. Instead, just provide a min > max scissor inside
86 * the bounds, which produces the expected no rendering.
92 } else if (render_to_fbo
) {
93 /* texmemory: Y=0=bottom */
94 sfv
.scissor
.xmin
= ctx
->DrawBuffer
->_Xmin
;
95 sfv
.scissor
.xmax
= ctx
->DrawBuffer
->_Xmax
- 1;
96 sfv
.scissor
.ymin
= ctx
->DrawBuffer
->_Ymin
;
97 sfv
.scissor
.ymax
= ctx
->DrawBuffer
->_Ymax
- 1;
100 /* memory: Y=0=top */
101 sfv
.scissor
.xmin
= ctx
->DrawBuffer
->_Xmin
;
102 sfv
.scissor
.xmax
= ctx
->DrawBuffer
->_Xmax
- 1;
103 sfv
.scissor
.ymin
= ctx
->DrawBuffer
->Height
- ctx
->DrawBuffer
->_Ymax
;
104 sfv
.scissor
.ymax
= ctx
->DrawBuffer
->Height
- ctx
->DrawBuffer
->_Ymin
- 1;
107 drm_intel_bo_unreference(brw
->sf
.vp_bo
);
108 brw
->sf
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_SF_VP
, &sfv
, sizeof(sfv
));
111 const struct brw_tracked_state brw_sf_vp
= {
113 .mesa
= (_NEW_VIEWPORT
|
119 .prepare
= upload_sf_vp
122 struct brw_sf_unit_key
{
123 unsigned int total_grf
;
124 unsigned int urb_entry_read_length
;
126 unsigned int nr_urb_entries
, urb_size
, sfsize
;
128 GLenum front_face
, cull_face
;
131 unsigned line_smooth
:1;
132 unsigned point_sprite
:1;
133 unsigned point_attenuated
:1;
134 unsigned render_to_fbo
:1;
140 sf_unit_populate_key(struct brw_context
*brw
, struct brw_sf_unit_key
*key
)
142 GLcontext
*ctx
= &brw
->intel
.ctx
;
143 memset(key
, 0, sizeof(*key
));
145 /* CACHE_NEW_SF_PROG */
146 key
->total_grf
= brw
->sf
.prog_data
->total_grf
;
147 key
->urb_entry_read_length
= brw
->sf
.prog_data
->urb_read_length
;
149 /* BRW_NEW_URB_FENCE */
150 key
->nr_urb_entries
= brw
->urb
.nr_sf_entries
;
151 key
->urb_size
= brw
->urb
.vsize
;
152 key
->sfsize
= brw
->urb
.sfsize
;
154 key
->scissor
= ctx
->Scissor
.Enabled
;
155 key
->front_face
= ctx
->Polygon
.FrontFace
;
157 if (ctx
->Polygon
.CullFlag
)
158 key
->cull_face
= ctx
->Polygon
.CullFaceMode
;
160 key
->cull_face
= GL_NONE
;
162 key
->line_width
= ctx
->Line
.Width
;
163 key
->line_smooth
= ctx
->Line
.SmoothFlag
;
165 key
->point_sprite
= ctx
->Point
.PointSprite
;
166 key
->point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
167 key
->point_attenuated
= ctx
->Point
._Attenuated
;
170 key
->pv_first
= (ctx
->Light
.ProvokingVertex
== GL_FIRST_VERTEX_CONVENTION
);
172 key
->render_to_fbo
= brw
->intel
.ctx
.DrawBuffer
->Name
!= 0;
175 static drm_intel_bo
*
176 sf_unit_create_from_key(struct brw_context
*brw
, struct brw_sf_unit_key
*key
,
177 drm_intel_bo
**reloc_bufs
)
179 struct intel_context
*intel
= &brw
->intel
;
180 struct brw_sf_unit_state sf
;
182 int chipset_max_threads
;
183 memset(&sf
, 0, sizeof(sf
));
185 sf
.thread0
.grf_reg_count
= ALIGN(key
->total_grf
, 16) / 16 - 1;
186 sf
.thread0
.kernel_start_pointer
= brw
->sf
.prog_bo
->offset
>> 6; /* reloc */
188 sf
.thread1
.floating_point_mode
= BRW_FLOATING_POINT_NON_IEEE_754
;
190 sf
.thread3
.dispatch_grf_start_reg
= 3;
193 sf
.thread3
.urb_entry_read_offset
= 3;
195 sf
.thread3
.urb_entry_read_offset
= 1;
197 sf
.thread3
.urb_entry_read_length
= key
->urb_entry_read_length
;
199 sf
.thread4
.nr_urb_entries
= key
->nr_urb_entries
;
200 sf
.thread4
.urb_entry_allocation_size
= key
->sfsize
- 1;
202 /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
203 * 48 (Ironlake) threads.
206 chipset_max_threads
= 48;
208 chipset_max_threads
= 24;
210 sf
.thread4
.max_threads
= MIN2(chipset_max_threads
, key
->nr_urb_entries
) - 1;
212 if (INTEL_DEBUG
& DEBUG_SINGLE_THREAD
)
213 sf
.thread4
.max_threads
= 0;
215 if (INTEL_DEBUG
& DEBUG_STATS
)
216 sf
.thread4
.stats_enable
= 1;
218 /* CACHE_NEW_SF_VP */
219 sf
.sf5
.sf_viewport_state_offset
= brw
->sf
.vp_bo
->offset
>> 5; /* reloc */
221 sf
.sf5
.viewport_transform
= 1;
228 if (key
->front_face
== GL_CCW
)
229 sf
.sf5
.front_winding
= BRW_FRONTWINDING_CCW
;
231 sf
.sf5
.front_winding
= BRW_FRONTWINDING_CW
;
233 /* The viewport is inverted for rendering to a FBO, and that inverts
234 * polygon front/back orientation.
236 sf
.sf5
.front_winding
^= key
->render_to_fbo
;
238 switch (key
->cull_face
) {
240 sf
.sf6
.cull_mode
= BRW_CULLMODE_FRONT
;
243 sf
.sf6
.cull_mode
= BRW_CULLMODE_BACK
;
245 case GL_FRONT_AND_BACK
:
246 sf
.sf6
.cull_mode
= BRW_CULLMODE_BOTH
;
249 sf
.sf6
.cull_mode
= BRW_CULLMODE_NONE
;
257 /* XXX use ctx->Const.Min/MaxLineWidth here */
258 sf
.sf6
.line_width
= CLAMP(key
->line_width
, 1.0, 5.0) * (1<<1);
260 sf
.sf6
.line_endcap_aa_region_width
= 1;
261 if (key
->line_smooth
)
262 sf
.sf6
.aa_enable
= 1;
263 else if (sf
.sf6
.line_width
<= 0x2)
264 sf
.sf6
.line_width
= 0;
267 key
->render_to_fbo
= brw
->intel
.ctx
.DrawBuffer
->Name
!= 0;
268 if (!key
->render_to_fbo
) {
269 /* Rendering to an OpenGL window */
270 sf
.sf6
.point_rast_rule
= BRW_RASTRULE_UPPER_RIGHT
;
273 /* If rendering to an FBO, the pixel coordinate system is
274 * inverted with respect to the normal OpenGL coordinate
275 * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
276 * But this value is listed as "Reserved, but not seen as useful"
277 * in Intel documentation (page 212, "Point Rasterization Rule",
278 * section 7.4 "SF Pipeline State Summary", of document
279 * "IntelĀ® 965 Express Chipset Family and IntelĀ® G35 Express
280 * Chipset Graphics Controller Programmer's Reference Manual,
281 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
283 * http://intellinuxgraphics.org/documentation.html
284 * at the time of this writing).
286 * It does work on at least some devices, if not all;
287 * if devices that don't support it can be identified,
288 * the likely failure case is that points are rasterized
289 * incorrectly, which is no worse than occurs without
290 * the value, so we're using it here.
292 sf
.sf6
.point_rast_rule
= BRW_RASTRULE_LOWER_RIGHT
;
294 /* XXX clamp max depends on AA vs. non-AA */
297 sf
.sf7
.sprite_point
= key
->point_sprite
;
298 sf
.sf7
.point_size
= CLAMP(rint(key
->point_size
), 1, 255) * (1<<3);
299 sf
.sf7
.use_point_size_state
= !key
->point_attenuated
;
300 sf
.sf7
.aa_line_distance_mode
= 0;
302 /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
304 if (!key
->pv_first
) {
305 sf
.sf7
.trifan_pv
= 2;
306 sf
.sf7
.linestrip_pv
= 1;
307 sf
.sf7
.tristrip_pv
= 2;
309 sf
.sf7
.trifan_pv
= 1;
310 sf
.sf7
.linestrip_pv
= 0;
311 sf
.sf7
.tristrip_pv
= 0;
313 sf
.sf7
.line_last_pixel_enable
= 0;
315 /* Set bias for OpenGL rasterization rules:
317 sf
.sf6
.dest_org_vbias
= 0x8;
318 sf
.sf6
.dest_org_hbias
= 0x8;
320 bo
= brw_upload_cache(&brw
->cache
, BRW_SF_UNIT
,
325 /* STATE_PREFETCH command description describes this state as being
326 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
328 /* Emit SF program relocation */
329 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_sf_unit_state
, thread0
),
330 brw
->sf
.prog_bo
, sf
.thread0
.grf_reg_count
<< 1,
331 I915_GEM_DOMAIN_INSTRUCTION
, 0);
333 /* Emit SF viewport relocation */
334 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_sf_unit_state
, sf5
),
335 brw
->sf
.vp_bo
, (sf
.sf5
.front_winding
|
336 (sf
.sf5
.viewport_transform
<< 1)),
337 I915_GEM_DOMAIN_INSTRUCTION
, 0);
342 static void upload_sf_unit( struct brw_context
*brw
)
344 struct brw_sf_unit_key key
;
345 drm_intel_bo
*reloc_bufs
[2];
347 sf_unit_populate_key(brw
, &key
);
349 reloc_bufs
[0] = brw
->sf
.prog_bo
;
350 reloc_bufs
[1] = brw
->sf
.vp_bo
;
352 drm_intel_bo_unreference(brw
->sf
.state_bo
);
353 brw
->sf
.state_bo
= brw_search_cache(&brw
->cache
, BRW_SF_UNIT
,
357 if (brw
->sf
.state_bo
== NULL
) {
358 brw
->sf
.state_bo
= sf_unit_create_from_key(brw
, &key
, reloc_bufs
);
362 const struct brw_tracked_state brw_sf_unit
= {
364 .mesa
= (_NEW_POLYGON
|
370 .brw
= BRW_NEW_URB_FENCE
,
371 .cache
= (CACHE_NEW_SF_VP
|
374 .prepare
= upload_sf_unit
,