Merge branch 'master' of git+ssh://agd5f@git.freedesktop.org/git/mesa/mesa into r6xx...
[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "main/macros.h"
38 #include "intel_fbo.h"
39
40 static void upload_sf_vp(struct brw_context *brw)
41 {
42 GLcontext *ctx = &brw->intel.ctx;
43 const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
44 struct brw_sf_viewport sfv;
45 GLfloat y_scale, y_bias;
46 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
47 const GLfloat *v = ctx->Viewport._WindowMap.m;
48
49 memset(&sfv, 0, sizeof(sfv));
50
51 if (render_to_fbo) {
52 y_scale = 1.0;
53 y_bias = 0;
54 }
55 else {
56 y_scale = -1.0;
57 y_bias = ctx->DrawBuffer->Height;
58 }
59
60 /* _NEW_VIEWPORT */
61
62 sfv.viewport.m00 = v[MAT_SX];
63 sfv.viewport.m11 = v[MAT_SY] * y_scale;
64 sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
65 sfv.viewport.m30 = v[MAT_TX];
66 sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
67 sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
68
69 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
70 * for DrawBuffer->_[XY]{min,max}
71 */
72
73 /* The scissor only needs to handle the intersection of drawable and
74 * scissor rect. Clipping to the boundaries of static shared buffers
75 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
76 *
77 * Note that the hardware's coordinates are inclusive, while Mesa's min is
78 * inclusive but max is exclusive.
79 */
80 if (render_to_fbo) {
81 /* texmemory: Y=0=bottom */
82 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
83 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
84 sfv.scissor.ymin = ctx->DrawBuffer->_Ymin;
85 sfv.scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
86 }
87 else {
88 /* memory: Y=0=top */
89 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
90 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
91 sfv.scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
92 sfv.scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
93 }
94
95 dri_bo_unreference(brw->sf.vp_bo);
96 brw->sf.vp_bo = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0 );
97 }
98
99 const struct brw_tracked_state brw_sf_vp = {
100 .dirty = {
101 .mesa = (_NEW_VIEWPORT |
102 _NEW_SCISSOR |
103 _NEW_BUFFERS),
104 .brw = 0,
105 .cache = 0
106 },
107 .prepare = upload_sf_vp
108 };
109
110 struct brw_sf_unit_key {
111 unsigned int total_grf;
112 unsigned int urb_entry_read_length;
113
114 unsigned int nr_urb_entries, urb_size, sfsize;
115
116 GLenum front_face, cull_face;
117 unsigned scissor:1;
118 unsigned line_smooth:1;
119 unsigned point_sprite:1;
120 unsigned point_attenuated:1;
121 unsigned render_to_fbo:1;
122 float line_width;
123 float point_size;
124 };
125
126 static void
127 sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
128 {
129 GLcontext *ctx = &brw->intel.ctx;
130 memset(key, 0, sizeof(*key));
131
132 /* CACHE_NEW_SF_PROG */
133 key->total_grf = brw->sf.prog_data->total_grf;
134 key->urb_entry_read_length = brw->sf.prog_data->urb_read_length;
135
136 /* BRW_NEW_URB_FENCE */
137 key->nr_urb_entries = brw->urb.nr_sf_entries;
138 key->urb_size = brw->urb.vsize;
139 key->sfsize = brw->urb.sfsize;
140
141 key->scissor = ctx->Scissor.Enabled;
142 key->front_face = ctx->Polygon.FrontFace;
143
144 if (ctx->Polygon.CullFlag)
145 key->cull_face = ctx->Polygon.CullFaceMode;
146 else
147 key->cull_face = GL_NONE;
148
149 key->line_width = ctx->Line.Width;
150 key->line_smooth = ctx->Line.SmoothFlag;
151
152 key->point_sprite = ctx->Point.PointSprite;
153 key->point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
154 key->point_attenuated = ctx->Point._Attenuated;
155
156 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
157 }
158
159 static dri_bo *
160 sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
161 dri_bo **reloc_bufs)
162 {
163 struct brw_sf_unit_state sf;
164 dri_bo *bo;
165 int chipset_max_threads;
166 memset(&sf, 0, sizeof(sf));
167
168 sf.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
169 sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
170
171 sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
172
173 sf.thread3.dispatch_grf_start_reg = 3;
174
175 if (BRW_IS_IGDNG(brw))
176 sf.thread3.urb_entry_read_offset = 3;
177 else
178 sf.thread3.urb_entry_read_offset = 1;
179
180 sf.thread3.urb_entry_read_length = key->urb_entry_read_length;
181
182 sf.thread4.nr_urb_entries = key->nr_urb_entries;
183 sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
184
185 /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or
186 * 48(IGDNG) threads
187 */
188 if (BRW_IS_IGDNG(brw))
189 chipset_max_threads = 48;
190 else
191 chipset_max_threads = 24;
192
193 sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
194
195 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
196 sf.thread4.max_threads = 0;
197
198 if (INTEL_DEBUG & DEBUG_STATS)
199 sf.thread4.stats_enable = 1;
200
201 /* CACHE_NEW_SF_VP */
202 sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset >> 5; /* reloc */
203
204 sf.sf5.viewport_transform = 1;
205
206 /* _NEW_SCISSOR */
207 if (key->scissor)
208 sf.sf6.scissor = 1;
209
210 /* _NEW_POLYGON */
211 if (key->front_face == GL_CCW)
212 sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
213 else
214 sf.sf5.front_winding = BRW_FRONTWINDING_CW;
215
216 /* The viewport is inverted for rendering to a FBO, and that inverts
217 * polygon front/back orientation.
218 */
219 sf.sf5.front_winding ^= key->render_to_fbo;
220
221 switch (key->cull_face) {
222 case GL_FRONT:
223 sf.sf6.cull_mode = BRW_CULLMODE_FRONT;
224 break;
225 case GL_BACK:
226 sf.sf6.cull_mode = BRW_CULLMODE_BACK;
227 break;
228 case GL_FRONT_AND_BACK:
229 sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
230 break;
231 case GL_NONE:
232 sf.sf6.cull_mode = BRW_CULLMODE_NONE;
233 break;
234 default:
235 assert(0);
236 break;
237 }
238
239 /* _NEW_LINE */
240 /* XXX use ctx->Const.Min/MaxLineWidth here */
241 sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1);
242
243 sf.sf6.line_endcap_aa_region_width = 1;
244 if (key->line_smooth)
245 sf.sf6.aa_enable = 1;
246 else if (sf.sf6.line_width <= 0x2)
247 sf.sf6.line_width = 0;
248
249 /* _NEW_BUFFERS */
250 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
251 if (!key->render_to_fbo) {
252 /* Rendering to an OpenGL window */
253 sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
254 }
255 else {
256 /* If rendering to an FBO, the pixel coordinate system is
257 * inverted with respect to the normal OpenGL coordinate
258 * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
259 * But this value is listed as "Reserved, but not seen as useful"
260 * in Intel documentation (page 212, "Point Rasterization Rule",
261 * section 7.4 "SF Pipeline State Summary", of document
262 * "IntelĀ® 965 Express Chipset Family and IntelĀ® G35 Express
263 * Chipset Graphics Controller Programmer's Reference Manual,
264 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
265 * available at
266 * http://intellinuxgraphics.org/documentation.html
267 * at the time of this writing).
268 *
269 * It does work on at least some devices, if not all;
270 * if devices that don't support it can be identified,
271 * the likely failure case is that points are rasterized
272 * incorrectly, which is no worse than occurs without
273 * the value, so we're using it here.
274 */
275 sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
276 }
277 /* XXX clamp max depends on AA vs. non-AA */
278
279 /* _NEW_POINT */
280 sf.sf7.sprite_point = key->point_sprite;
281 sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
282 sf.sf7.use_point_size_state = !key->point_attenuated;
283 sf.sf7.aa_line_distance_mode = 0;
284
285 /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
286 */
287 sf.sf7.trifan_pv = 2;
288 sf.sf7.linestrip_pv = 1;
289 sf.sf7.tristrip_pv = 2;
290 sf.sf7.line_last_pixel_enable = 0;
291
292 /* Set bias for OpenGL rasterization rules:
293 */
294 sf.sf6.dest_org_vbias = 0x8;
295 sf.sf6.dest_org_hbias = 0x8;
296
297 bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
298 key, sizeof(*key),
299 reloc_bufs, 2,
300 &sf, sizeof(sf),
301 NULL, NULL);
302
303 /* Emit SF program relocation */
304 dri_bo_emit_reloc(bo,
305 I915_GEM_DOMAIN_INSTRUCTION, 0,
306 sf.thread0.grf_reg_count << 1,
307 offsetof(struct brw_sf_unit_state, thread0),
308 brw->sf.prog_bo);
309
310 /* Emit SF viewport relocation */
311 dri_bo_emit_reloc(bo,
312 I915_GEM_DOMAIN_INSTRUCTION, 0,
313 sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
314 offsetof(struct brw_sf_unit_state, sf5),
315 brw->sf.vp_bo);
316
317 return bo;
318 }
319
320 static void upload_sf_unit( struct brw_context *brw )
321 {
322 struct brw_sf_unit_key key;
323 dri_bo *reloc_bufs[2];
324
325 sf_unit_populate_key(brw, &key);
326
327 reloc_bufs[0] = brw->sf.prog_bo;
328 reloc_bufs[1] = brw->sf.vp_bo;
329
330 dri_bo_unreference(brw->sf.state_bo);
331 brw->sf.state_bo = brw_search_cache(&brw->cache, BRW_SF_UNIT,
332 &key, sizeof(key),
333 reloc_bufs, 2,
334 NULL);
335 if (brw->sf.state_bo == NULL) {
336 brw->sf.state_bo = sf_unit_create_from_key(brw, &key, reloc_bufs);
337 }
338 }
339
340 const struct brw_tracked_state brw_sf_unit = {
341 .dirty = {
342 .mesa = (_NEW_POLYGON |
343 _NEW_LINE |
344 _NEW_POINT |
345 _NEW_SCISSOR |
346 _NEW_BUFFERS),
347 .brw = BRW_NEW_URB_FENCE,
348 .cache = (CACHE_NEW_SF_VP |
349 CACHE_NEW_SF_PROG)
350 },
351 .prepare = upload_sf_unit,
352 };