src/mesa/drivers/dri/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "main/mtypes.h"
  35 #include "main/macros.h"
  36 #include "main/fbobject.h"
  37 #include "main/viewport.h"
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41 #include "brw_sf.h"
  42
  43 static void upload_sf_vp(struct brw_context *brw)
  44 {
  45    struct gl_context *ctx = &brw->ctx;
  46    struct brw_sf_viewport *sfv;
  47    GLfloat y_scale, y_bias;
  48    float scale[3], translate[3];
  49    const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
  50
  51    sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
  52    memset(sfv, 0, sizeof(*sfv));
  53
  54    /* Accessing the fields Width and Height of gl_framebuffer to produce the
  55     * values to program the viewport and scissor is fine as long as the
  56     * gl_framebuffer has atleast one attachment.
  57     */
  58    assert(ctx->DrawBuffer->_HasAttachments);
  59
  60    if (render_to_fbo) {
  61       y_scale = 1.0;
  62       y_bias = 0;
  63    }
  64    else {
  65       y_scale = -1.0;
  66       y_bias = ctx->DrawBuffer->Height;
  67    }
  68
  69    /* _NEW_VIEWPORT */
  70
  71    _mesa_get_viewport_xform(ctx, 0, scale, translate);
  72    sfv->viewport.m00 = scale[0];
  73    sfv->viewport.m11 = scale[1] * y_scale;
  74    sfv->viewport.m22 = scale[2];
  75    sfv->viewport.m30 = translate[0];
  76    sfv->viewport.m31 = translate[1] * y_scale + y_bias;
  77    sfv->viewport.m32 = translate[2];
  78
  79    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
  80     * for DrawBuffer->_[XY]{min,max}
  81     */
  82
  83    /* The scissor only needs to handle the intersection of drawable
  84     * and scissor rect, since there are no longer cliprects for shared
  85     * buffers with DRI2.
  86     *
  87     * Note that the hardware's coordinates are inclusive, while Mesa's min is
  88     * inclusive but max is exclusive.
  89     */
  90
  91    if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
  92        ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
  93       /* If the scissor was out of bounds and got clamped to 0
  94        * width/height at the bounds, the subtraction of 1 from
  95        * maximums could produce a negative number and thus not clip
  96        * anything.  Instead, just provide a min > max scissor inside
  97        * the bounds, which produces the expected no rendering.
  98        */
  99       sfv->scissor.xmin = 1;
 100       sfv->scissor.xmax = 0;
 101       sfv->scissor.ymin = 1;
 102       sfv->scissor.ymax = 0;
 103    } else if (render_to_fbo) {
 104       /* texmemory: Y=0=bottom */
 105       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 106       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 107       sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
 108       sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
 109    }
 110    else {
 111       /* memory: Y=0=top */
 112       sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
 113       sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
 114       sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
 115       sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
 116    }
 117
 118    brw->ctx.NewDriverState |= BRW_NEW_SF_VP;
 119 }
 120
 121 const struct brw_tracked_state brw_sf_vp = {
 122    .dirty = {
 123       .mesa  = _NEW_BUFFERS |
 124                _NEW_SCISSOR |
 125                _NEW_VIEWPORT,
 126       .brw   = BRW_NEW_BATCH |
 127                BRW_NEW_BLORP,
 128    },
 129    .emit = upload_sf_vp
 130 };
 131
 132 static void upload_sf_unit( struct brw_context *brw )
 133 {
 134    struct gl_context *ctx = &brw->ctx;
 135    struct brw_sf_unit_state *sf;
 136    drm_bacon_bo *bo = brw->batch.bo;
 137    int chipset_max_threads;
 138    bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 139
 140    sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
 141
 142    memset(sf, 0, sizeof(*sf));
 143
 144    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_SF_PROG_DATA */
 145    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
 146    sf->thread0.kernel_start_pointer =
 147       brw_program_reloc(brw,
 148                         brw->sf.state_offset +
 149                         offsetof(struct brw_sf_unit_state, thread0),
 150                         brw->sf.prog_offset +
 151                         (sf->thread0.grf_reg_count << 1)) >> 6;
 152
 153    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 154
 155    sf->thread3.dispatch_grf_start_reg = 3;
 156    sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
 157
 158    /* BRW_NEW_SF_PROG_DATA */
 159    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 160
 161    /* BRW_NEW_URB_FENCE */
 162    sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
 163    sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
 164
 165    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
 166     * 48 (Ironlake) threads.
 167     */
 168    if (brw->gen == 5)
 169       chipset_max_threads = 48;
 170    else
 171       chipset_max_threads = 24;
 172
 173    /* BRW_NEW_URB_FENCE */
 174    sf->thread4.max_threads = MIN2(chipset_max_threads,
 175                                   brw->urb.nr_sf_entries) - 1;
 176
 177    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 178       sf->thread4.stats_enable = 1;
 179
 180    /* BRW_NEW_SF_VP */
 181    sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
 182                                        brw->sf.vp_offset) >> 5; /* reloc */
 183
 184    sf->sf5.viewport_transform = 1;
 185
 186    /* _NEW_SCISSOR */
 187    if (ctx->Scissor.EnableFlags)
 188       sf->sf6.scissor = 1;
 189
 190    /* _NEW_POLYGON */
 191    if (ctx->Polygon._FrontBit)
 192       sf->sf5.front_winding = BRW_FRONTWINDING_CW;
 193    else
 194       sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
 195
 196    /* _NEW_BUFFERS
 197     * The viewport is inverted for rendering to a FBO, and that inverts
 198     * polygon front/back orientation.
 199     */
 200    sf->sf5.front_winding ^= render_to_fbo;
 201
 202    /* _NEW_POLYGON */
 203    switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
 204    case GL_FRONT:
 205       sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
 206       break;
 207    case GL_BACK:
 208       sf->sf6.cull_mode = BRW_CULLMODE_BACK;
 209       break;
 210    case GL_FRONT_AND_BACK:
 211       sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
 212       break;
 213    case GL_NONE:
 214       sf->sf6.cull_mode = BRW_CULLMODE_NONE;
 215       break;
 216    default:
 217       unreachable("not reached");
 218    }
 219
 220    /* _NEW_LINE */
 221    sf->sf6.line_width =
 222       CLAMP(ctx->Line.Width, 1.0f, ctx->Const.MaxLineWidth) * (1<<1);
 223
 224    sf->sf6.line_endcap_aa_region_width = 1;
 225    if (ctx->Line.SmoothFlag)
 226       sf->sf6.aa_enable = 1;
 227    else if (sf->sf6.line_width <= 0x2)
 228        sf->sf6.line_width = 0;
 229
 230    /* _NEW_BUFFERS */
 231    if (!render_to_fbo) {
 232       /* Rendering to an OpenGL window */
 233       sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 234    }
 235    else {
 236       /* If rendering to an FBO, the pixel coordinate system is
 237        * inverted with respect to the normal OpenGL coordinate
 238        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 239        * But this value is listed as "Reserved, but not seen as useful"
 240        * in Intel documentation (page 212, "Point Rasterization Rule",
 241        * section 7.4 "SF Pipeline State Summary", of document
 242        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 243        * Chipset Graphics Controller Programmer's Reference Manual,
 244        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 245        * available at
 246        *     https://01.org/linuxgraphics/documentation/hardware-specification-prms
 247        * at the time of this writing).
 248        *
 249        * It does work on at least some devices, if not all;
 250        * if devices that don't support it can be identified,
 251        * the likely failure case is that points are rasterized
 252        * incorrectly, which is no worse than occurs without
 253        * the value, so we're using it here.
 254        */
 255       sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 256    }
 257    /* XXX clamp max depends on AA vs. non-AA */
 258
 259    /* _NEW_POINT */
 260    sf->sf7.sprite_point = ctx->Point.PointSprite;
 261    sf->sf7.point_size = CLAMP(rintf(CLAMP(ctx->Point.Size,
 262                                           ctx->Point.MinSize,
 263                                           ctx->Point.MaxSize)), 1.0f, 255.0f) *
 264                         (1<<3);
 265    /* _NEW_PROGRAM | _NEW_POINT */
 266    sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
 267                                     ctx->Point._Attenuated);
 268    sf->sf7.aa_line_distance_mode = 0;
 269
 270    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 271     * _NEW_LIGHT
 272     */
 273    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 274       sf->sf7.trifan_pv = 2;
 275       sf->sf7.linestrip_pv = 1;
 276       sf->sf7.tristrip_pv = 2;
 277    } else {
 278       sf->sf7.trifan_pv = 1;
 279       sf->sf7.linestrip_pv = 0;
 280       sf->sf7.tristrip_pv = 0;
 281    }
 282    sf->sf7.line_last_pixel_enable = 0;
 283
 284    /* Set bias for OpenGL rasterization rules:
 285     */
 286    sf->sf6.dest_org_vbias = 0x8;
 287    sf->sf6.dest_org_hbias = 0x8;
 288
 289    /* STATE_PREFETCH command description describes this state as being
 290     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 291     */
 292
 293    /* Emit SF viewport relocation */
 294    drm_bacon_bo_emit_reloc(bo, (brw->sf.state_offset +
 295                                 offsetof(struct brw_sf_unit_state, sf5)),
 296                            brw->batch.bo, (brw->sf.vp_offset |
 297                                              sf->sf5.front_winding |
 298                                              (sf->sf5.viewport_transform << 1)),
 299                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 300
 301    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 302 }
 303
 304 const struct brw_tracked_state brw_sf_unit = {
 305    .dirty = {
 306       .mesa  = _NEW_BUFFERS |
 307                _NEW_LIGHT |
 308                _NEW_LINE |
 309                _NEW_POINT |
 310                _NEW_POLYGON |
 311                _NEW_PROGRAM |
 312                _NEW_SCISSOR,
 313       .brw   = BRW_NEW_BATCH |
 314                BRW_NEW_BLORP |
 315                BRW_NEW_PROGRAM_CACHE |
 316                BRW_NEW_SF_PROG_DATA |
 317                BRW_NEW_SF_VP |
 318                BRW_NEW_URB_FENCE,
 319    },
 320    .emit = upload_sf_unit,
 321 };