src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 struct brw_compiler *
  36 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  37 {
  38    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  39
  40    compiler->devinfo = devinfo;
  41
  42    brw_fs_alloc_reg_sets(compiler);
  43    brw_vec4_alloc_reg_set(compiler);
  44
  45    return compiler;
  46 }
  47
  48 struct gl_shader *
  49 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  50 {
  51    struct brw_shader *shader;
  52
  53    shader = rzalloc(NULL, struct brw_shader);
  54    if (shader) {
  55       shader->base.Type = type;
  56       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  57       shader->base.Name = name;
  58       _mesa_init_shader(ctx, &shader->base);
  59    }
  60
  61    return &shader->base;
  62 }
  63
  64 /**
  65  * Performs a compile of the shader stages even when we don't know
  66  * what non-orthogonal state will be set, in the hope that it reflects
  67  * the eventual NOS used, and thus allows us to produce link failures.
  68  */
  69 static bool
  70 brw_shader_precompile(struct gl_context *ctx,
  71                       struct gl_shader_program *sh_prog)
  72 {
  73    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  74    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  75    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  76
  77    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  78       return false;
  79
  80    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  81       return false;
  82
  83    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  84       return false;
  85
  86    return true;
  87 }
  88
  89 static inline bool
  90 is_scalar_shader_stage(struct brw_context *brw, int stage)
  91 {
  92    switch (stage) {
  93    case MESA_SHADER_FRAGMENT:
  94       return true;
  95    case MESA_SHADER_VERTEX:
  96       return brw->scalar_vs;
  97    default:
  98       return false;
  99    }
 100 }
 101
 102 static void
 103 brw_lower_packing_builtins(struct brw_context *brw,
 104                            gl_shader_stage shader_type,
 105                            exec_list *ir)
 106 {
 107    int ops = LOWER_PACK_SNORM_2x16
 108            | LOWER_UNPACK_SNORM_2x16
 109            | LOWER_PACK_UNORM_2x16
 110            | LOWER_UNPACK_UNORM_2x16;
 111
 112    if (is_scalar_shader_stage(brw, shader_type)) {
 113       ops |= LOWER_UNPACK_UNORM_4x8
 114            | LOWER_UNPACK_SNORM_4x8
 115            | LOWER_PACK_UNORM_4x8
 116            | LOWER_PACK_SNORM_4x8;
 117    }
 118
 119    if (brw->gen >= 7) {
 120       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 121        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 122        * lowering is needed. For SOA code, the Half2x16 ops must be
 123        * scalarized.
 124        */
 125       if (is_scalar_shader_stage(brw, shader_type)) {
 126          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 127              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 128       }
 129    } else {
 130       ops |= LOWER_PACK_HALF_2x16
 131           |  LOWER_UNPACK_HALF_2x16;
 132    }
 133
 134    lower_packing_builtins(ir, ops);
 135 }
 136
 137 static void
 138 process_glsl_ir(struct brw_context *brw,
 139                 struct gl_shader_program *shader_prog,
 140                 struct gl_shader *shader)
 141 {
 142    struct gl_context *ctx = &brw->ctx;
 143    const struct gl_shader_compiler_options *options =
 144       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 145
 146    /* Temporary memory context for any new IR. */
 147    void *mem_ctx = ralloc_context(NULL);
 148
 149    ralloc_adopt(mem_ctx, shader->ir);
 150
 151    /* lower_packing_builtins() inserts arithmetic instructions, so it
 152     * must precede lower_instructions().
 153     */
 154    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 155    do_mat_op_to_vec(shader->ir);
 156    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 157    lower_instructions(shader->ir,
 158                       MOD_TO_FLOOR |
 159                       DIV_TO_MUL_RCP |
 160                       SUB_TO_ADD_NEG |
 161                       EXP_TO_EXP2 |
 162                       LOG_TO_LOG2 |
 163                       bitfield_insert |
 164                       LDEXP_TO_ARITH);
 165
 166    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 167     * if-statements need to be flattened.
 168     */
 169    if (brw->gen < 6)
 170       lower_if_to_cond_assign(shader->ir, 16);
 171
 172    do_lower_texture_projection(shader->ir);
 173    brw_lower_texture_gradients(brw, shader->ir);
 174    do_vec_index_to_cond_assign(shader->ir);
 175    lower_vector_insert(shader->ir, true);
 176    if (options->NirOptions == NULL)
 177       brw_do_cubemap_normalize(shader->ir);
 178    lower_offset_arrays(shader->ir);
 179    brw_do_lower_unnormalized_offset(shader->ir);
 180    lower_noise(shader->ir);
 181    lower_quadop_vector(shader->ir, false);
 182
 183    bool lowered_variable_indexing =
 184       lower_variable_index_to_cond_assign(shader->ir,
 185                                           options->EmitNoIndirectInput,
 186                                           options->EmitNoIndirectOutput,
 187                                           options->EmitNoIndirectTemp,
 188                                           options->EmitNoIndirectUniform);
 189
 190    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 191       perf_debug("Unsupported form of variable indexing in FS; falling "
 192                  "back to very inefficient code generation\n");
 193    }
 194
 195    lower_ubo_reference(shader, shader->ir);
 196
 197    bool progress;
 198    do {
 199       progress = false;
 200
 201       if (is_scalar_shader_stage(brw, shader->Stage)) {
 202          brw_do_channel_expressions(shader->ir);
 203          brw_do_vector_splitting(shader->ir);
 204       }
 205
 206       progress = do_lower_jumps(shader->ir, true, true,
 207                                 true, /* main return */
 208                                 false, /* continue */
 209                                 false /* loops */
 210                                 ) || progress;
 211
 212       progress = do_common_optimization(shader->ir, true, true,
 213                                         options, ctx->Const.NativeIntegers) || progress;
 214    } while (progress);
 215
 216    if (options->NirOptions != NULL)
 217       lower_output_reads(shader->ir);
 218
 219    validate_ir_tree(shader->ir);
 220
 221    /* Now that we've finished altering the linked IR, reparent any live IR back
 222     * to the permanent memory context, and free the temporary one (discarding any
 223     * junk we optimized away).
 224     */
 225    reparent_ir(shader->ir, shader->ir);
 226    ralloc_free(mem_ctx);
 227
 228    if (ctx->_Shader->Flags & GLSL_DUMP) {
 229       fprintf(stderr, "\n");
 230       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 231               _mesa_shader_stage_to_string(shader->Stage),
 232               shader_prog->Name);
 233       _mesa_print_ir(stderr, shader->ir, NULL);
 234       fprintf(stderr, "\n");
 235    }
 236 }
 237
 238 GLboolean
 239 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 240 {
 241    struct brw_context *brw = brw_context(ctx);
 242    unsigned int stage;
 243
 244    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 245       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 246       const struct gl_shader_compiler_options *options =
 247          &ctx->Const.ShaderCompilerOptions[stage];
 248
 249       if (!shader)
 250          continue;
 251
 252       struct gl_program *prog =
 253          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 254                                 shader->Name);
 255       if (!prog)
 256         return false;
 257       prog->Parameters = _mesa_new_parameter_list();
 258
 259       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 260
 261       process_glsl_ir(brw, shProg, shader);
 262
 263       /* Make a pass over the IR to add state references for any built-in
 264        * uniforms that are used.  This has to be done now (during linking).
 265        * Code generation doesn't happen until the first time this shader is
 266        * used for rendering.  Waiting until then to generate the parameters is
 267        * too late.  At that point, the values for the built-in uniforms won't
 268        * get sent to the shader.
 269        */
 270       foreach_in_list(ir_instruction, node, shader->ir) {
 271          ir_variable *var = node->as_variable();
 272
 273          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 274              || (strncmp(var->name, "gl_", 3) != 0))
 275             continue;
 276
 277          const ir_state_slot *const slots = var->get_state_slots();
 278          assert(slots != NULL);
 279
 280          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 281             _mesa_add_state_reference(prog->Parameters,
 282                                       (gl_state_index *) slots[i].tokens);
 283          }
 284       }
 285
 286       do_set_program_inouts(shader->ir, prog, shader->Stage);
 287
 288       prog->SamplersUsed = shader->active_samplers;
 289       prog->ShadowSamplers = shader->shadow_samplers;
 290       _mesa_update_shader_textures_used(shProg, prog);
 291
 292       _mesa_reference_program(ctx, &shader->Program, prog);
 293
 294       brw_add_texrect_params(prog);
 295
 296       if (options->NirOptions)
 297          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 298
 299       _mesa_reference_program(ctx, &prog, NULL);
 300    }
 301
 302    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 303       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 304          const struct gl_shader *sh = shProg->Shaders[i];
 305          if (!sh)
 306             continue;
 307
 308          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 309                  _mesa_shader_stage_to_string(sh->Stage),
 310                  i, shProg->Name);
 311          fprintf(stderr, "%s", sh->Source);
 312          fprintf(stderr, "\n");
 313       }
 314    }
 315
 316    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 317       return false;
 318
 319    return true;
 320 }
 321
 322
 323 enum brw_reg_type
 324 brw_type_for_base_type(const struct glsl_type *type)
 325 {
 326    switch (type->base_type) {
 327    case GLSL_TYPE_FLOAT:
 328       return BRW_REGISTER_TYPE_F;
 329    case GLSL_TYPE_INT:
 330    case GLSL_TYPE_BOOL:
 331       return BRW_REGISTER_TYPE_D;
 332    case GLSL_TYPE_UINT:
 333       return BRW_REGISTER_TYPE_UD;
 334    case GLSL_TYPE_ARRAY:
 335       return brw_type_for_base_type(type->fields.array);
 336    case GLSL_TYPE_STRUCT:
 337    case GLSL_TYPE_SAMPLER:
 338    case GLSL_TYPE_ATOMIC_UINT:
 339       /* These should be overridden with the type of the member when
 340        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 341        * way to trip up if we don't.
 342        */
 343       return BRW_REGISTER_TYPE_UD;
 344    case GLSL_TYPE_IMAGE:
 345       return BRW_REGISTER_TYPE_UD;
 346    case GLSL_TYPE_VOID:
 347    case GLSL_TYPE_ERROR:
 348    case GLSL_TYPE_INTERFACE:
 349    case GLSL_TYPE_DOUBLE:
 350       unreachable("not reached");
 351    }
 352
 353    return BRW_REGISTER_TYPE_F;
 354 }
 355
 356 enum brw_conditional_mod
 357 brw_conditional_for_comparison(unsigned int op)
 358 {
 359    switch (op) {
 360    case ir_binop_less:
 361       return BRW_CONDITIONAL_L;
 362    case ir_binop_greater:
 363       return BRW_CONDITIONAL_G;
 364    case ir_binop_lequal:
 365       return BRW_CONDITIONAL_LE;
 366    case ir_binop_gequal:
 367       return BRW_CONDITIONAL_GE;
 368    case ir_binop_equal:
 369    case ir_binop_all_equal: /* same as equal for scalars */
 370       return BRW_CONDITIONAL_Z;
 371    case ir_binop_nequal:
 372    case ir_binop_any_nequal: /* same as nequal for scalars */
 373       return BRW_CONDITIONAL_NZ;
 374    default:
 375       unreachable("not reached: bad operation for comparison");
 376    }
 377 }
 378
 379 uint32_t
 380 brw_math_function(enum opcode op)
 381 {
 382    switch (op) {
 383    case SHADER_OPCODE_RCP:
 384       return BRW_MATH_FUNCTION_INV;
 385    case SHADER_OPCODE_RSQ:
 386       return BRW_MATH_FUNCTION_RSQ;
 387    case SHADER_OPCODE_SQRT:
 388       return BRW_MATH_FUNCTION_SQRT;
 389    case SHADER_OPCODE_EXP2:
 390       return BRW_MATH_FUNCTION_EXP;
 391    case SHADER_OPCODE_LOG2:
 392       return BRW_MATH_FUNCTION_LOG;
 393    case SHADER_OPCODE_POW:
 394       return BRW_MATH_FUNCTION_POW;
 395    case SHADER_OPCODE_SIN:
 396       return BRW_MATH_FUNCTION_SIN;
 397    case SHADER_OPCODE_COS:
 398       return BRW_MATH_FUNCTION_COS;
 399    case SHADER_OPCODE_INT_QUOTIENT:
 400       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 401    case SHADER_OPCODE_INT_REMAINDER:
 402       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 403    default:
 404       unreachable("not reached: unknown math function");
 405    }
 406 }
 407
 408 uint32_t
 409 brw_texture_offset(int *offsets, unsigned num_components)
 410 {
 411    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 412
 413    /* Combine all three offsets into a single unsigned dword:
 414     *
 415     *    bits 11:8 - U Offset (X component)
 416     *    bits  7:4 - V Offset (Y component)
 417     *    bits  3:0 - R Offset (Z component)
 418     */
 419    unsigned offset_bits = 0;
 420    for (unsigned i = 0; i < num_components; i++) {
 421       const unsigned shift = 4 * (2 - i);
 422       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 423    }
 424    return offset_bits;
 425 }
 426
 427 const char *
 428 brw_instruction_name(enum opcode op)
 429 {
 430    switch (op) {
 431    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 432       assert(opcode_descs[op].name);
 433       return opcode_descs[op].name;
 434    case FS_OPCODE_FB_WRITE:
 435       return "fb_write";
 436    case FS_OPCODE_BLORP_FB_WRITE:
 437       return "blorp_fb_write";
 438    case FS_OPCODE_REP_FB_WRITE:
 439       return "rep_fb_write";
 440
 441    case SHADER_OPCODE_RCP:
 442       return "rcp";
 443    case SHADER_OPCODE_RSQ:
 444       return "rsq";
 445    case SHADER_OPCODE_SQRT:
 446       return "sqrt";
 447    case SHADER_OPCODE_EXP2:
 448       return "exp2";
 449    case SHADER_OPCODE_LOG2:
 450       return "log2";
 451    case SHADER_OPCODE_POW:
 452       return "pow";
 453    case SHADER_OPCODE_INT_QUOTIENT:
 454       return "int_quot";
 455    case SHADER_OPCODE_INT_REMAINDER:
 456       return "int_rem";
 457    case SHADER_OPCODE_SIN:
 458       return "sin";
 459    case SHADER_OPCODE_COS:
 460       return "cos";
 461
 462    case SHADER_OPCODE_TEX:
 463       return "tex";
 464    case SHADER_OPCODE_TXD:
 465       return "txd";
 466    case SHADER_OPCODE_TXF:
 467       return "txf";
 468    case SHADER_OPCODE_TXL:
 469       return "txl";
 470    case SHADER_OPCODE_TXS:
 471       return "txs";
 472    case FS_OPCODE_TXB:
 473       return "txb";
 474    case SHADER_OPCODE_TXF_CMS:
 475       return "txf_cms";
 476    case SHADER_OPCODE_TXF_UMS:
 477       return "txf_ums";
 478    case SHADER_OPCODE_TXF_MCS:
 479       return "txf_mcs";
 480    case SHADER_OPCODE_LOD:
 481       return "lod";
 482    case SHADER_OPCODE_TG4:
 483       return "tg4";
 484    case SHADER_OPCODE_TG4_OFFSET:
 485       return "tg4_offset";
 486    case SHADER_OPCODE_SHADER_TIME_ADD:
 487       return "shader_time_add";
 488
 489    case SHADER_OPCODE_UNTYPED_ATOMIC:
 490       return "untyped_atomic";
 491    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 492       return "untyped_surface_read";
 493
 494    case SHADER_OPCODE_LOAD_PAYLOAD:
 495       return "load_payload";
 496
 497    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 498       return "gen4_scratch_read";
 499    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 500       return "gen4_scratch_write";
 501    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 502       return "gen7_scratch_read";
 503    case SHADER_OPCODE_URB_WRITE_SIMD8:
 504       return "gen8_urb_write_simd8";
 505
 506    case VEC4_OPCODE_MOV_BYTES:
 507       return "mov_bytes";
 508    case VEC4_OPCODE_PACK_BYTES:
 509       return "pack_bytes";
 510    case VEC4_OPCODE_UNPACK_UNIFORM:
 511       return "unpack_uniform";
 512
 513    case FS_OPCODE_DDX_COARSE:
 514       return "ddx_coarse";
 515    case FS_OPCODE_DDX_FINE:
 516       return "ddx_fine";
 517    case FS_OPCODE_DDY_COARSE:
 518       return "ddy_coarse";
 519    case FS_OPCODE_DDY_FINE:
 520       return "ddy_fine";
 521
 522    case FS_OPCODE_CINTERP:
 523       return "cinterp";
 524    case FS_OPCODE_LINTERP:
 525       return "linterp";
 526
 527    case FS_OPCODE_PIXEL_X:
 528       return "pixel_x";
 529    case FS_OPCODE_PIXEL_Y:
 530       return "pixel_y";
 531
 532    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 533       return "uniform_pull_const";
 534    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 535       return "uniform_pull_const_gen7";
 536    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 537       return "varying_pull_const";
 538    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 539       return "varying_pull_const_gen7";
 540
 541    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 542       return "mov_dispatch_to_flags";
 543    case FS_OPCODE_DISCARD_JUMP:
 544       return "discard_jump";
 545
 546    case FS_OPCODE_SET_OMASK:
 547       return "set_omask";
 548    case FS_OPCODE_SET_SAMPLE_ID:
 549       return "set_sample_id";
 550    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 551       return "set_simd4x2_offset";
 552
 553    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 554       return "pack_half_2x16_split";
 555    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 556       return "unpack_half_2x16_split_x";
 557    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 558       return "unpack_half_2x16_split_y";
 559
 560    case FS_OPCODE_PLACEHOLDER_HALT:
 561       return "placeholder_halt";
 562
 563    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 564       return "interp_centroid";
 565    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 566       return "interp_sample";
 567    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 568       return "interp_shared_offset";
 569    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 570       return "interp_per_slot_offset";
 571
 572    case VS_OPCODE_URB_WRITE:
 573       return "vs_urb_write";
 574    case VS_OPCODE_PULL_CONSTANT_LOAD:
 575       return "pull_constant_load";
 576    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 577       return "pull_constant_load_gen7";
 578
 579    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 580       return "set_simd4x2_header_gen9";
 581
 582    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 583       return "unpack_flags_simd4x2";
 584
 585    case GS_OPCODE_URB_WRITE:
 586       return "gs_urb_write";
 587    case GS_OPCODE_URB_WRITE_ALLOCATE:
 588       return "gs_urb_write_allocate";
 589    case GS_OPCODE_THREAD_END:
 590       return "gs_thread_end";
 591    case GS_OPCODE_SET_WRITE_OFFSET:
 592       return "set_write_offset";
 593    case GS_OPCODE_SET_VERTEX_COUNT:
 594       return "set_vertex_count";
 595    case GS_OPCODE_SET_DWORD_2:
 596       return "set_dword_2";
 597    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 598       return "prepare_channel_masks";
 599    case GS_OPCODE_SET_CHANNEL_MASKS:
 600       return "set_channel_masks";
 601    case GS_OPCODE_GET_INSTANCE_ID:
 602       return "get_instance_id";
 603    case GS_OPCODE_FF_SYNC:
 604       return "ff_sync";
 605    case GS_OPCODE_SET_PRIMITIVE_ID:
 606       return "set_primitive_id";
 607    case GS_OPCODE_SVB_WRITE:
 608       return "gs_svb_write";
 609    case GS_OPCODE_SVB_SET_DST_INDEX:
 610       return "gs_svb_set_dst_index";
 611    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 612       return "gs_ff_sync_set_primitives";
 613    }
 614
 615    unreachable("not reached");
 616 }
 617
 618 bool
 619 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 620 {
 621    union {
 622       unsigned ud;
 623       int d;
 624       float f;
 625    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 626
 627    switch (type) {
 628    case BRW_REGISTER_TYPE_UD:
 629    case BRW_REGISTER_TYPE_D:
 630    case BRW_REGISTER_TYPE_UQ:
 631    case BRW_REGISTER_TYPE_Q:
 632       /* Nothing to do. */
 633       return false;
 634    case BRW_REGISTER_TYPE_UW:
 635       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 636       break;
 637    case BRW_REGISTER_TYPE_W:
 638       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 639       break;
 640    case BRW_REGISTER_TYPE_F:
 641       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 642       break;
 643    case BRW_REGISTER_TYPE_UB:
 644    case BRW_REGISTER_TYPE_B:
 645       unreachable("no UB/B immediates");
 646    case BRW_REGISTER_TYPE_V:
 647    case BRW_REGISTER_TYPE_UV:
 648    case BRW_REGISTER_TYPE_VF:
 649       unreachable("unimplemented: saturate vector immediate");
 650    case BRW_REGISTER_TYPE_DF:
 651    case BRW_REGISTER_TYPE_HF:
 652       unreachable("unimplemented: saturate DF/HF immediate");
 653    }
 654
 655    if (imm.ud != sat_imm.ud) {
 656       reg->dw1.ud = sat_imm.ud;
 657       return true;
 658    }
 659    return false;
 660 }
 661
 662 bool
 663 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 664 {
 665    switch (type) {
 666    case BRW_REGISTER_TYPE_D:
 667    case BRW_REGISTER_TYPE_UD:
 668       reg->dw1.d = -reg->dw1.d;
 669       return true;
 670    case BRW_REGISTER_TYPE_W:
 671    case BRW_REGISTER_TYPE_UW:
 672       reg->dw1.d = -(int16_t)reg->dw1.ud;
 673       return true;
 674    case BRW_REGISTER_TYPE_F:
 675       reg->dw1.f = -reg->dw1.f;
 676       return true;
 677    case BRW_REGISTER_TYPE_VF:
 678       reg->dw1.ud ^= 0x80808080;
 679       return true;
 680    case BRW_REGISTER_TYPE_UB:
 681    case BRW_REGISTER_TYPE_B:
 682       unreachable("no UB/B immediates");
 683    case BRW_REGISTER_TYPE_UV:
 684    case BRW_REGISTER_TYPE_V:
 685       assert(!"unimplemented: negate UV/V immediate");
 686    case BRW_REGISTER_TYPE_UQ:
 687    case BRW_REGISTER_TYPE_Q:
 688       assert(!"unimplemented: negate UQ/Q immediate");
 689    case BRW_REGISTER_TYPE_DF:
 690    case BRW_REGISTER_TYPE_HF:
 691       assert(!"unimplemented: negate DF/HF immediate");
 692    }
 693
 694    return false;
 695 }
 696
 697 bool
 698 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 699 {
 700    switch (type) {
 701    case BRW_REGISTER_TYPE_D:
 702       reg->dw1.d = abs(reg->dw1.d);
 703       return true;
 704    case BRW_REGISTER_TYPE_W:
 705       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 706       return true;
 707    case BRW_REGISTER_TYPE_F:
 708       reg->dw1.f = fabsf(reg->dw1.f);
 709       return true;
 710    case BRW_REGISTER_TYPE_VF:
 711       reg->dw1.ud &= ~0x80808080;
 712       return true;
 713    case BRW_REGISTER_TYPE_UB:
 714    case BRW_REGISTER_TYPE_B:
 715       unreachable("no UB/B immediates");
 716    case BRW_REGISTER_TYPE_UQ:
 717    case BRW_REGISTER_TYPE_UD:
 718    case BRW_REGISTER_TYPE_UW:
 719    case BRW_REGISTER_TYPE_UV:
 720       /* Presumably the absolute value modifier on an unsigned source is a
 721        * nop, but it would be nice to confirm.
 722        */
 723       assert(!"unimplemented: abs unsigned immediate");
 724    case BRW_REGISTER_TYPE_V:
 725       assert(!"unimplemented: abs V immediate");
 726    case BRW_REGISTER_TYPE_Q:
 727       assert(!"unimplemented: abs Q immediate");
 728    case BRW_REGISTER_TYPE_DF:
 729    case BRW_REGISTER_TYPE_HF:
 730       assert(!"unimplemented: abs DF/HF immediate");
 731    }
 732
 733    return false;
 734 }
 735
 736 backend_visitor::backend_visitor(struct brw_context *brw,
 737                                  struct gl_shader_program *shader_prog,
 738                                  struct gl_program *prog,
 739                                  struct brw_stage_prog_data *stage_prog_data,
 740                                  gl_shader_stage stage)
 741    : brw(brw),
 742      devinfo(brw->intelScreen->devinfo),
 743      ctx(&brw->ctx),
 744      shader(shader_prog ?
 745         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 746      shader_prog(shader_prog),
 747      prog(prog),
 748      stage_prog_data(stage_prog_data),
 749      cfg(NULL),
 750      stage(stage)
 751 {
 752    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 753    stage_name = _mesa_shader_stage_to_string(stage);
 754    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 755 }
 756
 757 bool
 758 backend_reg::is_zero() const
 759 {
 760    if (file != IMM)
 761       return false;
 762
 763    return fixed_hw_reg.dw1.d == 0;
 764 }
 765
 766 bool
 767 backend_reg::is_one() const
 768 {
 769    if (file != IMM)
 770       return false;
 771
 772    return type == BRW_REGISTER_TYPE_F
 773           ? fixed_hw_reg.dw1.f == 1.0
 774           : fixed_hw_reg.dw1.d == 1;
 775 }
 776
 777 bool
 778 backend_reg::is_negative_one() const
 779 {
 780    if (file != IMM)
 781       return false;
 782
 783    switch (type) {
 784    case BRW_REGISTER_TYPE_F:
 785       return fixed_hw_reg.dw1.f == -1.0;
 786    case BRW_REGISTER_TYPE_D:
 787       return fixed_hw_reg.dw1.d == -1;
 788    default:
 789       return false;
 790    }
 791 }
 792
 793 bool
 794 backend_reg::is_null() const
 795 {
 796    return file == HW_REG &&
 797           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 798           fixed_hw_reg.nr == BRW_ARF_NULL;
 799 }
 800
 801
 802 bool
 803 backend_reg::is_accumulator() const
 804 {
 805    return file == HW_REG &&
 806           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 807           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 808 }
 809
 810 bool
 811 backend_reg::in_range(const backend_reg &r, unsigned n) const
 812 {
 813    return (file == r.file &&
 814            reg == r.reg &&
 815            reg_offset >= r.reg_offset &&
 816            reg_offset < r.reg_offset + n);
 817 }
 818
 819 bool
 820 backend_instruction::is_commutative() const
 821 {
 822    switch (opcode) {
 823    case BRW_OPCODE_AND:
 824    case BRW_OPCODE_OR:
 825    case BRW_OPCODE_XOR:
 826    case BRW_OPCODE_ADD:
 827    case BRW_OPCODE_MUL:
 828       return true;
 829    case BRW_OPCODE_SEL:
 830       /* MIN and MAX are commutative. */
 831       if (conditional_mod == BRW_CONDITIONAL_GE ||
 832           conditional_mod == BRW_CONDITIONAL_L) {
 833          return true;
 834       }
 835       /* fallthrough */
 836    default:
 837       return false;
 838    }
 839 }
 840
 841 bool
 842 backend_instruction::is_3src() const
 843 {
 844    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 845 }
 846
 847 bool
 848 backend_instruction::is_tex() const
 849 {
 850    return (opcode == SHADER_OPCODE_TEX ||
 851            opcode == FS_OPCODE_TXB ||
 852            opcode == SHADER_OPCODE_TXD ||
 853            opcode == SHADER_OPCODE_TXF ||
 854            opcode == SHADER_OPCODE_TXF_CMS ||
 855            opcode == SHADER_OPCODE_TXF_UMS ||
 856            opcode == SHADER_OPCODE_TXF_MCS ||
 857            opcode == SHADER_OPCODE_TXL ||
 858            opcode == SHADER_OPCODE_TXS ||
 859            opcode == SHADER_OPCODE_LOD ||
 860            opcode == SHADER_OPCODE_TG4 ||
 861            opcode == SHADER_OPCODE_TG4_OFFSET);
 862 }
 863
 864 bool
 865 backend_instruction::is_math() const
 866 {
 867    return (opcode == SHADER_OPCODE_RCP ||
 868            opcode == SHADER_OPCODE_RSQ ||
 869            opcode == SHADER_OPCODE_SQRT ||
 870            opcode == SHADER_OPCODE_EXP2 ||
 871            opcode == SHADER_OPCODE_LOG2 ||
 872            opcode == SHADER_OPCODE_SIN ||
 873            opcode == SHADER_OPCODE_COS ||
 874            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 875            opcode == SHADER_OPCODE_INT_REMAINDER ||
 876            opcode == SHADER_OPCODE_POW);
 877 }
 878
 879 bool
 880 backend_instruction::is_control_flow() const
 881 {
 882    switch (opcode) {
 883    case BRW_OPCODE_DO:
 884    case BRW_OPCODE_WHILE:
 885    case BRW_OPCODE_IF:
 886    case BRW_OPCODE_ELSE:
 887    case BRW_OPCODE_ENDIF:
 888    case BRW_OPCODE_BREAK:
 889    case BRW_OPCODE_CONTINUE:
 890       return true;
 891    default:
 892       return false;
 893    }
 894 }
 895
 896 bool
 897 backend_instruction::can_do_source_mods() const
 898 {
 899    switch (opcode) {
 900    case BRW_OPCODE_ADDC:
 901    case BRW_OPCODE_BFE:
 902    case BRW_OPCODE_BFI1:
 903    case BRW_OPCODE_BFI2:
 904    case BRW_OPCODE_BFREV:
 905    case BRW_OPCODE_CBIT:
 906    case BRW_OPCODE_FBH:
 907    case BRW_OPCODE_FBL:
 908    case BRW_OPCODE_SUBB:
 909       return false;
 910    default:
 911       return true;
 912    }
 913 }
 914
 915 bool
 916 backend_instruction::can_do_saturate() const
 917 {
 918    switch (opcode) {
 919    case BRW_OPCODE_ADD:
 920    case BRW_OPCODE_ASR:
 921    case BRW_OPCODE_AVG:
 922    case BRW_OPCODE_DP2:
 923    case BRW_OPCODE_DP3:
 924    case BRW_OPCODE_DP4:
 925    case BRW_OPCODE_DPH:
 926    case BRW_OPCODE_F16TO32:
 927    case BRW_OPCODE_F32TO16:
 928    case BRW_OPCODE_LINE:
 929    case BRW_OPCODE_LRP:
 930    case BRW_OPCODE_MAC:
 931    case BRW_OPCODE_MACH:
 932    case BRW_OPCODE_MAD:
 933    case BRW_OPCODE_MATH:
 934    case BRW_OPCODE_MOV:
 935    case BRW_OPCODE_MUL:
 936    case BRW_OPCODE_PLN:
 937    case BRW_OPCODE_RNDD:
 938    case BRW_OPCODE_RNDE:
 939    case BRW_OPCODE_RNDU:
 940    case BRW_OPCODE_RNDZ:
 941    case BRW_OPCODE_SEL:
 942    case BRW_OPCODE_SHL:
 943    case BRW_OPCODE_SHR:
 944    case FS_OPCODE_LINTERP:
 945    case SHADER_OPCODE_COS:
 946    case SHADER_OPCODE_EXP2:
 947    case SHADER_OPCODE_LOG2:
 948    case SHADER_OPCODE_POW:
 949    case SHADER_OPCODE_RCP:
 950    case SHADER_OPCODE_RSQ:
 951    case SHADER_OPCODE_SIN:
 952    case SHADER_OPCODE_SQRT:
 953       return true;
 954    default:
 955       return false;
 956    }
 957 }
 958
 959 bool
 960 backend_instruction::can_do_cmod() const
 961 {
 962    switch (opcode) {
 963    case BRW_OPCODE_ADD:
 964    case BRW_OPCODE_ADDC:
 965    case BRW_OPCODE_AND:
 966    case BRW_OPCODE_ASR:
 967    case BRW_OPCODE_AVG:
 968    case BRW_OPCODE_CMP:
 969    case BRW_OPCODE_CMPN:
 970    case BRW_OPCODE_DP2:
 971    case BRW_OPCODE_DP3:
 972    case BRW_OPCODE_DP4:
 973    case BRW_OPCODE_DPH:
 974    case BRW_OPCODE_F16TO32:
 975    case BRW_OPCODE_F32TO16:
 976    case BRW_OPCODE_FRC:
 977    case BRW_OPCODE_LINE:
 978    case BRW_OPCODE_LRP:
 979    case BRW_OPCODE_LZD:
 980    case BRW_OPCODE_MAC:
 981    case BRW_OPCODE_MACH:
 982    case BRW_OPCODE_MAD:
 983    case BRW_OPCODE_MOV:
 984    case BRW_OPCODE_MUL:
 985    case BRW_OPCODE_NOT:
 986    case BRW_OPCODE_OR:
 987    case BRW_OPCODE_PLN:
 988    case BRW_OPCODE_RNDD:
 989    case BRW_OPCODE_RNDE:
 990    case BRW_OPCODE_RNDU:
 991    case BRW_OPCODE_RNDZ:
 992    case BRW_OPCODE_SAD2:
 993    case BRW_OPCODE_SADA2:
 994    case BRW_OPCODE_SHL:
 995    case BRW_OPCODE_SHR:
 996    case BRW_OPCODE_SUBB:
 997    case BRW_OPCODE_XOR:
 998    case FS_OPCODE_CINTERP:
 999    case FS_OPCODE_LINTERP:
1000       return true;
1001    default:
1002       return false;
1003    }
1004 }
1005
1006 bool
1007 backend_instruction::reads_accumulator_implicitly() const
1008 {
1009    switch (opcode) {
1010    case BRW_OPCODE_MAC:
1011    case BRW_OPCODE_MACH:
1012    case BRW_OPCODE_SADA2:
1013       return true;
1014    default:
1015       return false;
1016    }
1017 }
1018
1019 bool
1020 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1021 {
1022    return writes_accumulator ||
1023           (devinfo->gen < 6 &&
1024            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1025             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1026              opcode != FS_OPCODE_CINTERP)));
1027 }
1028
1029 bool
1030 backend_instruction::has_side_effects() const
1031 {
1032    switch (opcode) {
1033    case SHADER_OPCODE_UNTYPED_ATOMIC:
1034    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1035    case SHADER_OPCODE_URB_WRITE_SIMD8:
1036    case FS_OPCODE_FB_WRITE:
1037       return true;
1038    default:
1039       return false;
1040    }
1041 }
1042
1043 #ifndef NDEBUG
1044 static bool
1045 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1046 {
1047    bool found = false;
1048    foreach_inst_in_block (backend_instruction, i, block) {
1049       if (inst == i) {
1050          found = true;
1051       }
1052    }
1053    return found;
1054 }
1055 #endif
1056
1057 static void
1058 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1059 {
1060    for (bblock_t *block_iter = start_block->next();
1061         !block_iter->link.is_tail_sentinel();
1062         block_iter = block_iter->next()) {
1063       block_iter->start_ip += ip_adjustment;
1064       block_iter->end_ip += ip_adjustment;
1065    }
1066 }
1067
1068 void
1069 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1070 {
1071    if (!this->is_head_sentinel())
1072       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1073
1074    block->end_ip++;
1075
1076    adjust_later_block_ips(block, 1);
1077
1078    exec_node::insert_after(inst);
1079 }
1080
1081 void
1082 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1083 {
1084    if (!this->is_tail_sentinel())
1085       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1086
1087    block->end_ip++;
1088
1089    adjust_later_block_ips(block, 1);
1090
1091    exec_node::insert_before(inst);
1092 }
1093
1094 void
1095 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1096 {
1097    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1098
1099    unsigned num_inst = list->length();
1100
1101    block->end_ip += num_inst;
1102
1103    adjust_later_block_ips(block, num_inst);
1104
1105    exec_node::insert_before(list);
1106 }
1107
1108 void
1109 backend_instruction::remove(bblock_t *block)
1110 {
1111    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1112
1113    adjust_later_block_ips(block, -1);
1114
1115    if (block->start_ip == block->end_ip) {
1116       block->cfg->remove_block(block);
1117    } else {
1118       block->end_ip--;
1119    }
1120
1121    exec_node::remove();
1122 }
1123
1124 void
1125 backend_visitor::dump_instructions()
1126 {
1127    dump_instructions(NULL);
1128 }
1129
1130 void
1131 backend_visitor::dump_instructions(const char *name)
1132 {
1133    FILE *file = stderr;
1134    if (name && geteuid() != 0) {
1135       file = fopen(name, "w");
1136       if (!file)
1137          file = stderr;
1138    }
1139
1140    if (cfg) {
1141       int ip = 0;
1142       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1143          fprintf(file, "%4d: ", ip++);
1144          dump_instruction(inst, file);
1145       }
1146    } else {
1147       int ip = 0;
1148       foreach_in_list(backend_instruction, inst, &instructions) {
1149          fprintf(file, "%4d: ", ip++);
1150          dump_instruction(inst, file);
1151       }
1152    }
1153
1154    if (file != stderr) {
1155       fclose(file);
1156    }
1157 }
1158
1159 void
1160 backend_visitor::calculate_cfg()
1161 {
1162    if (this->cfg)
1163       return;
1164    cfg = new(mem_ctx) cfg_t(&this->instructions);
1165 }
1166
1167 void
1168 backend_visitor::invalidate_cfg()
1169 {
1170    ralloc_free(this->cfg);
1171    this->cfg = NULL;
1172 }
1173
1174 /**
1175  * Sets up the starting offsets for the groups of binding table entries
1176  * commong to all pipeline stages.
1177  *
1178  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1179  * unused but also make sure that addition of small offsets to them will
1180  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1181  */
1182 void
1183 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1184 {
1185    int num_textures = _mesa_fls(prog->SamplersUsed);
1186
1187    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1188    next_binding_table_offset += num_textures;
1189
1190    if (shader) {
1191       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1192       next_binding_table_offset += shader->base.NumUniformBlocks;
1193    } else {
1194       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1195    }
1196
1197    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1198       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1199       next_binding_table_offset++;
1200    } else {
1201       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1202    }
1203
1204    if (prog->UsesGather) {
1205       if (devinfo->gen >= 8) {
1206          stage_prog_data->binding_table.gather_texture_start =
1207             stage_prog_data->binding_table.texture_start;
1208       } else {
1209          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1210          next_binding_table_offset += num_textures;
1211       }
1212    } else {
1213       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1214    }
1215
1216    if (shader_prog && shader_prog->NumAtomicBuffers) {
1217       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1218       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1219    } else {
1220       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1221    }
1222
1223    if (shader && shader->base.NumImages) {
1224       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1225       next_binding_table_offset += shader->base.NumImages;
1226    } else {
1227       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1228    }
1229
1230    /* This may or may not be used depending on how the compile goes. */
1231    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1232    next_binding_table_offset++;
1233
1234    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1235
1236    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1237 }