src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 bool
  76 is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80    case MESA_SHADER_COMPUTE:
  81       return true;
  82    case MESA_SHADER_VERTEX:
  83       return compiler->scalar_vs;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 struct brw_compiler *
  90 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  91 {
  92    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  93
  94    compiler->devinfo = devinfo;
  95    compiler->shader_debug_log = shader_debug_log_mesa;
  96    compiler->shader_perf_log = shader_perf_log_mesa;
  97
  98    brw_fs_alloc_reg_sets(compiler);
  99    brw_vec4_alloc_reg_set(compiler);
 100
 101    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
 102       compiler->scalar_vs = true;
 103
 104    nir_shader_compiler_options *nir_options =
 105       rzalloc(compiler, nir_shader_compiler_options);
 106    nir_options->native_integers = true;
 107    /* In order to help allow for better CSE at the NIR level we tell NIR
 108     * to split all ffma instructions during opt_algebraic and we then
 109     * re-combine them as a later step.
 110     */
 111    nir_options->lower_ffma = true;
 112    nir_options->lower_sub = true;
 113    /* In the vec4 backend, our dpN instruction replicates its result to all
 114     * the components of a vec4.  We would like NIR to give us replicated fdot
 115     * instructions because it can optimize better for us.
 116     *
 117     * For the FS backend, it should be lowered away by the scalarizing pass so
 118     * we should never see fdot anyway.
 119     */
 120    nir_options->fdot_replicates = true;
 121
 122    /* We want the GLSL compiler to emit code that uses condition codes */
 123    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 124       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 125       compiler->glsl_compiler_options[i].MaxIfDepth =
 126          devinfo->gen < 6 ? 16 : UINT_MAX;
 127
 128       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 129       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 130       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 132       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 133       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 134
 135       bool is_scalar = is_scalar_shader_stage(compiler, i);
 136
 137       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 138       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 139       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 140
 141       /* !ARB_gpu_shader5 */
 142       if (devinfo->gen < 7)
 143          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 144
 145       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 146    }
 147
 148    return compiler;
 149 }
 150
 151 struct gl_shader *
 152 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 153 {
 154    struct brw_shader *shader;
 155
 156    shader = rzalloc(NULL, struct brw_shader);
 157    if (shader) {
 158       shader->base.Type = type;
 159       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 160       shader->base.Name = name;
 161       _mesa_init_shader(ctx, &shader->base);
 162    }
 163
 164    return &shader->base;
 165 }
 166
 167 void
 168 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 169                       unsigned surf_index)
 170 {
 171    assert(surf_index < BRW_MAX_SURFACES);
 172
 173    prog_data->binding_table.size_bytes =
 174       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 175 }
 176
 177 enum brw_reg_type
 178 brw_type_for_base_type(const struct glsl_type *type)
 179 {
 180    switch (type->base_type) {
 181    case GLSL_TYPE_FLOAT:
 182       return BRW_REGISTER_TYPE_F;
 183    case GLSL_TYPE_INT:
 184    case GLSL_TYPE_BOOL:
 185    case GLSL_TYPE_SUBROUTINE:
 186       return BRW_REGISTER_TYPE_D;
 187    case GLSL_TYPE_UINT:
 188       return BRW_REGISTER_TYPE_UD;
 189    case GLSL_TYPE_ARRAY:
 190       return brw_type_for_base_type(type->fields.array);
 191    case GLSL_TYPE_STRUCT:
 192    case GLSL_TYPE_SAMPLER:
 193    case GLSL_TYPE_ATOMIC_UINT:
 194       /* These should be overridden with the type of the member when
 195        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 196        * way to trip up if we don't.
 197        */
 198       return BRW_REGISTER_TYPE_UD;
 199    case GLSL_TYPE_IMAGE:
 200       return BRW_REGISTER_TYPE_UD;
 201    case GLSL_TYPE_VOID:
 202    case GLSL_TYPE_ERROR:
 203    case GLSL_TYPE_INTERFACE:
 204    case GLSL_TYPE_DOUBLE:
 205       unreachable("not reached");
 206    }
 207
 208    return BRW_REGISTER_TYPE_F;
 209 }
 210
 211 enum brw_conditional_mod
 212 brw_conditional_for_comparison(unsigned int op)
 213 {
 214    switch (op) {
 215    case ir_binop_less:
 216       return BRW_CONDITIONAL_L;
 217    case ir_binop_greater:
 218       return BRW_CONDITIONAL_G;
 219    case ir_binop_lequal:
 220       return BRW_CONDITIONAL_LE;
 221    case ir_binop_gequal:
 222       return BRW_CONDITIONAL_GE;
 223    case ir_binop_equal:
 224    case ir_binop_all_equal: /* same as equal for scalars */
 225       return BRW_CONDITIONAL_Z;
 226    case ir_binop_nequal:
 227    case ir_binop_any_nequal: /* same as nequal for scalars */
 228       return BRW_CONDITIONAL_NZ;
 229    default:
 230       unreachable("not reached: bad operation for comparison");
 231    }
 232 }
 233
 234 uint32_t
 235 brw_math_function(enum opcode op)
 236 {
 237    switch (op) {
 238    case SHADER_OPCODE_RCP:
 239       return BRW_MATH_FUNCTION_INV;
 240    case SHADER_OPCODE_RSQ:
 241       return BRW_MATH_FUNCTION_RSQ;
 242    case SHADER_OPCODE_SQRT:
 243       return BRW_MATH_FUNCTION_SQRT;
 244    case SHADER_OPCODE_EXP2:
 245       return BRW_MATH_FUNCTION_EXP;
 246    case SHADER_OPCODE_LOG2:
 247       return BRW_MATH_FUNCTION_LOG;
 248    case SHADER_OPCODE_POW:
 249       return BRW_MATH_FUNCTION_POW;
 250    case SHADER_OPCODE_SIN:
 251       return BRW_MATH_FUNCTION_SIN;
 252    case SHADER_OPCODE_COS:
 253       return BRW_MATH_FUNCTION_COS;
 254    case SHADER_OPCODE_INT_QUOTIENT:
 255       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 256    case SHADER_OPCODE_INT_REMAINDER:
 257       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 258    default:
 259       unreachable("not reached: unknown math function");
 260    }
 261 }
 262
 263 uint32_t
 264 brw_texture_offset(int *offsets, unsigned num_components)
 265 {
 266    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 267
 268    /* Combine all three offsets into a single unsigned dword:
 269     *
 270     *    bits 11:8 - U Offset (X component)
 271     *    bits  7:4 - V Offset (Y component)
 272     *    bits  3:0 - R Offset (Z component)
 273     */
 274    unsigned offset_bits = 0;
 275    for (unsigned i = 0; i < num_components; i++) {
 276       const unsigned shift = 4 * (2 - i);
 277       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 278    }
 279    return offset_bits;
 280 }
 281
 282 const char *
 283 brw_instruction_name(enum opcode op)
 284 {
 285    switch (op) {
 286    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 287       assert(opcode_descs[op].name);
 288       return opcode_descs[op].name;
 289    case FS_OPCODE_FB_WRITE:
 290       return "fb_write";
 291    case FS_OPCODE_FB_WRITE_LOGICAL:
 292       return "fb_write_logical";
 293    case FS_OPCODE_BLORP_FB_WRITE:
 294       return "blorp_fb_write";
 295    case FS_OPCODE_REP_FB_WRITE:
 296       return "rep_fb_write";
 297
 298    case SHADER_OPCODE_RCP:
 299       return "rcp";
 300    case SHADER_OPCODE_RSQ:
 301       return "rsq";
 302    case SHADER_OPCODE_SQRT:
 303       return "sqrt";
 304    case SHADER_OPCODE_EXP2:
 305       return "exp2";
 306    case SHADER_OPCODE_LOG2:
 307       return "log2";
 308    case SHADER_OPCODE_POW:
 309       return "pow";
 310    case SHADER_OPCODE_INT_QUOTIENT:
 311       return "int_quot";
 312    case SHADER_OPCODE_INT_REMAINDER:
 313       return "int_rem";
 314    case SHADER_OPCODE_SIN:
 315       return "sin";
 316    case SHADER_OPCODE_COS:
 317       return "cos";
 318
 319    case SHADER_OPCODE_TEX:
 320       return "tex";
 321    case SHADER_OPCODE_TEX_LOGICAL:
 322       return "tex_logical";
 323    case SHADER_OPCODE_TXD:
 324       return "txd";
 325    case SHADER_OPCODE_TXD_LOGICAL:
 326       return "txd_logical";
 327    case SHADER_OPCODE_TXF:
 328       return "txf";
 329    case SHADER_OPCODE_TXF_LOGICAL:
 330       return "txf_logical";
 331    case SHADER_OPCODE_TXL:
 332       return "txl";
 333    case SHADER_OPCODE_TXL_LOGICAL:
 334       return "txl_logical";
 335    case SHADER_OPCODE_TXS:
 336       return "txs";
 337    case SHADER_OPCODE_TXS_LOGICAL:
 338       return "txs_logical";
 339    case FS_OPCODE_TXB:
 340       return "txb";
 341    case FS_OPCODE_TXB_LOGICAL:
 342       return "txb_logical";
 343    case SHADER_OPCODE_TXF_CMS:
 344       return "txf_cms";
 345    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 346       return "txf_cms_logical";
 347    case SHADER_OPCODE_TXF_UMS:
 348       return "txf_ums";
 349    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 350       return "txf_ums_logical";
 351    case SHADER_OPCODE_TXF_MCS:
 352       return "txf_mcs";
 353    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 354       return "txf_mcs_logical";
 355    case SHADER_OPCODE_LOD:
 356       return "lod";
 357    case SHADER_OPCODE_LOD_LOGICAL:
 358       return "lod_logical";
 359    case SHADER_OPCODE_TG4:
 360       return "tg4";
 361    case SHADER_OPCODE_TG4_LOGICAL:
 362       return "tg4_logical";
 363    case SHADER_OPCODE_TG4_OFFSET:
 364       return "tg4_offset";
 365    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 366       return "tg4_offset_logical";
 367    case SHADER_OPCODE_SAMPLEINFO:
 368       return "sampleinfo";
 369
 370    case SHADER_OPCODE_SHADER_TIME_ADD:
 371       return "shader_time_add";
 372
 373    case SHADER_OPCODE_UNTYPED_ATOMIC:
 374       return "untyped_atomic";
 375    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 376       return "untyped_atomic_logical";
 377    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 378       return "untyped_surface_read";
 379    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 380       return "untyped_surface_read_logical";
 381    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 382       return "untyped_surface_write";
 383    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 384       return "untyped_surface_write_logical";
 385    case SHADER_OPCODE_TYPED_ATOMIC:
 386       return "typed_atomic";
 387    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 388       return "typed_atomic_logical";
 389    case SHADER_OPCODE_TYPED_SURFACE_READ:
 390       return "typed_surface_read";
 391    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 392       return "typed_surface_read_logical";
 393    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 394       return "typed_surface_write";
 395    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 396       return "typed_surface_write_logical";
 397    case SHADER_OPCODE_MEMORY_FENCE:
 398       return "memory_fence";
 399
 400    case SHADER_OPCODE_LOAD_PAYLOAD:
 401       return "load_payload";
 402
 403    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 404       return "gen4_scratch_read";
 405    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 406       return "gen4_scratch_write";
 407    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 408       return "gen7_scratch_read";
 409    case SHADER_OPCODE_URB_WRITE_SIMD8:
 410       return "gen8_urb_write_simd8";
 411
 412    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 413       return "find_live_channel";
 414    case SHADER_OPCODE_BROADCAST:
 415       return "broadcast";
 416
 417    case VEC4_OPCODE_MOV_BYTES:
 418       return "mov_bytes";
 419    case VEC4_OPCODE_PACK_BYTES:
 420       return "pack_bytes";
 421    case VEC4_OPCODE_UNPACK_UNIFORM:
 422       return "unpack_uniform";
 423
 424    case FS_OPCODE_DDX_COARSE:
 425       return "ddx_coarse";
 426    case FS_OPCODE_DDX_FINE:
 427       return "ddx_fine";
 428    case FS_OPCODE_DDY_COARSE:
 429       return "ddy_coarse";
 430    case FS_OPCODE_DDY_FINE:
 431       return "ddy_fine";
 432
 433    case FS_OPCODE_CINTERP:
 434       return "cinterp";
 435    case FS_OPCODE_LINTERP:
 436       return "linterp";
 437
 438    case FS_OPCODE_PIXEL_X:
 439       return "pixel_x";
 440    case FS_OPCODE_PIXEL_Y:
 441       return "pixel_y";
 442
 443    case FS_OPCODE_GET_BUFFER_SIZE:
 444       return "fs_get_buffer_size";
 445
 446    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 447       return "uniform_pull_const";
 448    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 449       return "uniform_pull_const_gen7";
 450    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 451       return "varying_pull_const";
 452    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 453       return "varying_pull_const_gen7";
 454
 455    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 456       return "mov_dispatch_to_flags";
 457    case FS_OPCODE_DISCARD_JUMP:
 458       return "discard_jump";
 459
 460    case FS_OPCODE_SET_SAMPLE_ID:
 461       return "set_sample_id";
 462    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 463       return "set_simd4x2_offset";
 464
 465    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 466       return "pack_half_2x16_split";
 467    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 468       return "unpack_half_2x16_split_x";
 469    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 470       return "unpack_half_2x16_split_y";
 471
 472    case FS_OPCODE_PLACEHOLDER_HALT:
 473       return "placeholder_halt";
 474
 475    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 476       return "interp_centroid";
 477    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 478       return "interp_sample";
 479    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 480       return "interp_shared_offset";
 481    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 482       return "interp_per_slot_offset";
 483
 484    case VS_OPCODE_URB_WRITE:
 485       return "vs_urb_write";
 486    case VS_OPCODE_PULL_CONSTANT_LOAD:
 487       return "pull_constant_load";
 488    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 489       return "pull_constant_load_gen7";
 490
 491    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 492       return "set_simd4x2_header_gen9";
 493
 494    case VS_OPCODE_GET_BUFFER_SIZE:
 495       return "vs_get_buffer_size";
 496
 497    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 498       return "unpack_flags_simd4x2";
 499
 500    case GS_OPCODE_URB_WRITE:
 501       return "gs_urb_write";
 502    case GS_OPCODE_URB_WRITE_ALLOCATE:
 503       return "gs_urb_write_allocate";
 504    case GS_OPCODE_THREAD_END:
 505       return "gs_thread_end";
 506    case GS_OPCODE_SET_WRITE_OFFSET:
 507       return "set_write_offset";
 508    case GS_OPCODE_SET_VERTEX_COUNT:
 509       return "set_vertex_count";
 510    case GS_OPCODE_SET_DWORD_2:
 511       return "set_dword_2";
 512    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 513       return "prepare_channel_masks";
 514    case GS_OPCODE_SET_CHANNEL_MASKS:
 515       return "set_channel_masks";
 516    case GS_OPCODE_GET_INSTANCE_ID:
 517       return "get_instance_id";
 518    case GS_OPCODE_FF_SYNC:
 519       return "ff_sync";
 520    case GS_OPCODE_SET_PRIMITIVE_ID:
 521       return "set_primitive_id";
 522    case GS_OPCODE_SVB_WRITE:
 523       return "gs_svb_write";
 524    case GS_OPCODE_SVB_SET_DST_INDEX:
 525       return "gs_svb_set_dst_index";
 526    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 527       return "gs_ff_sync_set_primitives";
 528    case CS_OPCODE_CS_TERMINATE:
 529       return "cs_terminate";
 530    case SHADER_OPCODE_BARRIER:
 531       return "barrier";
 532    case SHADER_OPCODE_MULH:
 533       return "mulh";
 534    }
 535
 536    unreachable("not reached");
 537 }
 538
 539 bool
 540 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 541 {
 542    union {
 543       unsigned ud;
 544       int d;
 545       float f;
 546    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 547
 548    switch (type) {
 549    case BRW_REGISTER_TYPE_UD:
 550    case BRW_REGISTER_TYPE_D:
 551    case BRW_REGISTER_TYPE_UQ:
 552    case BRW_REGISTER_TYPE_Q:
 553       /* Nothing to do. */
 554       return false;
 555    case BRW_REGISTER_TYPE_UW:
 556       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 557       break;
 558    case BRW_REGISTER_TYPE_W:
 559       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 560       break;
 561    case BRW_REGISTER_TYPE_F:
 562       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 563       break;
 564    case BRW_REGISTER_TYPE_UB:
 565    case BRW_REGISTER_TYPE_B:
 566       unreachable("no UB/B immediates");
 567    case BRW_REGISTER_TYPE_V:
 568    case BRW_REGISTER_TYPE_UV:
 569    case BRW_REGISTER_TYPE_VF:
 570       unreachable("unimplemented: saturate vector immediate");
 571    case BRW_REGISTER_TYPE_DF:
 572    case BRW_REGISTER_TYPE_HF:
 573       unreachable("unimplemented: saturate DF/HF immediate");
 574    }
 575
 576    if (imm.ud != sat_imm.ud) {
 577       reg->dw1.ud = sat_imm.ud;
 578       return true;
 579    }
 580    return false;
 581 }
 582
 583 bool
 584 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 585 {
 586    switch (type) {
 587    case BRW_REGISTER_TYPE_D:
 588    case BRW_REGISTER_TYPE_UD:
 589       reg->dw1.d = -reg->dw1.d;
 590       return true;
 591    case BRW_REGISTER_TYPE_W:
 592    case BRW_REGISTER_TYPE_UW:
 593       reg->dw1.d = -(int16_t)reg->dw1.ud;
 594       return true;
 595    case BRW_REGISTER_TYPE_F:
 596       reg->dw1.f = -reg->dw1.f;
 597       return true;
 598    case BRW_REGISTER_TYPE_VF:
 599       reg->dw1.ud ^= 0x80808080;
 600       return true;
 601    case BRW_REGISTER_TYPE_UB:
 602    case BRW_REGISTER_TYPE_B:
 603       unreachable("no UB/B immediates");
 604    case BRW_REGISTER_TYPE_UV:
 605    case BRW_REGISTER_TYPE_V:
 606       assert(!"unimplemented: negate UV/V immediate");
 607    case BRW_REGISTER_TYPE_UQ:
 608    case BRW_REGISTER_TYPE_Q:
 609       assert(!"unimplemented: negate UQ/Q immediate");
 610    case BRW_REGISTER_TYPE_DF:
 611    case BRW_REGISTER_TYPE_HF:
 612       assert(!"unimplemented: negate DF/HF immediate");
 613    }
 614
 615    return false;
 616 }
 617
 618 bool
 619 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 620 {
 621    switch (type) {
 622    case BRW_REGISTER_TYPE_D:
 623       reg->dw1.d = abs(reg->dw1.d);
 624       return true;
 625    case BRW_REGISTER_TYPE_W:
 626       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 627       return true;
 628    case BRW_REGISTER_TYPE_F:
 629       reg->dw1.f = fabsf(reg->dw1.f);
 630       return true;
 631    case BRW_REGISTER_TYPE_VF:
 632       reg->dw1.ud &= ~0x80808080;
 633       return true;
 634    case BRW_REGISTER_TYPE_UB:
 635    case BRW_REGISTER_TYPE_B:
 636       unreachable("no UB/B immediates");
 637    case BRW_REGISTER_TYPE_UQ:
 638    case BRW_REGISTER_TYPE_UD:
 639    case BRW_REGISTER_TYPE_UW:
 640    case BRW_REGISTER_TYPE_UV:
 641       /* Presumably the absolute value modifier on an unsigned source is a
 642        * nop, but it would be nice to confirm.
 643        */
 644       assert(!"unimplemented: abs unsigned immediate");
 645    case BRW_REGISTER_TYPE_V:
 646       assert(!"unimplemented: abs V immediate");
 647    case BRW_REGISTER_TYPE_Q:
 648       assert(!"unimplemented: abs Q immediate");
 649    case BRW_REGISTER_TYPE_DF:
 650    case BRW_REGISTER_TYPE_HF:
 651       assert(!"unimplemented: abs DF/HF immediate");
 652    }
 653
 654    return false;
 655 }
 656
 657 backend_shader::backend_shader(const struct brw_compiler *compiler,
 658                                void *log_data,
 659                                void *mem_ctx,
 660                                nir_shader *shader,
 661                                struct brw_stage_prog_data *stage_prog_data)
 662    : compiler(compiler),
 663      log_data(log_data),
 664      devinfo(compiler->devinfo),
 665      nir(shader),
 666      stage_prog_data(stage_prog_data),
 667      mem_ctx(mem_ctx),
 668      cfg(NULL),
 669      stage(shader->stage)
 670 {
 671    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 672    stage_name = _mesa_shader_stage_to_string(stage);
 673    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 674 }
 675
 676 bool
 677 backend_reg::is_zero() const
 678 {
 679    if (file != IMM)
 680       return false;
 681
 682    return fixed_hw_reg.dw1.d == 0;
 683 }
 684
 685 bool
 686 backend_reg::is_one() const
 687 {
 688    if (file != IMM)
 689       return false;
 690
 691    return type == BRW_REGISTER_TYPE_F
 692           ? fixed_hw_reg.dw1.f == 1.0
 693           : fixed_hw_reg.dw1.d == 1;
 694 }
 695
 696 bool
 697 backend_reg::is_negative_one() const
 698 {
 699    if (file != IMM)
 700       return false;
 701
 702    switch (type) {
 703    case BRW_REGISTER_TYPE_F:
 704       return fixed_hw_reg.dw1.f == -1.0;
 705    case BRW_REGISTER_TYPE_D:
 706       return fixed_hw_reg.dw1.d == -1;
 707    default:
 708       return false;
 709    }
 710 }
 711
 712 bool
 713 backend_reg::is_null() const
 714 {
 715    return file == HW_REG &&
 716           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 717           fixed_hw_reg.nr == BRW_ARF_NULL;
 718 }
 719
 720
 721 bool
 722 backend_reg::is_accumulator() const
 723 {
 724    return file == HW_REG &&
 725           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 726           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 727 }
 728
 729 bool
 730 backend_reg::in_range(const backend_reg &r, unsigned n) const
 731 {
 732    return (file == r.file &&
 733            reg == r.reg &&
 734            reg_offset >= r.reg_offset &&
 735            reg_offset < r.reg_offset + n);
 736 }
 737
 738 bool
 739 backend_instruction::is_commutative() const
 740 {
 741    switch (opcode) {
 742    case BRW_OPCODE_AND:
 743    case BRW_OPCODE_OR:
 744    case BRW_OPCODE_XOR:
 745    case BRW_OPCODE_ADD:
 746    case BRW_OPCODE_MUL:
 747    case SHADER_OPCODE_MULH:
 748       return true;
 749    case BRW_OPCODE_SEL:
 750       /* MIN and MAX are commutative. */
 751       if (conditional_mod == BRW_CONDITIONAL_GE ||
 752           conditional_mod == BRW_CONDITIONAL_L) {
 753          return true;
 754       }
 755       /* fallthrough */
 756    default:
 757       return false;
 758    }
 759 }
 760
 761 bool
 762 backend_instruction::is_3src() const
 763 {
 764    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 765 }
 766
 767 bool
 768 backend_instruction::is_tex() const
 769 {
 770    return (opcode == SHADER_OPCODE_TEX ||
 771            opcode == FS_OPCODE_TXB ||
 772            opcode == SHADER_OPCODE_TXD ||
 773            opcode == SHADER_OPCODE_TXF ||
 774            opcode == SHADER_OPCODE_TXF_CMS ||
 775            opcode == SHADER_OPCODE_TXF_UMS ||
 776            opcode == SHADER_OPCODE_TXF_MCS ||
 777            opcode == SHADER_OPCODE_TXL ||
 778            opcode == SHADER_OPCODE_TXS ||
 779            opcode == SHADER_OPCODE_LOD ||
 780            opcode == SHADER_OPCODE_TG4 ||
 781            opcode == SHADER_OPCODE_TG4_OFFSET);
 782 }
 783
 784 bool
 785 backend_instruction::is_math() const
 786 {
 787    return (opcode == SHADER_OPCODE_RCP ||
 788            opcode == SHADER_OPCODE_RSQ ||
 789            opcode == SHADER_OPCODE_SQRT ||
 790            opcode == SHADER_OPCODE_EXP2 ||
 791            opcode == SHADER_OPCODE_LOG2 ||
 792            opcode == SHADER_OPCODE_SIN ||
 793            opcode == SHADER_OPCODE_COS ||
 794            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 795            opcode == SHADER_OPCODE_INT_REMAINDER ||
 796            opcode == SHADER_OPCODE_POW);
 797 }
 798
 799 bool
 800 backend_instruction::is_control_flow() const
 801 {
 802    switch (opcode) {
 803    case BRW_OPCODE_DO:
 804    case BRW_OPCODE_WHILE:
 805    case BRW_OPCODE_IF:
 806    case BRW_OPCODE_ELSE:
 807    case BRW_OPCODE_ENDIF:
 808    case BRW_OPCODE_BREAK:
 809    case BRW_OPCODE_CONTINUE:
 810       return true;
 811    default:
 812       return false;
 813    }
 814 }
 815
 816 bool
 817 backend_instruction::can_do_source_mods() const
 818 {
 819    switch (opcode) {
 820    case BRW_OPCODE_ADDC:
 821    case BRW_OPCODE_BFE:
 822    case BRW_OPCODE_BFI1:
 823    case BRW_OPCODE_BFI2:
 824    case BRW_OPCODE_BFREV:
 825    case BRW_OPCODE_CBIT:
 826    case BRW_OPCODE_FBH:
 827    case BRW_OPCODE_FBL:
 828    case BRW_OPCODE_SUBB:
 829       return false;
 830    default:
 831       return true;
 832    }
 833 }
 834
 835 bool
 836 backend_instruction::can_do_saturate() const
 837 {
 838    switch (opcode) {
 839    case BRW_OPCODE_ADD:
 840    case BRW_OPCODE_ASR:
 841    case BRW_OPCODE_AVG:
 842    case BRW_OPCODE_DP2:
 843    case BRW_OPCODE_DP3:
 844    case BRW_OPCODE_DP4:
 845    case BRW_OPCODE_DPH:
 846    case BRW_OPCODE_F16TO32:
 847    case BRW_OPCODE_F32TO16:
 848    case BRW_OPCODE_LINE:
 849    case BRW_OPCODE_LRP:
 850    case BRW_OPCODE_MAC:
 851    case BRW_OPCODE_MAD:
 852    case BRW_OPCODE_MATH:
 853    case BRW_OPCODE_MOV:
 854    case BRW_OPCODE_MUL:
 855    case SHADER_OPCODE_MULH:
 856    case BRW_OPCODE_PLN:
 857    case BRW_OPCODE_RNDD:
 858    case BRW_OPCODE_RNDE:
 859    case BRW_OPCODE_RNDU:
 860    case BRW_OPCODE_RNDZ:
 861    case BRW_OPCODE_SEL:
 862    case BRW_OPCODE_SHL:
 863    case BRW_OPCODE_SHR:
 864    case FS_OPCODE_LINTERP:
 865    case SHADER_OPCODE_COS:
 866    case SHADER_OPCODE_EXP2:
 867    case SHADER_OPCODE_LOG2:
 868    case SHADER_OPCODE_POW:
 869    case SHADER_OPCODE_RCP:
 870    case SHADER_OPCODE_RSQ:
 871    case SHADER_OPCODE_SIN:
 872    case SHADER_OPCODE_SQRT:
 873       return true;
 874    default:
 875       return false;
 876    }
 877 }
 878
 879 bool
 880 backend_instruction::can_do_cmod() const
 881 {
 882    switch (opcode) {
 883    case BRW_OPCODE_ADD:
 884    case BRW_OPCODE_ADDC:
 885    case BRW_OPCODE_AND:
 886    case BRW_OPCODE_ASR:
 887    case BRW_OPCODE_AVG:
 888    case BRW_OPCODE_CMP:
 889    case BRW_OPCODE_CMPN:
 890    case BRW_OPCODE_DP2:
 891    case BRW_OPCODE_DP3:
 892    case BRW_OPCODE_DP4:
 893    case BRW_OPCODE_DPH:
 894    case BRW_OPCODE_F16TO32:
 895    case BRW_OPCODE_F32TO16:
 896    case BRW_OPCODE_FRC:
 897    case BRW_OPCODE_LINE:
 898    case BRW_OPCODE_LRP:
 899    case BRW_OPCODE_LZD:
 900    case BRW_OPCODE_MAC:
 901    case BRW_OPCODE_MACH:
 902    case BRW_OPCODE_MAD:
 903    case BRW_OPCODE_MOV:
 904    case BRW_OPCODE_MUL:
 905    case BRW_OPCODE_NOT:
 906    case BRW_OPCODE_OR:
 907    case BRW_OPCODE_PLN:
 908    case BRW_OPCODE_RNDD:
 909    case BRW_OPCODE_RNDE:
 910    case BRW_OPCODE_RNDU:
 911    case BRW_OPCODE_RNDZ:
 912    case BRW_OPCODE_SAD2:
 913    case BRW_OPCODE_SADA2:
 914    case BRW_OPCODE_SHL:
 915    case BRW_OPCODE_SHR:
 916    case BRW_OPCODE_SUBB:
 917    case BRW_OPCODE_XOR:
 918    case FS_OPCODE_CINTERP:
 919    case FS_OPCODE_LINTERP:
 920       return true;
 921    default:
 922       return false;
 923    }
 924 }
 925
 926 bool
 927 backend_instruction::reads_accumulator_implicitly() const
 928 {
 929    switch (opcode) {
 930    case BRW_OPCODE_MAC:
 931    case BRW_OPCODE_MACH:
 932    case BRW_OPCODE_SADA2:
 933       return true;
 934    default:
 935       return false;
 936    }
 937 }
 938
 939 bool
 940 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 941 {
 942    return writes_accumulator ||
 943           (devinfo->gen < 6 &&
 944            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 945             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 946              opcode != FS_OPCODE_CINTERP)));
 947 }
 948
 949 bool
 950 backend_instruction::has_side_effects() const
 951 {
 952    switch (opcode) {
 953    case SHADER_OPCODE_UNTYPED_ATOMIC:
 954    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 955    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 956    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 957    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 958    case SHADER_OPCODE_TYPED_ATOMIC:
 959    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 960    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 961    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 962    case SHADER_OPCODE_MEMORY_FENCE:
 963    case SHADER_OPCODE_URB_WRITE_SIMD8:
 964    case FS_OPCODE_FB_WRITE:
 965    case SHADER_OPCODE_BARRIER:
 966       return true;
 967    default:
 968       return false;
 969    }
 970 }
 971
 972 #ifndef NDEBUG
 973 static bool
 974 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 975 {
 976    bool found = false;
 977    foreach_inst_in_block (backend_instruction, i, block) {
 978       if (inst == i) {
 979          found = true;
 980       }
 981    }
 982    return found;
 983 }
 984 #endif
 985
 986 static void
 987 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 988 {
 989    for (bblock_t *block_iter = start_block->next();
 990         !block_iter->link.is_tail_sentinel();
 991         block_iter = block_iter->next()) {
 992       block_iter->start_ip += ip_adjustment;
 993       block_iter->end_ip += ip_adjustment;
 994    }
 995 }
 996
 997 void
 998 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
 999 {
1000    if (!this->is_head_sentinel())
1001       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1002
1003    block->end_ip++;
1004
1005    adjust_later_block_ips(block, 1);
1006
1007    exec_node::insert_after(inst);
1008 }
1009
1010 void
1011 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1012 {
1013    if (!this->is_tail_sentinel())
1014       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1015
1016    block->end_ip++;
1017
1018    adjust_later_block_ips(block, 1);
1019
1020    exec_node::insert_before(inst);
1021 }
1022
1023 void
1024 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1025 {
1026    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1027
1028    unsigned num_inst = list->length();
1029
1030    block->end_ip += num_inst;
1031
1032    adjust_later_block_ips(block, num_inst);
1033
1034    exec_node::insert_before(list);
1035 }
1036
1037 void
1038 backend_instruction::remove(bblock_t *block)
1039 {
1040    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1041
1042    adjust_later_block_ips(block, -1);
1043
1044    if (block->start_ip == block->end_ip) {
1045       block->cfg->remove_block(block);
1046    } else {
1047       block->end_ip--;
1048    }
1049
1050    exec_node::remove();
1051 }
1052
1053 void
1054 backend_shader::dump_instructions()
1055 {
1056    dump_instructions(NULL);
1057 }
1058
1059 void
1060 backend_shader::dump_instructions(const char *name)
1061 {
1062    FILE *file = stderr;
1063    if (name && geteuid() != 0) {
1064       file = fopen(name, "w");
1065       if (!file)
1066          file = stderr;
1067    }
1068
1069    if (cfg) {
1070       int ip = 0;
1071       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1072          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1073             fprintf(file, "%4d: ", ip++);
1074          dump_instruction(inst, file);
1075       }
1076    } else {
1077       int ip = 0;
1078       foreach_in_list(backend_instruction, inst, &instructions) {
1079          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1080             fprintf(file, "%4d: ", ip++);
1081          dump_instruction(inst, file);
1082       }
1083    }
1084
1085    if (file != stderr) {
1086       fclose(file);
1087    }
1088 }
1089
1090 void
1091 backend_shader::calculate_cfg()
1092 {
1093    if (this->cfg)
1094       return;
1095    cfg = new(mem_ctx) cfg_t(&this->instructions);
1096 }
1097
1098 void
1099 backend_shader::invalidate_cfg()
1100 {
1101    ralloc_free(this->cfg);
1102    this->cfg = NULL;
1103 }
1104
1105 /**
1106  * Sets up the starting offsets for the groups of binding table entries
1107  * commong to all pipeline stages.
1108  *
1109  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1110  * unused but also make sure that addition of small offsets to them will
1111  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1112  */
1113 void
1114 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1115                                         const struct brw_device_info *devinfo,
1116                                         const struct gl_shader_program *shader_prog,
1117                                         const struct gl_program *prog,
1118                                         struct brw_stage_prog_data *stage_prog_data,
1119                                         uint32_t next_binding_table_offset)
1120 {
1121    const struct gl_shader *shader = NULL;
1122    int num_textures = _mesa_fls(prog->SamplersUsed);
1123
1124    if (shader_prog)
1125       shader = shader_prog->_LinkedShaders[stage];
1126
1127    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1128    next_binding_table_offset += num_textures;
1129
1130    if (shader) {
1131       assert(shader->NumUniformBlocks <= BRW_MAX_COMBINED_UBO_SSBO);
1132       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1133       next_binding_table_offset += shader->NumUniformBlocks;
1134    } else {
1135       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1136    }
1137
1138    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1139       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1140       next_binding_table_offset++;
1141    } else {
1142       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1143    }
1144
1145    if (prog->UsesGather) {
1146       if (devinfo->gen >= 8) {
1147          stage_prog_data->binding_table.gather_texture_start =
1148             stage_prog_data->binding_table.texture_start;
1149       } else {
1150          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1151          next_binding_table_offset += num_textures;
1152       }
1153    } else {
1154       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1155    }
1156
1157    if (shader_prog && shader_prog->NumAtomicBuffers) {
1158       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1159       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1160    } else {
1161       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1162    }
1163
1164    if (shader && shader->NumImages) {
1165       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1166       next_binding_table_offset += shader->NumImages;
1167    } else {
1168       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1169    }
1170
1171    /* This may or may not be used depending on how the compile goes. */
1172    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1173    next_binding_table_offset++;
1174
1175    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1176
1177    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1178 }
1179
1180 static void
1181 setup_vec4_uniform_value(const gl_constant_value **params,
1182                          const gl_constant_value *values,
1183                          unsigned n)
1184 {
1185    static const gl_constant_value zero = { 0 };
1186
1187    for (unsigned i = 0; i < n; ++i)
1188       params[i] = &values[i];
1189
1190    for (unsigned i = n; i < 4; ++i)
1191       params[i] = &zero;
1192 }
1193
1194 void
1195 brw_setup_image_uniform_values(gl_shader_stage stage,
1196                                struct brw_stage_prog_data *stage_prog_data,
1197                                unsigned param_start_index,
1198                                const gl_uniform_storage *storage)
1199 {
1200    const gl_constant_value **param =
1201       &stage_prog_data->param[param_start_index];
1202
1203    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1204       const unsigned image_idx = storage->opaque[stage].index + i;
1205       const brw_image_param *image_param =
1206          &stage_prog_data->image_param[image_idx];
1207
1208       /* Upload the brw_image_param structure.  The order is expected to match
1209        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1210        */
1211       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1212          (const gl_constant_value *)&image_param->surface_idx, 1);
1213       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1214          (const gl_constant_value *)image_param->offset, 2);
1215       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1216          (const gl_constant_value *)image_param->size, 3);
1217       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1218          (const gl_constant_value *)image_param->stride, 4);
1219       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1220          (const gl_constant_value *)image_param->tiling, 3);
1221       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1222          (const gl_constant_value *)image_param->swizzling, 2);
1223       param += BRW_IMAGE_PARAM_SIZE;
1224
1225       brw_mark_surface_used(
1226          stage_prog_data,
1227          stage_prog_data->binding_table.image_start + image_idx);
1228    }
1229 }
1230
1231 /**
1232  * Decide which set of clip planes should be used when clipping via
1233  * gl_Position or gl_ClipVertex.
1234  */
1235 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1236 {
1237    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1238       /* There is currently a GLSL vertex shader, so clip according to GLSL
1239        * rules, which means compare gl_ClipVertex (or gl_Position, if
1240        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1241        * that were stored in EyeUserPlane at the time the clip planes were
1242        * specified.
1243        */
1244       return ctx->Transform.EyeUserPlane;
1245    } else {
1246       /* Either we are using fixed function or an ARB vertex program.  In
1247        * either case the clip planes are going to be compared against
1248        * gl_Position (which is in clip coordinates) so we have to clip using
1249        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1250        * core.
1251        */
1252       return ctx->Transform._ClipUserPlane;
1253    }
1254 }
1255