src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 bool
  76 is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80    case MESA_SHADER_COMPUTE:
  81       return true;
  82    case MESA_SHADER_GEOMETRY:
  83       return compiler->scalar_gs;
  84    case MESA_SHADER_VERTEX:
  85       return compiler->scalar_vs;
  86    default:
  87       return false;
  88    }
  89 }
  90
  91 struct brw_compiler *
  92 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  93 {
  94    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  95
  96    compiler->devinfo = devinfo;
  97    compiler->shader_debug_log = shader_debug_log_mesa;
  98    compiler->shader_perf_log = shader_perf_log_mesa;
  99
 100    brw_fs_alloc_reg_sets(compiler);
 101    brw_vec4_alloc_reg_set(compiler);
 102
 103    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
 104       compiler->scalar_vs = true;
 105
 106    if (devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
 107       compiler->scalar_gs = true;
 108
 109    nir_shader_compiler_options *nir_options =
 110       rzalloc(compiler, nir_shader_compiler_options);
 111    nir_options->native_integers = true;
 112    /* In order to help allow for better CSE at the NIR level we tell NIR
 113     * to split all ffma instructions during opt_algebraic and we then
 114     * re-combine them as a later step.
 115     */
 116    nir_options->lower_ffma = true;
 117    nir_options->lower_sub = true;
 118    nir_options->lower_fdiv = true;
 119
 120    /* In the vec4 backend, our dpN instruction replicates its result to all
 121     * the components of a vec4.  We would like NIR to give us replicated fdot
 122     * instructions because it can optimize better for us.
 123     *
 124     * For the FS backend, it should be lowered away by the scalarizing pass so
 125     * we should never see fdot anyway.
 126     */
 127    nir_options->fdot_replicates = true;
 128
 129    /* We want the GLSL compiler to emit code that uses condition codes */
 130    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 131       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 132       compiler->glsl_compiler_options[i].MaxIfDepth =
 133          devinfo->gen < 6 ? 16 : UINT_MAX;
 134
 135       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 136       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 137       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 138       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 139       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 140       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 141
 142       bool is_scalar = is_scalar_shader_stage(compiler, i);
 143
 144       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 145       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 146       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 147
 148       /* !ARB_gpu_shader5 */
 149       if (devinfo->gen < 7)
 150          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 151
 152       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 153
 154       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 155    }
 156
 157    return compiler;
 158 }
 159
 160 struct gl_shader *
 161 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 162 {
 163    struct brw_shader *shader;
 164
 165    shader = rzalloc(NULL, struct brw_shader);
 166    if (shader) {
 167       shader->base.Type = type;
 168       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 169       shader->base.Name = name;
 170       _mesa_init_shader(ctx, &shader->base);
 171    }
 172
 173    return &shader->base;
 174 }
 175
 176 void
 177 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 178                       unsigned surf_index)
 179 {
 180    assert(surf_index < BRW_MAX_SURFACES);
 181
 182    prog_data->binding_table.size_bytes =
 183       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 184 }
 185
 186 enum brw_reg_type
 187 brw_type_for_base_type(const struct glsl_type *type)
 188 {
 189    switch (type->base_type) {
 190    case GLSL_TYPE_FLOAT:
 191       return BRW_REGISTER_TYPE_F;
 192    case GLSL_TYPE_INT:
 193    case GLSL_TYPE_BOOL:
 194    case GLSL_TYPE_SUBROUTINE:
 195       return BRW_REGISTER_TYPE_D;
 196    case GLSL_TYPE_UINT:
 197       return BRW_REGISTER_TYPE_UD;
 198    case GLSL_TYPE_ARRAY:
 199       return brw_type_for_base_type(type->fields.array);
 200    case GLSL_TYPE_STRUCT:
 201    case GLSL_TYPE_SAMPLER:
 202    case GLSL_TYPE_ATOMIC_UINT:
 203       /* These should be overridden with the type of the member when
 204        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 205        * way to trip up if we don't.
 206        */
 207       return BRW_REGISTER_TYPE_UD;
 208    case GLSL_TYPE_IMAGE:
 209       return BRW_REGISTER_TYPE_UD;
 210    case GLSL_TYPE_VOID:
 211    case GLSL_TYPE_ERROR:
 212    case GLSL_TYPE_INTERFACE:
 213    case GLSL_TYPE_DOUBLE:
 214    case GLSL_TYPE_FUNCTION:
 215       unreachable("not reached");
 216    }
 217
 218    return BRW_REGISTER_TYPE_F;
 219 }
 220
 221 enum brw_conditional_mod
 222 brw_conditional_for_comparison(unsigned int op)
 223 {
 224    switch (op) {
 225    case ir_binop_less:
 226       return BRW_CONDITIONAL_L;
 227    case ir_binop_greater:
 228       return BRW_CONDITIONAL_G;
 229    case ir_binop_lequal:
 230       return BRW_CONDITIONAL_LE;
 231    case ir_binop_gequal:
 232       return BRW_CONDITIONAL_GE;
 233    case ir_binop_equal:
 234    case ir_binop_all_equal: /* same as equal for scalars */
 235       return BRW_CONDITIONAL_Z;
 236    case ir_binop_nequal:
 237    case ir_binop_any_nequal: /* same as nequal for scalars */
 238       return BRW_CONDITIONAL_NZ;
 239    default:
 240       unreachable("not reached: bad operation for comparison");
 241    }
 242 }
 243
 244 uint32_t
 245 brw_math_function(enum opcode op)
 246 {
 247    switch (op) {
 248    case SHADER_OPCODE_RCP:
 249       return BRW_MATH_FUNCTION_INV;
 250    case SHADER_OPCODE_RSQ:
 251       return BRW_MATH_FUNCTION_RSQ;
 252    case SHADER_OPCODE_SQRT:
 253       return BRW_MATH_FUNCTION_SQRT;
 254    case SHADER_OPCODE_EXP2:
 255       return BRW_MATH_FUNCTION_EXP;
 256    case SHADER_OPCODE_LOG2:
 257       return BRW_MATH_FUNCTION_LOG;
 258    case SHADER_OPCODE_POW:
 259       return BRW_MATH_FUNCTION_POW;
 260    case SHADER_OPCODE_SIN:
 261       return BRW_MATH_FUNCTION_SIN;
 262    case SHADER_OPCODE_COS:
 263       return BRW_MATH_FUNCTION_COS;
 264    case SHADER_OPCODE_INT_QUOTIENT:
 265       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 266    case SHADER_OPCODE_INT_REMAINDER:
 267       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 268    default:
 269       unreachable("not reached: unknown math function");
 270    }
 271 }
 272
 273 uint32_t
 274 brw_texture_offset(int *offsets, unsigned num_components)
 275 {
 276    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 277
 278    /* Combine all three offsets into a single unsigned dword:
 279     *
 280     *    bits 11:8 - U Offset (X component)
 281     *    bits  7:4 - V Offset (Y component)
 282     *    bits  3:0 - R Offset (Z component)
 283     */
 284    unsigned offset_bits = 0;
 285    for (unsigned i = 0; i < num_components; i++) {
 286       const unsigned shift = 4 * (2 - i);
 287       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 288    }
 289    return offset_bits;
 290 }
 291
 292 const char *
 293 brw_instruction_name(enum opcode op)
 294 {
 295    switch (op) {
 296    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 297       assert(opcode_descs[op].name);
 298       return opcode_descs[op].name;
 299    case FS_OPCODE_FB_WRITE:
 300       return "fb_write";
 301    case FS_OPCODE_FB_WRITE_LOGICAL:
 302       return "fb_write_logical";
 303    case FS_OPCODE_PACK_STENCIL_REF:
 304       return "pack_stencil_ref";
 305    case FS_OPCODE_BLORP_FB_WRITE:
 306       return "blorp_fb_write";
 307    case FS_OPCODE_REP_FB_WRITE:
 308       return "rep_fb_write";
 309
 310    case SHADER_OPCODE_RCP:
 311       return "rcp";
 312    case SHADER_OPCODE_RSQ:
 313       return "rsq";
 314    case SHADER_OPCODE_SQRT:
 315       return "sqrt";
 316    case SHADER_OPCODE_EXP2:
 317       return "exp2";
 318    case SHADER_OPCODE_LOG2:
 319       return "log2";
 320    case SHADER_OPCODE_POW:
 321       return "pow";
 322    case SHADER_OPCODE_INT_QUOTIENT:
 323       return "int_quot";
 324    case SHADER_OPCODE_INT_REMAINDER:
 325       return "int_rem";
 326    case SHADER_OPCODE_SIN:
 327       return "sin";
 328    case SHADER_OPCODE_COS:
 329       return "cos";
 330
 331    case SHADER_OPCODE_TEX:
 332       return "tex";
 333    case SHADER_OPCODE_TEX_LOGICAL:
 334       return "tex_logical";
 335    case SHADER_OPCODE_TXD:
 336       return "txd";
 337    case SHADER_OPCODE_TXD_LOGICAL:
 338       return "txd_logical";
 339    case SHADER_OPCODE_TXF:
 340       return "txf";
 341    case SHADER_OPCODE_TXF_LOGICAL:
 342       return "txf_logical";
 343    case SHADER_OPCODE_TXL:
 344       return "txl";
 345    case SHADER_OPCODE_TXL_LOGICAL:
 346       return "txl_logical";
 347    case SHADER_OPCODE_TXS:
 348       return "txs";
 349    case SHADER_OPCODE_TXS_LOGICAL:
 350       return "txs_logical";
 351    case FS_OPCODE_TXB:
 352       return "txb";
 353    case FS_OPCODE_TXB_LOGICAL:
 354       return "txb_logical";
 355    case SHADER_OPCODE_TXF_CMS:
 356       return "txf_cms";
 357    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 358       return "txf_cms_logical";
 359    case SHADER_OPCODE_TXF_CMS_W:
 360       return "txf_cms_w";
 361    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 362       return "txf_cms_w_logical";
 363    case SHADER_OPCODE_TXF_UMS:
 364       return "txf_ums";
 365    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 366       return "txf_ums_logical";
 367    case SHADER_OPCODE_TXF_MCS:
 368       return "txf_mcs";
 369    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 370       return "txf_mcs_logical";
 371    case SHADER_OPCODE_LOD:
 372       return "lod";
 373    case SHADER_OPCODE_LOD_LOGICAL:
 374       return "lod_logical";
 375    case SHADER_OPCODE_TG4:
 376       return "tg4";
 377    case SHADER_OPCODE_TG4_LOGICAL:
 378       return "tg4_logical";
 379    case SHADER_OPCODE_TG4_OFFSET:
 380       return "tg4_offset";
 381    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 382       return "tg4_offset_logical";
 383    case SHADER_OPCODE_SAMPLEINFO:
 384       return "sampleinfo";
 385
 386    case SHADER_OPCODE_SHADER_TIME_ADD:
 387       return "shader_time_add";
 388
 389    case SHADER_OPCODE_UNTYPED_ATOMIC:
 390       return "untyped_atomic";
 391    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 392       return "untyped_atomic_logical";
 393    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 394       return "untyped_surface_read";
 395    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 396       return "untyped_surface_read_logical";
 397    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 398       return "untyped_surface_write";
 399    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 400       return "untyped_surface_write_logical";
 401    case SHADER_OPCODE_TYPED_ATOMIC:
 402       return "typed_atomic";
 403    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 404       return "typed_atomic_logical";
 405    case SHADER_OPCODE_TYPED_SURFACE_READ:
 406       return "typed_surface_read";
 407    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 408       return "typed_surface_read_logical";
 409    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 410       return "typed_surface_write";
 411    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 412       return "typed_surface_write_logical";
 413    case SHADER_OPCODE_MEMORY_FENCE:
 414       return "memory_fence";
 415
 416    case SHADER_OPCODE_LOAD_PAYLOAD:
 417       return "load_payload";
 418
 419    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 420       return "gen4_scratch_read";
 421    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 422       return "gen4_scratch_write";
 423    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 424       return "gen7_scratch_read";
 425    case SHADER_OPCODE_URB_WRITE_SIMD8:
 426       return "gen8_urb_write_simd8";
 427    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 428       return "gen8_urb_write_simd8_per_slot";
 429    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 430       return "gen8_urb_write_simd8_masked";
 431    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 432       return "gen8_urb_write_simd8_masked_per_slot";
 433    case SHADER_OPCODE_URB_READ_SIMD8:
 434       return "urb_read_simd8";
 435    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 436       return "urb_read_simd8_per_slot";
 437
 438    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 439       return "find_live_channel";
 440    case SHADER_OPCODE_BROADCAST:
 441       return "broadcast";
 442
 443    case VEC4_OPCODE_MOV_BYTES:
 444       return "mov_bytes";
 445    case VEC4_OPCODE_PACK_BYTES:
 446       return "pack_bytes";
 447    case VEC4_OPCODE_UNPACK_UNIFORM:
 448       return "unpack_uniform";
 449
 450    case FS_OPCODE_DDX_COARSE:
 451       return "ddx_coarse";
 452    case FS_OPCODE_DDX_FINE:
 453       return "ddx_fine";
 454    case FS_OPCODE_DDY_COARSE:
 455       return "ddy_coarse";
 456    case FS_OPCODE_DDY_FINE:
 457       return "ddy_fine";
 458
 459    case FS_OPCODE_CINTERP:
 460       return "cinterp";
 461    case FS_OPCODE_LINTERP:
 462       return "linterp";
 463
 464    case FS_OPCODE_PIXEL_X:
 465       return "pixel_x";
 466    case FS_OPCODE_PIXEL_Y:
 467       return "pixel_y";
 468
 469    case FS_OPCODE_GET_BUFFER_SIZE:
 470       return "fs_get_buffer_size";
 471
 472    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 473       return "uniform_pull_const";
 474    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 475       return "uniform_pull_const_gen7";
 476    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 477       return "varying_pull_const";
 478    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 479       return "varying_pull_const_gen7";
 480
 481    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 482       return "mov_dispatch_to_flags";
 483    case FS_OPCODE_DISCARD_JUMP:
 484       return "discard_jump";
 485
 486    case FS_OPCODE_SET_SAMPLE_ID:
 487       return "set_sample_id";
 488    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 489       return "set_simd4x2_offset";
 490
 491    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 492       return "pack_half_2x16_split";
 493    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 494       return "unpack_half_2x16_split_x";
 495    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 496       return "unpack_half_2x16_split_y";
 497
 498    case FS_OPCODE_PLACEHOLDER_HALT:
 499       return "placeholder_halt";
 500
 501    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 502       return "interp_centroid";
 503    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 504       return "interp_sample";
 505    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 506       return "interp_shared_offset";
 507    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 508       return "interp_per_slot_offset";
 509
 510    case VS_OPCODE_URB_WRITE:
 511       return "vs_urb_write";
 512    case VS_OPCODE_PULL_CONSTANT_LOAD:
 513       return "pull_constant_load";
 514    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 515       return "pull_constant_load_gen7";
 516
 517    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 518       return "set_simd4x2_header_gen9";
 519
 520    case VS_OPCODE_GET_BUFFER_SIZE:
 521       return "vs_get_buffer_size";
 522
 523    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 524       return "unpack_flags_simd4x2";
 525
 526    case GS_OPCODE_URB_WRITE:
 527       return "gs_urb_write";
 528    case GS_OPCODE_URB_WRITE_ALLOCATE:
 529       return "gs_urb_write_allocate";
 530    case GS_OPCODE_THREAD_END:
 531       return "gs_thread_end";
 532    case GS_OPCODE_SET_WRITE_OFFSET:
 533       return "set_write_offset";
 534    case GS_OPCODE_SET_VERTEX_COUNT:
 535       return "set_vertex_count";
 536    case GS_OPCODE_SET_DWORD_2:
 537       return "set_dword_2";
 538    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 539       return "prepare_channel_masks";
 540    case GS_OPCODE_SET_CHANNEL_MASKS:
 541       return "set_channel_masks";
 542    case GS_OPCODE_GET_INSTANCE_ID:
 543       return "get_instance_id";
 544    case GS_OPCODE_FF_SYNC:
 545       return "ff_sync";
 546    case GS_OPCODE_SET_PRIMITIVE_ID:
 547       return "set_primitive_id";
 548    case GS_OPCODE_SVB_WRITE:
 549       return "gs_svb_write";
 550    case GS_OPCODE_SVB_SET_DST_INDEX:
 551       return "gs_svb_set_dst_index";
 552    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 553       return "gs_ff_sync_set_primitives";
 554    case CS_OPCODE_CS_TERMINATE:
 555       return "cs_terminate";
 556    case SHADER_OPCODE_BARRIER:
 557       return "barrier";
 558    case SHADER_OPCODE_MULH:
 559       return "mulh";
 560    }
 561
 562    unreachable("not reached");
 563 }
 564
 565 bool
 566 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 567 {
 568    union {
 569       unsigned ud;
 570       int d;
 571       float f;
 572    } imm = { reg->ud }, sat_imm = { 0 };
 573
 574    switch (type) {
 575    case BRW_REGISTER_TYPE_UD:
 576    case BRW_REGISTER_TYPE_D:
 577    case BRW_REGISTER_TYPE_UQ:
 578    case BRW_REGISTER_TYPE_Q:
 579       /* Nothing to do. */
 580       return false;
 581    case BRW_REGISTER_TYPE_UW:
 582       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 583       break;
 584    case BRW_REGISTER_TYPE_W:
 585       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 586       break;
 587    case BRW_REGISTER_TYPE_F:
 588       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 589       break;
 590    case BRW_REGISTER_TYPE_UB:
 591    case BRW_REGISTER_TYPE_B:
 592       unreachable("no UB/B immediates");
 593    case BRW_REGISTER_TYPE_V:
 594    case BRW_REGISTER_TYPE_UV:
 595    case BRW_REGISTER_TYPE_VF:
 596       unreachable("unimplemented: saturate vector immediate");
 597    case BRW_REGISTER_TYPE_DF:
 598    case BRW_REGISTER_TYPE_HF:
 599       unreachable("unimplemented: saturate DF/HF immediate");
 600    }
 601
 602    if (imm.ud != sat_imm.ud) {
 603       reg->ud = sat_imm.ud;
 604       return true;
 605    }
 606    return false;
 607 }
 608
 609 bool
 610 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 611 {
 612    switch (type) {
 613    case BRW_REGISTER_TYPE_D:
 614    case BRW_REGISTER_TYPE_UD:
 615       reg->d = -reg->d;
 616       return true;
 617    case BRW_REGISTER_TYPE_W:
 618    case BRW_REGISTER_TYPE_UW:
 619       reg->d = -(int16_t)reg->ud;
 620       return true;
 621    case BRW_REGISTER_TYPE_F:
 622       reg->f = -reg->f;
 623       return true;
 624    case BRW_REGISTER_TYPE_VF:
 625       reg->ud ^= 0x80808080;
 626       return true;
 627    case BRW_REGISTER_TYPE_UB:
 628    case BRW_REGISTER_TYPE_B:
 629       unreachable("no UB/B immediates");
 630    case BRW_REGISTER_TYPE_UV:
 631    case BRW_REGISTER_TYPE_V:
 632       assert(!"unimplemented: negate UV/V immediate");
 633    case BRW_REGISTER_TYPE_UQ:
 634    case BRW_REGISTER_TYPE_Q:
 635       assert(!"unimplemented: negate UQ/Q immediate");
 636    case BRW_REGISTER_TYPE_DF:
 637    case BRW_REGISTER_TYPE_HF:
 638       assert(!"unimplemented: negate DF/HF immediate");
 639    }
 640
 641    return false;
 642 }
 643
 644 bool
 645 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 646 {
 647    switch (type) {
 648    case BRW_REGISTER_TYPE_D:
 649       reg->d = abs(reg->d);
 650       return true;
 651    case BRW_REGISTER_TYPE_W:
 652       reg->d = abs((int16_t)reg->ud);
 653       return true;
 654    case BRW_REGISTER_TYPE_F:
 655       reg->f = fabsf(reg->f);
 656       return true;
 657    case BRW_REGISTER_TYPE_VF:
 658       reg->ud &= ~0x80808080;
 659       return true;
 660    case BRW_REGISTER_TYPE_UB:
 661    case BRW_REGISTER_TYPE_B:
 662       unreachable("no UB/B immediates");
 663    case BRW_REGISTER_TYPE_UQ:
 664    case BRW_REGISTER_TYPE_UD:
 665    case BRW_REGISTER_TYPE_UW:
 666    case BRW_REGISTER_TYPE_UV:
 667       /* Presumably the absolute value modifier on an unsigned source is a
 668        * nop, but it would be nice to confirm.
 669        */
 670       assert(!"unimplemented: abs unsigned immediate");
 671    case BRW_REGISTER_TYPE_V:
 672       assert(!"unimplemented: abs V immediate");
 673    case BRW_REGISTER_TYPE_Q:
 674       assert(!"unimplemented: abs Q immediate");
 675    case BRW_REGISTER_TYPE_DF:
 676    case BRW_REGISTER_TYPE_HF:
 677       assert(!"unimplemented: abs DF/HF immediate");
 678    }
 679
 680    return false;
 681 }
 682
 683 backend_shader::backend_shader(const struct brw_compiler *compiler,
 684                                void *log_data,
 685                                void *mem_ctx,
 686                                const nir_shader *shader,
 687                                struct brw_stage_prog_data *stage_prog_data)
 688    : compiler(compiler),
 689      log_data(log_data),
 690      devinfo(compiler->devinfo),
 691      nir(shader),
 692      stage_prog_data(stage_prog_data),
 693      mem_ctx(mem_ctx),
 694      cfg(NULL),
 695      stage(shader->stage)
 696 {
 697    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 698    stage_name = _mesa_shader_stage_to_string(stage);
 699    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 700 }
 701
 702 bool
 703 backend_reg::is_zero() const
 704 {
 705    if (file != IMM)
 706       return false;
 707
 708    return d == 0;
 709 }
 710
 711 bool
 712 backend_reg::is_one() const
 713 {
 714    if (file != IMM)
 715       return false;
 716
 717    return type == BRW_REGISTER_TYPE_F
 718           ? f == 1.0
 719           : d == 1;
 720 }
 721
 722 bool
 723 backend_reg::is_negative_one() const
 724 {
 725    if (file != IMM)
 726       return false;
 727
 728    switch (type) {
 729    case BRW_REGISTER_TYPE_F:
 730       return f == -1.0;
 731    case BRW_REGISTER_TYPE_D:
 732       return d == -1;
 733    default:
 734       return false;
 735    }
 736 }
 737
 738 bool
 739 backend_reg::is_null() const
 740 {
 741    return file == ARF && nr == BRW_ARF_NULL;
 742 }
 743
 744
 745 bool
 746 backend_reg::is_accumulator() const
 747 {
 748    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 749 }
 750
 751 bool
 752 backend_reg::in_range(const backend_reg &r, unsigned n) const
 753 {
 754    return (file == r.file &&
 755            nr == r.nr &&
 756            reg_offset >= r.reg_offset &&
 757            reg_offset < r.reg_offset + n);
 758 }
 759
 760 bool
 761 backend_instruction::is_commutative() const
 762 {
 763    switch (opcode) {
 764    case BRW_OPCODE_AND:
 765    case BRW_OPCODE_OR:
 766    case BRW_OPCODE_XOR:
 767    case BRW_OPCODE_ADD:
 768    case BRW_OPCODE_MUL:
 769    case SHADER_OPCODE_MULH:
 770       return true;
 771    case BRW_OPCODE_SEL:
 772       /* MIN and MAX are commutative. */
 773       if (conditional_mod == BRW_CONDITIONAL_GE ||
 774           conditional_mod == BRW_CONDITIONAL_L) {
 775          return true;
 776       }
 777       /* fallthrough */
 778    default:
 779       return false;
 780    }
 781 }
 782
 783 bool
 784 backend_instruction::is_3src() const
 785 {
 786    return ::is_3src(opcode);
 787 }
 788
 789 bool
 790 backend_instruction::is_tex() const
 791 {
 792    return (opcode == SHADER_OPCODE_TEX ||
 793            opcode == FS_OPCODE_TXB ||
 794            opcode == SHADER_OPCODE_TXD ||
 795            opcode == SHADER_OPCODE_TXF ||
 796            opcode == SHADER_OPCODE_TXF_CMS ||
 797            opcode == SHADER_OPCODE_TXF_CMS_W ||
 798            opcode == SHADER_OPCODE_TXF_UMS ||
 799            opcode == SHADER_OPCODE_TXF_MCS ||
 800            opcode == SHADER_OPCODE_TXL ||
 801            opcode == SHADER_OPCODE_TXS ||
 802            opcode == SHADER_OPCODE_LOD ||
 803            opcode == SHADER_OPCODE_TG4 ||
 804            opcode == SHADER_OPCODE_TG4_OFFSET);
 805 }
 806
 807 bool
 808 backend_instruction::is_math() const
 809 {
 810    return (opcode == SHADER_OPCODE_RCP ||
 811            opcode == SHADER_OPCODE_RSQ ||
 812            opcode == SHADER_OPCODE_SQRT ||
 813            opcode == SHADER_OPCODE_EXP2 ||
 814            opcode == SHADER_OPCODE_LOG2 ||
 815            opcode == SHADER_OPCODE_SIN ||
 816            opcode == SHADER_OPCODE_COS ||
 817            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 818            opcode == SHADER_OPCODE_INT_REMAINDER ||
 819            opcode == SHADER_OPCODE_POW);
 820 }
 821
 822 bool
 823 backend_instruction::is_control_flow() const
 824 {
 825    switch (opcode) {
 826    case BRW_OPCODE_DO:
 827    case BRW_OPCODE_WHILE:
 828    case BRW_OPCODE_IF:
 829    case BRW_OPCODE_ELSE:
 830    case BRW_OPCODE_ENDIF:
 831    case BRW_OPCODE_BREAK:
 832    case BRW_OPCODE_CONTINUE:
 833       return true;
 834    default:
 835       return false;
 836    }
 837 }
 838
 839 bool
 840 backend_instruction::can_do_source_mods() const
 841 {
 842    switch (opcode) {
 843    case BRW_OPCODE_ADDC:
 844    case BRW_OPCODE_BFE:
 845    case BRW_OPCODE_BFI1:
 846    case BRW_OPCODE_BFI2:
 847    case BRW_OPCODE_BFREV:
 848    case BRW_OPCODE_CBIT:
 849    case BRW_OPCODE_FBH:
 850    case BRW_OPCODE_FBL:
 851    case BRW_OPCODE_SUBB:
 852       return false;
 853    default:
 854       return true;
 855    }
 856 }
 857
 858 bool
 859 backend_instruction::can_do_saturate() const
 860 {
 861    switch (opcode) {
 862    case BRW_OPCODE_ADD:
 863    case BRW_OPCODE_ASR:
 864    case BRW_OPCODE_AVG:
 865    case BRW_OPCODE_DP2:
 866    case BRW_OPCODE_DP3:
 867    case BRW_OPCODE_DP4:
 868    case BRW_OPCODE_DPH:
 869    case BRW_OPCODE_F16TO32:
 870    case BRW_OPCODE_F32TO16:
 871    case BRW_OPCODE_LINE:
 872    case BRW_OPCODE_LRP:
 873    case BRW_OPCODE_MAC:
 874    case BRW_OPCODE_MAD:
 875    case BRW_OPCODE_MATH:
 876    case BRW_OPCODE_MOV:
 877    case BRW_OPCODE_MUL:
 878    case SHADER_OPCODE_MULH:
 879    case BRW_OPCODE_PLN:
 880    case BRW_OPCODE_RNDD:
 881    case BRW_OPCODE_RNDE:
 882    case BRW_OPCODE_RNDU:
 883    case BRW_OPCODE_RNDZ:
 884    case BRW_OPCODE_SEL:
 885    case BRW_OPCODE_SHL:
 886    case BRW_OPCODE_SHR:
 887    case FS_OPCODE_LINTERP:
 888    case SHADER_OPCODE_COS:
 889    case SHADER_OPCODE_EXP2:
 890    case SHADER_OPCODE_LOG2:
 891    case SHADER_OPCODE_POW:
 892    case SHADER_OPCODE_RCP:
 893    case SHADER_OPCODE_RSQ:
 894    case SHADER_OPCODE_SIN:
 895    case SHADER_OPCODE_SQRT:
 896       return true;
 897    default:
 898       return false;
 899    }
 900 }
 901
 902 bool
 903 backend_instruction::can_do_cmod() const
 904 {
 905    switch (opcode) {
 906    case BRW_OPCODE_ADD:
 907    case BRW_OPCODE_ADDC:
 908    case BRW_OPCODE_AND:
 909    case BRW_OPCODE_ASR:
 910    case BRW_OPCODE_AVG:
 911    case BRW_OPCODE_CMP:
 912    case BRW_OPCODE_CMPN:
 913    case BRW_OPCODE_DP2:
 914    case BRW_OPCODE_DP3:
 915    case BRW_OPCODE_DP4:
 916    case BRW_OPCODE_DPH:
 917    case BRW_OPCODE_F16TO32:
 918    case BRW_OPCODE_F32TO16:
 919    case BRW_OPCODE_FRC:
 920    case BRW_OPCODE_LINE:
 921    case BRW_OPCODE_LRP:
 922    case BRW_OPCODE_LZD:
 923    case BRW_OPCODE_MAC:
 924    case BRW_OPCODE_MACH:
 925    case BRW_OPCODE_MAD:
 926    case BRW_OPCODE_MOV:
 927    case BRW_OPCODE_MUL:
 928    case BRW_OPCODE_NOT:
 929    case BRW_OPCODE_OR:
 930    case BRW_OPCODE_PLN:
 931    case BRW_OPCODE_RNDD:
 932    case BRW_OPCODE_RNDE:
 933    case BRW_OPCODE_RNDU:
 934    case BRW_OPCODE_RNDZ:
 935    case BRW_OPCODE_SAD2:
 936    case BRW_OPCODE_SADA2:
 937    case BRW_OPCODE_SHL:
 938    case BRW_OPCODE_SHR:
 939    case BRW_OPCODE_SUBB:
 940    case BRW_OPCODE_XOR:
 941    case FS_OPCODE_CINTERP:
 942    case FS_OPCODE_LINTERP:
 943       return true;
 944    default:
 945       return false;
 946    }
 947 }
 948
 949 bool
 950 backend_instruction::reads_accumulator_implicitly() const
 951 {
 952    switch (opcode) {
 953    case BRW_OPCODE_MAC:
 954    case BRW_OPCODE_MACH:
 955    case BRW_OPCODE_SADA2:
 956       return true;
 957    default:
 958       return false;
 959    }
 960 }
 961
 962 bool
 963 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 964 {
 965    return writes_accumulator ||
 966           (devinfo->gen < 6 &&
 967            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 968             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 969              opcode != FS_OPCODE_CINTERP)));
 970 }
 971
 972 bool
 973 backend_instruction::has_side_effects() const
 974 {
 975    switch (opcode) {
 976    case SHADER_OPCODE_UNTYPED_ATOMIC:
 977    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 978    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 979    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 980    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 981    case SHADER_OPCODE_TYPED_ATOMIC:
 982    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 983    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 984    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 985    case SHADER_OPCODE_MEMORY_FENCE:
 986    case SHADER_OPCODE_URB_WRITE_SIMD8:
 987    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 988    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 989    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 990    case FS_OPCODE_FB_WRITE:
 991    case SHADER_OPCODE_BARRIER:
 992       return true;
 993    default:
 994       return false;
 995    }
 996 }
 997
 998 bool
 999 backend_instruction::is_volatile() const
1000 {
1001    switch (opcode) {
1002    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1003    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1004    case SHADER_OPCODE_TYPED_SURFACE_READ:
1005    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1006       return true;
1007    default:
1008       return false;
1009    }
1010 }
1011
1012 #ifndef NDEBUG
1013 static bool
1014 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1015 {
1016    bool found = false;
1017    foreach_inst_in_block (backend_instruction, i, block) {
1018       if (inst == i) {
1019          found = true;
1020       }
1021    }
1022    return found;
1023 }
1024 #endif
1025
1026 static void
1027 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1028 {
1029    for (bblock_t *block_iter = start_block->next();
1030         !block_iter->link.is_tail_sentinel();
1031         block_iter = block_iter->next()) {
1032       block_iter->start_ip += ip_adjustment;
1033       block_iter->end_ip += ip_adjustment;
1034    }
1035 }
1036
1037 void
1038 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1039 {
1040    if (!this->is_head_sentinel())
1041       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1042
1043    block->end_ip++;
1044
1045    adjust_later_block_ips(block, 1);
1046
1047    exec_node::insert_after(inst);
1048 }
1049
1050 void
1051 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1052 {
1053    if (!this->is_tail_sentinel())
1054       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1055
1056    block->end_ip++;
1057
1058    adjust_later_block_ips(block, 1);
1059
1060    exec_node::insert_before(inst);
1061 }
1062
1063 void
1064 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1065 {
1066    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    unsigned num_inst = list->length();
1069
1070    block->end_ip += num_inst;
1071
1072    adjust_later_block_ips(block, num_inst);
1073
1074    exec_node::insert_before(list);
1075 }
1076
1077 void
1078 backend_instruction::remove(bblock_t *block)
1079 {
1080    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1081
1082    adjust_later_block_ips(block, -1);
1083
1084    if (block->start_ip == block->end_ip) {
1085       block->cfg->remove_block(block);
1086    } else {
1087       block->end_ip--;
1088    }
1089
1090    exec_node::remove();
1091 }
1092
1093 void
1094 backend_shader::dump_instructions()
1095 {
1096    dump_instructions(NULL);
1097 }
1098
1099 void
1100 backend_shader::dump_instructions(const char *name)
1101 {
1102    FILE *file = stderr;
1103    if (name && geteuid() != 0) {
1104       file = fopen(name, "w");
1105       if (!file)
1106          file = stderr;
1107    }
1108
1109    if (cfg) {
1110       int ip = 0;
1111       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1112          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1113             fprintf(file, "%4d: ", ip++);
1114          dump_instruction(inst, file);
1115       }
1116    } else {
1117       int ip = 0;
1118       foreach_in_list(backend_instruction, inst, &instructions) {
1119          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1120             fprintf(file, "%4d: ", ip++);
1121          dump_instruction(inst, file);
1122       }
1123    }
1124
1125    if (file != stderr) {
1126       fclose(file);
1127    }
1128 }
1129
1130 void
1131 backend_shader::calculate_cfg()
1132 {
1133    if (this->cfg)
1134       return;
1135    cfg = new(mem_ctx) cfg_t(&this->instructions);
1136 }
1137
1138 void
1139 backend_shader::invalidate_cfg()
1140 {
1141    ralloc_free(this->cfg);
1142    this->cfg = NULL;
1143 }
1144
1145 /**
1146  * Sets up the starting offsets for the groups of binding table entries
1147  * commong to all pipeline stages.
1148  *
1149  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1150  * unused but also make sure that addition of small offsets to them will
1151  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1152  */
1153 void
1154 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1155                                         const struct brw_device_info *devinfo,
1156                                         const struct gl_shader_program *shader_prog,
1157                                         const struct gl_program *prog,
1158                                         struct brw_stage_prog_data *stage_prog_data,
1159                                         uint32_t next_binding_table_offset)
1160 {
1161    const struct gl_shader *shader = NULL;
1162    int num_textures = _mesa_fls(prog->SamplersUsed);
1163
1164    if (shader_prog)
1165       shader = shader_prog->_LinkedShaders[stage];
1166
1167    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1168    next_binding_table_offset += num_textures;
1169
1170    if (shader) {
1171       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1172       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1173       next_binding_table_offset += shader->NumUniformBlocks;
1174
1175       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1176       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1177       next_binding_table_offset += shader->NumShaderStorageBlocks;
1178    } else {
1179       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1180       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1181    }
1182
1183    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1184       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1185       next_binding_table_offset++;
1186    } else {
1187       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1188    }
1189
1190    if (prog->UsesGather) {
1191       if (devinfo->gen >= 8) {
1192          stage_prog_data->binding_table.gather_texture_start =
1193             stage_prog_data->binding_table.texture_start;
1194       } else {
1195          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1196          next_binding_table_offset += num_textures;
1197       }
1198    } else {
1199       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1200    }
1201
1202    if (shader && shader->NumAtomicBuffers) {
1203       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1204       next_binding_table_offset += shader->NumAtomicBuffers;
1205    } else {
1206       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1207    }
1208
1209    if (shader && shader->NumImages) {
1210       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1211       next_binding_table_offset += shader->NumImages;
1212    } else {
1213       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1214    }
1215
1216    /* This may or may not be used depending on how the compile goes. */
1217    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1218    next_binding_table_offset++;
1219
1220    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1221
1222    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1223 }
1224
1225 static void
1226 setup_vec4_uniform_value(const gl_constant_value **params,
1227                          const gl_constant_value *values,
1228                          unsigned n)
1229 {
1230    static const gl_constant_value zero = { 0 };
1231
1232    for (unsigned i = 0; i < n; ++i)
1233       params[i] = &values[i];
1234
1235    for (unsigned i = n; i < 4; ++i)
1236       params[i] = &zero;
1237 }
1238
1239 void
1240 brw_setup_image_uniform_values(gl_shader_stage stage,
1241                                struct brw_stage_prog_data *stage_prog_data,
1242                                unsigned param_start_index,
1243                                const gl_uniform_storage *storage)
1244 {
1245    const gl_constant_value **param =
1246       &stage_prog_data->param[param_start_index];
1247
1248    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1249       const unsigned image_idx = storage->opaque[stage].index + i;
1250       const brw_image_param *image_param =
1251          &stage_prog_data->image_param[image_idx];
1252
1253       /* Upload the brw_image_param structure.  The order is expected to match
1254        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1255        */
1256       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1257          (const gl_constant_value *)&image_param->surface_idx, 1);
1258       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1259          (const gl_constant_value *)image_param->offset, 2);
1260       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1261          (const gl_constant_value *)image_param->size, 3);
1262       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1263          (const gl_constant_value *)image_param->stride, 4);
1264       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1265          (const gl_constant_value *)image_param->tiling, 3);
1266       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1267          (const gl_constant_value *)image_param->swizzling, 2);
1268       param += BRW_IMAGE_PARAM_SIZE;
1269
1270       brw_mark_surface_used(
1271          stage_prog_data,
1272          stage_prog_data->binding_table.image_start + image_idx);
1273    }
1274 }
1275
1276 /**
1277  * Decide which set of clip planes should be used when clipping via
1278  * gl_Position or gl_ClipVertex.
1279  */
1280 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1281 {
1282    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1283       /* There is currently a GLSL vertex shader, so clip according to GLSL
1284        * rules, which means compare gl_ClipVertex (or gl_Position, if
1285        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1286        * that were stored in EyeUserPlane at the time the clip planes were
1287        * specified.
1288        */
1289       return ctx->Transform.EyeUserPlane;
1290    } else {
1291       /* Either we are using fixed function or an ARB vertex program.  In
1292        * either case the clip planes are going to be compared against
1293        * gl_Position (which is in clip coordinates) so we have to clip using
1294        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1295        * core.
1296        */
1297       return ctx->Transform._ClipUserPlane;
1298    }
1299 }
1300