2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/macros.h"
26 #include "brw_context.h"
29 #include "brw_vec4_gs.h"
32 #include "glsl/ir_optimization.h"
33 #include "glsl/glsl_parser_extras.h"
34 #include "main/shaderapi.h"
37 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
39 struct brw_shader
*shader
;
41 shader
= rzalloc(NULL
, struct brw_shader
);
43 shader
->base
.Type
= type
;
44 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
45 shader
->base
.Name
= name
;
46 _mesa_init_shader(ctx
, &shader
->base
);
53 * Performs a compile of the shader stages even when we don't know
54 * what non-orthogonal state will be set, in the hope that it reflects
55 * the eventual NOS used, and thus allows us to produce link failures.
58 brw_shader_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
60 struct brw_context
*brw
= brw_context(ctx
);
62 if (brw
->precompile
&& !brw_fs_precompile(ctx
, prog
))
65 if (brw
->precompile
&& !brw_gs_precompile(ctx
, prog
))
68 if (brw
->precompile
&& !brw_vs_precompile(ctx
, prog
))
75 brw_lower_packing_builtins(struct brw_context
*brw
,
76 gl_shader_stage shader_type
,
79 int ops
= LOWER_PACK_SNORM_2x16
80 | LOWER_UNPACK_SNORM_2x16
81 | LOWER_PACK_UNORM_2x16
82 | LOWER_UNPACK_UNORM_2x16
83 | LOWER_PACK_SNORM_4x8
84 | LOWER_UNPACK_SNORM_4x8
85 | LOWER_PACK_UNORM_4x8
86 | LOWER_UNPACK_UNORM_4x8
;
89 /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
90 * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
91 * lowering is needed. For SOA code, the Half2x16 ops must be
94 if (shader_type
== MESA_SHADER_FRAGMENT
) {
95 ops
|= LOWER_PACK_HALF_2x16_TO_SPLIT
96 | LOWER_UNPACK_HALF_2x16_TO_SPLIT
;
99 ops
|= LOWER_PACK_HALF_2x16
100 | LOWER_UNPACK_HALF_2x16
;
103 lower_packing_builtins(ir
, ops
);
107 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*shProg
)
109 struct brw_context
*brw
= brw_context(ctx
);
112 for (stage
= 0; stage
< ARRAY_SIZE(shProg
->_LinkedShaders
); stage
++) {
113 const struct gl_shader_compiler_options
*options
=
114 &ctx
->Const
.ShaderCompilerOptions
[stage
];
115 struct brw_shader
*shader
=
116 (struct brw_shader
*)shProg
->_LinkedShaders
[stage
];
121 struct gl_program
*prog
=
122 ctx
->Driver
.NewProgram(ctx
, _mesa_shader_stage_to_program(stage
),
126 prog
->Parameters
= _mesa_new_parameter_list();
128 _mesa_copy_linked_program_data((gl_shader_stage
) stage
, shProg
, prog
);
132 /* lower_packing_builtins() inserts arithmetic instructions, so it
133 * must precede lower_instructions().
135 brw_lower_packing_builtins(brw
, (gl_shader_stage
) stage
, shader
->base
.ir
);
136 do_mat_op_to_vec(shader
->base
.ir
);
137 const int bitfield_insert
= brw
->gen
>= 7
138 ? BITFIELD_INSERT_TO_BFM_BFI
140 lower_instructions(shader
->base
.ir
,
149 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
150 * if-statements need to be flattened.
153 lower_if_to_cond_assign(shader
->base
.ir
, 16);
155 do_lower_texture_projection(shader
->base
.ir
);
156 brw_lower_texture_gradients(brw
, shader
->base
.ir
);
157 do_vec_index_to_cond_assign(shader
->base
.ir
);
158 lower_vector_insert(shader
->base
.ir
, true);
159 brw_do_cubemap_normalize(shader
->base
.ir
);
160 lower_offset_arrays(shader
->base
.ir
);
161 brw_do_lower_unnormalized_offset(shader
->base
.ir
);
162 lower_noise(shader
->base
.ir
);
163 lower_quadop_vector(shader
->base
.ir
, false);
165 bool lowered_variable_indexing
=
166 lower_variable_index_to_cond_assign(shader
->base
.ir
,
167 options
->EmitNoIndirectInput
,
168 options
->EmitNoIndirectOutput
,
169 options
->EmitNoIndirectTemp
,
170 options
->EmitNoIndirectUniform
);
172 if (unlikely(brw
->perf_debug
&& lowered_variable_indexing
)) {
173 perf_debug("Unsupported form of variable indexing in FS; falling "
174 "back to very inefficient code generation\n");
177 lower_ubo_reference(&shader
->base
, shader
->base
.ir
);
182 if (stage
== MESA_SHADER_FRAGMENT
) {
183 brw_do_channel_expressions(shader
->base
.ir
);
184 brw_do_vector_splitting(shader
->base
.ir
);
187 progress
= do_lower_jumps(shader
->base
.ir
, true, true,
188 true, /* main return */
189 false, /* continue */
193 progress
= do_common_optimization(shader
->base
.ir
, true, true,
194 options
, ctx
->Const
.NativeIntegers
)
198 /* Make a pass over the IR to add state references for any built-in
199 * uniforms that are used. This has to be done now (during linking).
200 * Code generation doesn't happen until the first time this shader is
201 * used for rendering. Waiting until then to generate the parameters is
202 * too late. At that point, the values for the built-in uniforms won't
203 * get sent to the shader.
205 foreach_in_list(ir_instruction
, node
, shader
->base
.ir
) {
206 ir_variable
*var
= node
->as_variable();
208 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
209 || (strncmp(var
->name
, "gl_", 3) != 0))
212 const ir_state_slot
*const slots
= var
->get_state_slots();
213 assert(slots
!= NULL
);
215 for (unsigned int i
= 0; i
< var
->get_num_state_slots(); i
++) {
216 _mesa_add_state_reference(prog
->Parameters
,
217 (gl_state_index
*) slots
[i
].tokens
);
221 validate_ir_tree(shader
->base
.ir
);
223 do_set_program_inouts(shader
->base
.ir
, prog
, shader
->base
.Stage
);
225 prog
->SamplersUsed
= shader
->base
.active_samplers
;
226 _mesa_update_shader_textures_used(shProg
, prog
);
228 _mesa_reference_program(ctx
, &shader
->base
.Program
, prog
);
230 brw_add_texrect_params(prog
);
232 _mesa_reference_program(ctx
, &prog
, NULL
);
234 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
235 fprintf(stderr
, "\n");
236 fprintf(stderr
, "GLSL IR for linked %s program %d:\n",
237 _mesa_shader_stage_to_string(shader
->base
.Stage
),
239 _mesa_print_ir(stderr
, shader
->base
.ir
, NULL
);
240 fprintf(stderr
, "\n");
244 if ((ctx
->_Shader
->Flags
& GLSL_DUMP
) && shProg
->Name
!= 0) {
245 for (unsigned i
= 0; i
< shProg
->NumShaders
; i
++) {
246 const struct gl_shader
*sh
= shProg
->Shaders
[i
];
250 fprintf(stderr
, "GLSL %s shader %d source for linked program %d:\n",
251 _mesa_shader_stage_to_string(sh
->Stage
),
253 fprintf(stderr
, "%s", sh
->Source
);
254 fprintf(stderr
, "\n");
258 if (!brw_shader_precompile(ctx
, shProg
))
266 brw_type_for_base_type(const struct glsl_type
*type
)
268 switch (type
->base_type
) {
269 case GLSL_TYPE_FLOAT
:
270 return BRW_REGISTER_TYPE_F
;
272 return BRW_REGISTER_TYPE_D
;
275 return BRW_REGISTER_TYPE_UD
;
276 case GLSL_TYPE_ARRAY
:
277 return brw_type_for_base_type(type
->fields
.array
);
278 case GLSL_TYPE_STRUCT
:
279 case GLSL_TYPE_SAMPLER
:
280 case GLSL_TYPE_ATOMIC_UINT
:
281 /* These should be overridden with the type of the member when
282 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
283 * way to trip up if we don't.
285 return BRW_REGISTER_TYPE_UD
;
286 case GLSL_TYPE_IMAGE
:
287 return BRW_REGISTER_TYPE_UD
;
289 case GLSL_TYPE_ERROR
:
290 case GLSL_TYPE_INTERFACE
:
291 unreachable("not reached");
294 return BRW_REGISTER_TYPE_F
;
297 enum brw_conditional_mod
298 brw_conditional_for_comparison(unsigned int op
)
302 return BRW_CONDITIONAL_L
;
303 case ir_binop_greater
:
304 return BRW_CONDITIONAL_G
;
305 case ir_binop_lequal
:
306 return BRW_CONDITIONAL_LE
;
307 case ir_binop_gequal
:
308 return BRW_CONDITIONAL_GE
;
310 case ir_binop_all_equal
: /* same as equal for scalars */
311 return BRW_CONDITIONAL_Z
;
312 case ir_binop_nequal
:
313 case ir_binop_any_nequal
: /* same as nequal for scalars */
314 return BRW_CONDITIONAL_NZ
;
316 unreachable("not reached: bad operation for comparison");
321 brw_math_function(enum opcode op
)
324 case SHADER_OPCODE_RCP
:
325 return BRW_MATH_FUNCTION_INV
;
326 case SHADER_OPCODE_RSQ
:
327 return BRW_MATH_FUNCTION_RSQ
;
328 case SHADER_OPCODE_SQRT
:
329 return BRW_MATH_FUNCTION_SQRT
;
330 case SHADER_OPCODE_EXP2
:
331 return BRW_MATH_FUNCTION_EXP
;
332 case SHADER_OPCODE_LOG2
:
333 return BRW_MATH_FUNCTION_LOG
;
334 case SHADER_OPCODE_POW
:
335 return BRW_MATH_FUNCTION_POW
;
336 case SHADER_OPCODE_SIN
:
337 return BRW_MATH_FUNCTION_SIN
;
338 case SHADER_OPCODE_COS
:
339 return BRW_MATH_FUNCTION_COS
;
340 case SHADER_OPCODE_INT_QUOTIENT
:
341 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
342 case SHADER_OPCODE_INT_REMAINDER
:
343 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
345 unreachable("not reached: unknown math function");
350 brw_texture_offset(struct gl_context
*ctx
, int *offsets
,
351 unsigned num_components
)
353 /* If the driver does not support GL_ARB_gpu_shader5, the offset
356 assert(offsets
!= NULL
|| ctx
->Extensions
.ARB_gpu_shader5
);
358 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
360 /* Combine all three offsets into a single unsigned dword:
362 * bits 11:8 - U Offset (X component)
363 * bits 7:4 - V Offset (Y component)
364 * bits 3:0 - R Offset (Z component)
366 unsigned offset_bits
= 0;
367 for (unsigned i
= 0; i
< num_components
; i
++) {
368 const unsigned shift
= 4 * (2 - i
);
369 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
375 brw_instruction_name(enum opcode op
)
379 if (op
< ARRAY_SIZE(opcode_descs
) && opcode_descs
[op
].name
)
380 return opcode_descs
[op
].name
;
383 case FS_OPCODE_FB_WRITE
:
385 case FS_OPCODE_BLORP_FB_WRITE
:
386 return "blorp_fb_write";
388 case SHADER_OPCODE_RCP
:
390 case SHADER_OPCODE_RSQ
:
392 case SHADER_OPCODE_SQRT
:
394 case SHADER_OPCODE_EXP2
:
396 case SHADER_OPCODE_LOG2
:
398 case SHADER_OPCODE_POW
:
400 case SHADER_OPCODE_INT_QUOTIENT
:
402 case SHADER_OPCODE_INT_REMAINDER
:
404 case SHADER_OPCODE_SIN
:
406 case SHADER_OPCODE_COS
:
409 case SHADER_OPCODE_TEX
:
411 case SHADER_OPCODE_TXD
:
413 case SHADER_OPCODE_TXF
:
415 case SHADER_OPCODE_TXL
:
417 case SHADER_OPCODE_TXS
:
421 case SHADER_OPCODE_TXF_CMS
:
423 case SHADER_OPCODE_TXF_UMS
:
425 case SHADER_OPCODE_TXF_MCS
:
427 case SHADER_OPCODE_TG4
:
429 case SHADER_OPCODE_TG4_OFFSET
:
431 case SHADER_OPCODE_SHADER_TIME_ADD
:
432 return "shader_time_add";
434 case SHADER_OPCODE_LOAD_PAYLOAD
:
435 return "load_payload";
437 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
438 return "gen4_scratch_read";
439 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
440 return "gen4_scratch_write";
441 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
442 return "gen7_scratch_read";
449 case FS_OPCODE_PIXEL_X
:
451 case FS_OPCODE_PIXEL_Y
:
454 case FS_OPCODE_CINTERP
:
456 case FS_OPCODE_LINTERP
:
459 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
460 return "uniform_pull_const";
461 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
462 return "uniform_pull_const_gen7";
463 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
464 return "varying_pull_const";
465 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
466 return "varying_pull_const_gen7";
468 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
469 return "mov_dispatch_to_flags";
470 case FS_OPCODE_DISCARD_JUMP
:
471 return "discard_jump";
473 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
474 return "set_simd4x2_offset";
476 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
477 return "pack_half_2x16_split";
478 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
479 return "unpack_half_2x16_split_x";
480 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
481 return "unpack_half_2x16_split_y";
483 case FS_OPCODE_PLACEHOLDER_HALT
:
484 return "placeholder_halt";
486 case VS_OPCODE_URB_WRITE
:
487 return "vs_urb_write";
488 case VS_OPCODE_PULL_CONSTANT_LOAD
:
489 return "pull_constant_load";
490 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
491 return "pull_constant_load_gen7";
492 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
493 return "unpack_flags_simd4x2";
495 case GS_OPCODE_URB_WRITE
:
496 return "gs_urb_write";
497 case GS_OPCODE_URB_WRITE_ALLOCATE
:
498 return "gs_urb_write_allocate";
499 case GS_OPCODE_THREAD_END
:
500 return "gs_thread_end";
501 case GS_OPCODE_SET_WRITE_OFFSET
:
502 return "set_write_offset";
503 case GS_OPCODE_SET_VERTEX_COUNT
:
504 return "set_vertex_count";
505 case GS_OPCODE_SET_DWORD_2
:
506 return "set_dword_2";
507 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
508 return "prepare_channel_masks";
509 case GS_OPCODE_SET_CHANNEL_MASKS
:
510 return "set_channel_masks";
511 case GS_OPCODE_GET_INSTANCE_ID
:
512 return "get_instance_id";
513 case GS_OPCODE_FF_SYNC
:
515 case GS_OPCODE_SET_PRIMITIVE_ID
:
516 return "set_primitive_id";
517 case GS_OPCODE_SVB_WRITE
:
518 return "gs_svb_write";
519 case GS_OPCODE_SVB_SET_DST_INDEX
:
520 return "gs_svb_set_dst_index";
521 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
522 return "gs_ff_sync_set_primitives";
525 /* Yes, this leaks. It's in debug code, it should never occur, and if
526 * it does, you should just add the case to the list above.
528 asprintf(&fallback
, "op%d", op
);
533 backend_visitor::backend_visitor(struct brw_context
*brw
,
534 struct gl_shader_program
*shader_prog
,
535 struct gl_program
*prog
,
536 struct brw_stage_prog_data
*stage_prog_data
,
537 gl_shader_stage stage
)
541 (struct brw_shader
*)shader_prog
->_LinkedShaders
[stage
] : NULL
),
542 shader_prog(shader_prog
),
544 stage_prog_data(stage_prog_data
),
551 backend_reg::is_zero() const
556 return fixed_hw_reg
.dw1
.d
== 0;
560 backend_reg::is_one() const
565 return type
== BRW_REGISTER_TYPE_F
566 ? fixed_hw_reg
.dw1
.f
== 1.0
567 : fixed_hw_reg
.dw1
.d
== 1;
571 backend_reg::is_null() const
573 return file
== HW_REG
&&
574 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
575 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
580 backend_reg::is_accumulator() const
582 return file
== HW_REG
&&
583 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
584 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
588 backend_instruction::is_tex() const
590 return (opcode
== SHADER_OPCODE_TEX
||
591 opcode
== FS_OPCODE_TXB
||
592 opcode
== SHADER_OPCODE_TXD
||
593 opcode
== SHADER_OPCODE_TXF
||
594 opcode
== SHADER_OPCODE_TXF_CMS
||
595 opcode
== SHADER_OPCODE_TXF_UMS
||
596 opcode
== SHADER_OPCODE_TXF_MCS
||
597 opcode
== SHADER_OPCODE_TXL
||
598 opcode
== SHADER_OPCODE_TXS
||
599 opcode
== SHADER_OPCODE_LOD
||
600 opcode
== SHADER_OPCODE_TG4
||
601 opcode
== SHADER_OPCODE_TG4_OFFSET
);
605 backend_instruction::is_math() const
607 return (opcode
== SHADER_OPCODE_RCP
||
608 opcode
== SHADER_OPCODE_RSQ
||
609 opcode
== SHADER_OPCODE_SQRT
||
610 opcode
== SHADER_OPCODE_EXP2
||
611 opcode
== SHADER_OPCODE_LOG2
||
612 opcode
== SHADER_OPCODE_SIN
||
613 opcode
== SHADER_OPCODE_COS
||
614 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
615 opcode
== SHADER_OPCODE_INT_REMAINDER
||
616 opcode
== SHADER_OPCODE_POW
);
620 backend_instruction::is_control_flow() const
624 case BRW_OPCODE_WHILE
:
626 case BRW_OPCODE_ELSE
:
627 case BRW_OPCODE_ENDIF
:
628 case BRW_OPCODE_BREAK
:
629 case BRW_OPCODE_CONTINUE
:
637 backend_instruction::can_do_source_mods() const
640 case BRW_OPCODE_ADDC
:
642 case BRW_OPCODE_BFI1
:
643 case BRW_OPCODE_BFI2
:
644 case BRW_OPCODE_BFREV
:
645 case BRW_OPCODE_CBIT
:
648 case BRW_OPCODE_SUBB
:
656 backend_instruction::can_do_saturate() const
666 case BRW_OPCODE_F16TO32
:
667 case BRW_OPCODE_F32TO16
:
668 case BRW_OPCODE_LINE
:
671 case BRW_OPCODE_MACH
:
673 case BRW_OPCODE_MATH
:
677 case BRW_OPCODE_RNDD
:
678 case BRW_OPCODE_RNDE
:
679 case BRW_OPCODE_RNDU
:
680 case BRW_OPCODE_RNDZ
:
684 case FS_OPCODE_LINTERP
:
685 case SHADER_OPCODE_COS
:
686 case SHADER_OPCODE_EXP2
:
687 case SHADER_OPCODE_LOG2
:
688 case SHADER_OPCODE_POW
:
689 case SHADER_OPCODE_RCP
:
690 case SHADER_OPCODE_RSQ
:
691 case SHADER_OPCODE_SIN
:
692 case SHADER_OPCODE_SQRT
:
700 backend_instruction::reads_accumulator_implicitly() const
704 case BRW_OPCODE_MACH
:
705 case BRW_OPCODE_SADA2
:
713 backend_instruction::writes_accumulator_implicitly(struct brw_context
*brw
) const
715 return writes_accumulator
||
717 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
718 (opcode
>= FS_OPCODE_DDX
&& opcode
<= FS_OPCODE_LINTERP
&&
719 opcode
!= FS_OPCODE_CINTERP
)));
723 backend_instruction::has_side_effects() const
726 case SHADER_OPCODE_UNTYPED_ATOMIC
:
727 case FS_OPCODE_FB_WRITE
:
736 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
739 foreach_inst_in_block (backend_instruction
, i
, block
) {
749 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
751 for (bblock_t
*block_iter
= start_block
->next();
752 !block_iter
->link
.is_tail_sentinel();
753 block_iter
= block_iter
->next()) {
754 block_iter
->start_ip
+= ip_adjustment
;
755 block_iter
->end_ip
+= ip_adjustment
;
760 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
762 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
766 adjust_later_block_ips(block
, 1);
768 exec_node::insert_after(inst
);
772 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
774 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
778 adjust_later_block_ips(block
, 1);
780 exec_node::insert_before(inst
);
784 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
786 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
788 unsigned num_inst
= list
->length();
790 block
->end_ip
+= num_inst
;
792 adjust_later_block_ips(block
, num_inst
);
794 exec_node::insert_before(list
);
798 backend_instruction::remove(bblock_t
*block
)
800 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
802 adjust_later_block_ips(block
, -1);
804 if (block
->start_ip
== block
->end_ip
) {
805 block
->cfg
->remove_block(block
);
814 backend_visitor::dump_instructions()
816 dump_instructions(NULL
);
820 backend_visitor::dump_instructions(const char *name
)
823 if (name
&& geteuid() != 0) {
824 file
= fopen(name
, "w");
830 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
832 fprintf(stderr
, "%d: ", ip
++);
833 dump_instruction(inst
, file
);
836 if (file
!= stderr
) {
842 backend_visitor::calculate_cfg()
846 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
850 backend_visitor::invalidate_cfg()
852 ralloc_free(this->cfg
);
857 * Sets up the starting offsets for the groups of binding table entries
858 * commong to all pipeline stages.
860 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
861 * unused but also make sure that addition of small offsets to them will
862 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
865 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset
)
867 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
869 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
870 next_binding_table_offset
+= num_textures
;
873 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
874 next_binding_table_offset
+= shader
->base
.NumUniformBlocks
;
876 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
879 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
880 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
881 next_binding_table_offset
++;
883 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
886 if (prog
->UsesGather
) {
888 stage_prog_data
->binding_table
.gather_texture_start
=
889 stage_prog_data
->binding_table
.texture_start
;
891 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
892 next_binding_table_offset
+= num_textures
;
895 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
898 if (shader_prog
&& shader_prog
->NumAtomicBuffers
) {
899 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
900 next_binding_table_offset
+= shader_prog
->NumAtomicBuffers
;
902 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
905 /* This may or may not be used depending on how the compile goes. */
906 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
907 next_binding_table_offset
++;
909 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
911 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */