src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  88       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  89    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  90       devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false);
  91    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  92    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  93
  94    nir_shader_compiler_options *nir_options =
  95       rzalloc(compiler, nir_shader_compiler_options);
  96    nir_options->native_integers = true;
  97    /* In order to help allow for better CSE at the NIR level we tell NIR
  98     * to split all ffma instructions during opt_algebraic and we then
  99     * re-combine them as a later step.
 100     */
 101    nir_options->lower_ffma = true;
 102    nir_options->lower_sub = true;
 103    nir_options->lower_fdiv = true;
 104
 105    /* In the vec4 backend, our dpN instruction replicates its result to all
 106     * the components of a vec4.  We would like NIR to give us replicated fdot
 107     * instructions because it can optimize better for us.
 108     *
 109     * For the FS backend, it should be lowered away by the scalarizing pass so
 110     * we should never see fdot anyway.
 111     */
 112    nir_options->fdot_replicates = true;
 113
 114    /* We want the GLSL compiler to emit code that uses condition codes */
 115    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 116       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 117       compiler->glsl_compiler_options[i].MaxIfDepth =
 118          devinfo->gen < 6 ? 16 : UINT_MAX;
 119
 120       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 121       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 122       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 123       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 124       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 125       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 126
 127       bool is_scalar = compiler->scalar_stage[i];
 128
 129       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 130       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 131       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 132
 133       /* !ARB_gpu_shader5 */
 134       if (devinfo->gen < 7)
 135          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 136
 137       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 138
 139       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 140    }
 141
 142    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 143       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 144
 145    return compiler;
 146 }
 147
 148 struct gl_shader *
 149 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 150 {
 151    struct brw_shader *shader;
 152
 153    shader = rzalloc(NULL, struct brw_shader);
 154    if (shader) {
 155       shader->base.Type = type;
 156       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 157       shader->base.Name = name;
 158       _mesa_init_shader(ctx, &shader->base);
 159    }
 160
 161    return &shader->base;
 162 }
 163
 164 void
 165 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 166                       unsigned surf_index)
 167 {
 168    assert(surf_index < BRW_MAX_SURFACES);
 169
 170    prog_data->binding_table.size_bytes =
 171       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 172 }
 173
 174 enum brw_reg_type
 175 brw_type_for_base_type(const struct glsl_type *type)
 176 {
 177    switch (type->base_type) {
 178    case GLSL_TYPE_FLOAT:
 179       return BRW_REGISTER_TYPE_F;
 180    case GLSL_TYPE_INT:
 181    case GLSL_TYPE_BOOL:
 182    case GLSL_TYPE_SUBROUTINE:
 183       return BRW_REGISTER_TYPE_D;
 184    case GLSL_TYPE_UINT:
 185       return BRW_REGISTER_TYPE_UD;
 186    case GLSL_TYPE_ARRAY:
 187       return brw_type_for_base_type(type->fields.array);
 188    case GLSL_TYPE_STRUCT:
 189    case GLSL_TYPE_SAMPLER:
 190    case GLSL_TYPE_ATOMIC_UINT:
 191       /* These should be overridden with the type of the member when
 192        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 193        * way to trip up if we don't.
 194        */
 195       return BRW_REGISTER_TYPE_UD;
 196    case GLSL_TYPE_IMAGE:
 197       return BRW_REGISTER_TYPE_UD;
 198    case GLSL_TYPE_VOID:
 199    case GLSL_TYPE_ERROR:
 200    case GLSL_TYPE_INTERFACE:
 201    case GLSL_TYPE_DOUBLE:
 202    case GLSL_TYPE_FUNCTION:
 203       unreachable("not reached");
 204    }
 205
 206    return BRW_REGISTER_TYPE_F;
 207 }
 208
 209 enum brw_conditional_mod
 210 brw_conditional_for_comparison(unsigned int op)
 211 {
 212    switch (op) {
 213    case ir_binop_less:
 214       return BRW_CONDITIONAL_L;
 215    case ir_binop_greater:
 216       return BRW_CONDITIONAL_G;
 217    case ir_binop_lequal:
 218       return BRW_CONDITIONAL_LE;
 219    case ir_binop_gequal:
 220       return BRW_CONDITIONAL_GE;
 221    case ir_binop_equal:
 222    case ir_binop_all_equal: /* same as equal for scalars */
 223       return BRW_CONDITIONAL_Z;
 224    case ir_binop_nequal:
 225    case ir_binop_any_nequal: /* same as nequal for scalars */
 226       return BRW_CONDITIONAL_NZ;
 227    default:
 228       unreachable("not reached: bad operation for comparison");
 229    }
 230 }
 231
 232 uint32_t
 233 brw_math_function(enum opcode op)
 234 {
 235    switch (op) {
 236    case SHADER_OPCODE_RCP:
 237       return BRW_MATH_FUNCTION_INV;
 238    case SHADER_OPCODE_RSQ:
 239       return BRW_MATH_FUNCTION_RSQ;
 240    case SHADER_OPCODE_SQRT:
 241       return BRW_MATH_FUNCTION_SQRT;
 242    case SHADER_OPCODE_EXP2:
 243       return BRW_MATH_FUNCTION_EXP;
 244    case SHADER_OPCODE_LOG2:
 245       return BRW_MATH_FUNCTION_LOG;
 246    case SHADER_OPCODE_POW:
 247       return BRW_MATH_FUNCTION_POW;
 248    case SHADER_OPCODE_SIN:
 249       return BRW_MATH_FUNCTION_SIN;
 250    case SHADER_OPCODE_COS:
 251       return BRW_MATH_FUNCTION_COS;
 252    case SHADER_OPCODE_INT_QUOTIENT:
 253       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 254    case SHADER_OPCODE_INT_REMAINDER:
 255       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 256    default:
 257       unreachable("not reached: unknown math function");
 258    }
 259 }
 260
 261 uint32_t
 262 brw_texture_offset(int *offsets, unsigned num_components)
 263 {
 264    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 265
 266    /* Combine all three offsets into a single unsigned dword:
 267     *
 268     *    bits 11:8 - U Offset (X component)
 269     *    bits  7:4 - V Offset (Y component)
 270     *    bits  3:0 - R Offset (Z component)
 271     */
 272    unsigned offset_bits = 0;
 273    for (unsigned i = 0; i < num_components; i++) {
 274       const unsigned shift = 4 * (2 - i);
 275       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 276    }
 277    return offset_bits;
 278 }
 279
 280 const char *
 281 brw_instruction_name(enum opcode op)
 282 {
 283    switch (op) {
 284    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 285       assert(opcode_descs[op].name);
 286       return opcode_descs[op].name;
 287    case FS_OPCODE_FB_WRITE:
 288       return "fb_write";
 289    case FS_OPCODE_FB_WRITE_LOGICAL:
 290       return "fb_write_logical";
 291    case FS_OPCODE_PACK_STENCIL_REF:
 292       return "pack_stencil_ref";
 293    case FS_OPCODE_BLORP_FB_WRITE:
 294       return "blorp_fb_write";
 295    case FS_OPCODE_REP_FB_WRITE:
 296       return "rep_fb_write";
 297
 298    case SHADER_OPCODE_RCP:
 299       return "rcp";
 300    case SHADER_OPCODE_RSQ:
 301       return "rsq";
 302    case SHADER_OPCODE_SQRT:
 303       return "sqrt";
 304    case SHADER_OPCODE_EXP2:
 305       return "exp2";
 306    case SHADER_OPCODE_LOG2:
 307       return "log2";
 308    case SHADER_OPCODE_POW:
 309       return "pow";
 310    case SHADER_OPCODE_INT_QUOTIENT:
 311       return "int_quot";
 312    case SHADER_OPCODE_INT_REMAINDER:
 313       return "int_rem";
 314    case SHADER_OPCODE_SIN:
 315       return "sin";
 316    case SHADER_OPCODE_COS:
 317       return "cos";
 318
 319    case SHADER_OPCODE_TEX:
 320       return "tex";
 321    case SHADER_OPCODE_TEX_LOGICAL:
 322       return "tex_logical";
 323    case SHADER_OPCODE_TXD:
 324       return "txd";
 325    case SHADER_OPCODE_TXD_LOGICAL:
 326       return "txd_logical";
 327    case SHADER_OPCODE_TXF:
 328       return "txf";
 329    case SHADER_OPCODE_TXF_LOGICAL:
 330       return "txf_logical";
 331    case SHADER_OPCODE_TXL:
 332       return "txl";
 333    case SHADER_OPCODE_TXL_LOGICAL:
 334       return "txl_logical";
 335    case SHADER_OPCODE_TXS:
 336       return "txs";
 337    case SHADER_OPCODE_TXS_LOGICAL:
 338       return "txs_logical";
 339    case FS_OPCODE_TXB:
 340       return "txb";
 341    case FS_OPCODE_TXB_LOGICAL:
 342       return "txb_logical";
 343    case SHADER_OPCODE_TXF_CMS:
 344       return "txf_cms";
 345    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 346       return "txf_cms_logical";
 347    case SHADER_OPCODE_TXF_CMS_W:
 348       return "txf_cms_w";
 349    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 350       return "txf_cms_w_logical";
 351    case SHADER_OPCODE_TXF_UMS:
 352       return "txf_ums";
 353    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 354       return "txf_ums_logical";
 355    case SHADER_OPCODE_TXF_MCS:
 356       return "txf_mcs";
 357    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 358       return "txf_mcs_logical";
 359    case SHADER_OPCODE_LOD:
 360       return "lod";
 361    case SHADER_OPCODE_LOD_LOGICAL:
 362       return "lod_logical";
 363    case SHADER_OPCODE_TG4:
 364       return "tg4";
 365    case SHADER_OPCODE_TG4_LOGICAL:
 366       return "tg4_logical";
 367    case SHADER_OPCODE_TG4_OFFSET:
 368       return "tg4_offset";
 369    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 370       return "tg4_offset_logical";
 371    case SHADER_OPCODE_SAMPLEINFO:
 372       return "sampleinfo";
 373
 374    case SHADER_OPCODE_SHADER_TIME_ADD:
 375       return "shader_time_add";
 376
 377    case SHADER_OPCODE_UNTYPED_ATOMIC:
 378       return "untyped_atomic";
 379    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 380       return "untyped_atomic_logical";
 381    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 382       return "untyped_surface_read";
 383    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 384       return "untyped_surface_read_logical";
 385    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 386       return "untyped_surface_write";
 387    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 388       return "untyped_surface_write_logical";
 389    case SHADER_OPCODE_TYPED_ATOMIC:
 390       return "typed_atomic";
 391    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 392       return "typed_atomic_logical";
 393    case SHADER_OPCODE_TYPED_SURFACE_READ:
 394       return "typed_surface_read";
 395    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 396       return "typed_surface_read_logical";
 397    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 398       return "typed_surface_write";
 399    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 400       return "typed_surface_write_logical";
 401    case SHADER_OPCODE_MEMORY_FENCE:
 402       return "memory_fence";
 403
 404    case SHADER_OPCODE_LOAD_PAYLOAD:
 405       return "load_payload";
 406
 407    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 408       return "gen4_scratch_read";
 409    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 410       return "gen4_scratch_write";
 411    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 412       return "gen7_scratch_read";
 413    case SHADER_OPCODE_URB_WRITE_SIMD8:
 414       return "gen8_urb_write_simd8";
 415    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 416       return "gen8_urb_write_simd8_per_slot";
 417    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 418       return "gen8_urb_write_simd8_masked";
 419    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 420       return "gen8_urb_write_simd8_masked_per_slot";
 421    case SHADER_OPCODE_URB_READ_SIMD8:
 422       return "urb_read_simd8";
 423    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 424       return "urb_read_simd8_per_slot";
 425
 426    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 427       return "find_live_channel";
 428    case SHADER_OPCODE_BROADCAST:
 429       return "broadcast";
 430
 431    case VEC4_OPCODE_MOV_BYTES:
 432       return "mov_bytes";
 433    case VEC4_OPCODE_PACK_BYTES:
 434       return "pack_bytes";
 435    case VEC4_OPCODE_UNPACK_UNIFORM:
 436       return "unpack_uniform";
 437
 438    case FS_OPCODE_DDX_COARSE:
 439       return "ddx_coarse";
 440    case FS_OPCODE_DDX_FINE:
 441       return "ddx_fine";
 442    case FS_OPCODE_DDY_COARSE:
 443       return "ddy_coarse";
 444    case FS_OPCODE_DDY_FINE:
 445       return "ddy_fine";
 446
 447    case FS_OPCODE_CINTERP:
 448       return "cinterp";
 449    case FS_OPCODE_LINTERP:
 450       return "linterp";
 451
 452    case FS_OPCODE_PIXEL_X:
 453       return "pixel_x";
 454    case FS_OPCODE_PIXEL_Y:
 455       return "pixel_y";
 456
 457    case FS_OPCODE_GET_BUFFER_SIZE:
 458       return "fs_get_buffer_size";
 459
 460    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 461       return "uniform_pull_const";
 462    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 463       return "uniform_pull_const_gen7";
 464    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 465       return "varying_pull_const";
 466    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 467       return "varying_pull_const_gen7";
 468
 469    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 470       return "mov_dispatch_to_flags";
 471    case FS_OPCODE_DISCARD_JUMP:
 472       return "discard_jump";
 473
 474    case FS_OPCODE_SET_SAMPLE_ID:
 475       return "set_sample_id";
 476    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 477       return "set_simd4x2_offset";
 478
 479    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 480       return "pack_half_2x16_split";
 481    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 482       return "unpack_half_2x16_split_x";
 483    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 484       return "unpack_half_2x16_split_y";
 485
 486    case FS_OPCODE_PLACEHOLDER_HALT:
 487       return "placeholder_halt";
 488
 489    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 490       return "interp_centroid";
 491    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 492       return "interp_sample";
 493    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 494       return "interp_shared_offset";
 495    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 496       return "interp_per_slot_offset";
 497
 498    case VS_OPCODE_URB_WRITE:
 499       return "vs_urb_write";
 500    case VS_OPCODE_PULL_CONSTANT_LOAD:
 501       return "pull_constant_load";
 502    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 503       return "pull_constant_load_gen7";
 504
 505    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 506       return "set_simd4x2_header_gen9";
 507
 508    case VS_OPCODE_GET_BUFFER_SIZE:
 509       return "vs_get_buffer_size";
 510
 511    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 512       return "unpack_flags_simd4x2";
 513
 514    case GS_OPCODE_URB_WRITE:
 515       return "gs_urb_write";
 516    case GS_OPCODE_URB_WRITE_ALLOCATE:
 517       return "gs_urb_write_allocate";
 518    case GS_OPCODE_THREAD_END:
 519       return "gs_thread_end";
 520    case GS_OPCODE_SET_WRITE_OFFSET:
 521       return "set_write_offset";
 522    case GS_OPCODE_SET_VERTEX_COUNT:
 523       return "set_vertex_count";
 524    case GS_OPCODE_SET_DWORD_2:
 525       return "set_dword_2";
 526    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 527       return "prepare_channel_masks";
 528    case GS_OPCODE_SET_CHANNEL_MASKS:
 529       return "set_channel_masks";
 530    case GS_OPCODE_GET_INSTANCE_ID:
 531       return "get_instance_id";
 532    case GS_OPCODE_FF_SYNC:
 533       return "ff_sync";
 534    case GS_OPCODE_SET_PRIMITIVE_ID:
 535       return "set_primitive_id";
 536    case GS_OPCODE_SVB_WRITE:
 537       return "gs_svb_write";
 538    case GS_OPCODE_SVB_SET_DST_INDEX:
 539       return "gs_svb_set_dst_index";
 540    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 541       return "gs_ff_sync_set_primitives";
 542    case CS_OPCODE_CS_TERMINATE:
 543       return "cs_terminate";
 544    case SHADER_OPCODE_BARRIER:
 545       return "barrier";
 546    case SHADER_OPCODE_MULH:
 547       return "mulh";
 548    case SHADER_OPCODE_MOV_INDIRECT:
 549       return "mov_indirect";
 550    }
 551
 552    unreachable("not reached");
 553 }
 554
 555 bool
 556 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 557 {
 558    union {
 559       unsigned ud;
 560       int d;
 561       float f;
 562    } imm = { reg->ud }, sat_imm = { 0 };
 563
 564    switch (type) {
 565    case BRW_REGISTER_TYPE_UD:
 566    case BRW_REGISTER_TYPE_D:
 567    case BRW_REGISTER_TYPE_UW:
 568    case BRW_REGISTER_TYPE_W:
 569    case BRW_REGISTER_TYPE_UQ:
 570    case BRW_REGISTER_TYPE_Q:
 571       /* Nothing to do. */
 572       return false;
 573    case BRW_REGISTER_TYPE_F:
 574       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 575       break;
 576    case BRW_REGISTER_TYPE_UB:
 577    case BRW_REGISTER_TYPE_B:
 578       unreachable("no UB/B immediates");
 579    case BRW_REGISTER_TYPE_V:
 580    case BRW_REGISTER_TYPE_UV:
 581    case BRW_REGISTER_TYPE_VF:
 582       unreachable("unimplemented: saturate vector immediate");
 583    case BRW_REGISTER_TYPE_DF:
 584    case BRW_REGISTER_TYPE_HF:
 585       unreachable("unimplemented: saturate DF/HF immediate");
 586    }
 587
 588    if (imm.ud != sat_imm.ud) {
 589       reg->ud = sat_imm.ud;
 590       return true;
 591    }
 592    return false;
 593 }
 594
 595 bool
 596 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 597 {
 598    switch (type) {
 599    case BRW_REGISTER_TYPE_D:
 600    case BRW_REGISTER_TYPE_UD:
 601       reg->d = -reg->d;
 602       return true;
 603    case BRW_REGISTER_TYPE_W:
 604    case BRW_REGISTER_TYPE_UW:
 605       reg->d = -(int16_t)reg->ud;
 606       return true;
 607    case BRW_REGISTER_TYPE_F:
 608       reg->f = -reg->f;
 609       return true;
 610    case BRW_REGISTER_TYPE_VF:
 611       reg->ud ^= 0x80808080;
 612       return true;
 613    case BRW_REGISTER_TYPE_UB:
 614    case BRW_REGISTER_TYPE_B:
 615       unreachable("no UB/B immediates");
 616    case BRW_REGISTER_TYPE_UV:
 617    case BRW_REGISTER_TYPE_V:
 618       assert(!"unimplemented: negate UV/V immediate");
 619    case BRW_REGISTER_TYPE_UQ:
 620    case BRW_REGISTER_TYPE_Q:
 621       assert(!"unimplemented: negate UQ/Q immediate");
 622    case BRW_REGISTER_TYPE_DF:
 623    case BRW_REGISTER_TYPE_HF:
 624       assert(!"unimplemented: negate DF/HF immediate");
 625    }
 626
 627    return false;
 628 }
 629
 630 bool
 631 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 632 {
 633    switch (type) {
 634    case BRW_REGISTER_TYPE_D:
 635       reg->d = abs(reg->d);
 636       return true;
 637    case BRW_REGISTER_TYPE_W:
 638       reg->d = abs((int16_t)reg->ud);
 639       return true;
 640    case BRW_REGISTER_TYPE_F:
 641       reg->f = fabsf(reg->f);
 642       return true;
 643    case BRW_REGISTER_TYPE_VF:
 644       reg->ud &= ~0x80808080;
 645       return true;
 646    case BRW_REGISTER_TYPE_UB:
 647    case BRW_REGISTER_TYPE_B:
 648       unreachable("no UB/B immediates");
 649    case BRW_REGISTER_TYPE_UQ:
 650    case BRW_REGISTER_TYPE_UD:
 651    case BRW_REGISTER_TYPE_UW:
 652    case BRW_REGISTER_TYPE_UV:
 653       /* Presumably the absolute value modifier on an unsigned source is a
 654        * nop, but it would be nice to confirm.
 655        */
 656       assert(!"unimplemented: abs unsigned immediate");
 657    case BRW_REGISTER_TYPE_V:
 658       assert(!"unimplemented: abs V immediate");
 659    case BRW_REGISTER_TYPE_Q:
 660       assert(!"unimplemented: abs Q immediate");
 661    case BRW_REGISTER_TYPE_DF:
 662    case BRW_REGISTER_TYPE_HF:
 663       assert(!"unimplemented: abs DF/HF immediate");
 664    }
 665
 666    return false;
 667 }
 668
 669 backend_shader::backend_shader(const struct brw_compiler *compiler,
 670                                void *log_data,
 671                                void *mem_ctx,
 672                                const nir_shader *shader,
 673                                struct brw_stage_prog_data *stage_prog_data)
 674    : compiler(compiler),
 675      log_data(log_data),
 676      devinfo(compiler->devinfo),
 677      nir(shader),
 678      stage_prog_data(stage_prog_data),
 679      mem_ctx(mem_ctx),
 680      cfg(NULL),
 681      stage(shader->stage)
 682 {
 683    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 684    stage_name = _mesa_shader_stage_to_string(stage);
 685    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 686 }
 687
 688 bool
 689 backend_reg::is_zero() const
 690 {
 691    if (file != IMM)
 692       return false;
 693
 694    return d == 0;
 695 }
 696
 697 bool
 698 backend_reg::is_one() const
 699 {
 700    if (file != IMM)
 701       return false;
 702
 703    return type == BRW_REGISTER_TYPE_F
 704           ? f == 1.0
 705           : d == 1;
 706 }
 707
 708 bool
 709 backend_reg::is_negative_one() const
 710 {
 711    if (file != IMM)
 712       return false;
 713
 714    switch (type) {
 715    case BRW_REGISTER_TYPE_F:
 716       return f == -1.0;
 717    case BRW_REGISTER_TYPE_D:
 718       return d == -1;
 719    default:
 720       return false;
 721    }
 722 }
 723
 724 bool
 725 backend_reg::is_null() const
 726 {
 727    return file == ARF && nr == BRW_ARF_NULL;
 728 }
 729
 730
 731 bool
 732 backend_reg::is_accumulator() const
 733 {
 734    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 735 }
 736
 737 bool
 738 backend_reg::in_range(const backend_reg &r, unsigned n) const
 739 {
 740    return (file == r.file &&
 741            nr == r.nr &&
 742            reg_offset >= r.reg_offset &&
 743            reg_offset < r.reg_offset + n);
 744 }
 745
 746 bool
 747 backend_instruction::is_commutative() const
 748 {
 749    switch (opcode) {
 750    case BRW_OPCODE_AND:
 751    case BRW_OPCODE_OR:
 752    case BRW_OPCODE_XOR:
 753    case BRW_OPCODE_ADD:
 754    case BRW_OPCODE_MUL:
 755    case SHADER_OPCODE_MULH:
 756       return true;
 757    case BRW_OPCODE_SEL:
 758       /* MIN and MAX are commutative. */
 759       if (conditional_mod == BRW_CONDITIONAL_GE ||
 760           conditional_mod == BRW_CONDITIONAL_L) {
 761          return true;
 762       }
 763       /* fallthrough */
 764    default:
 765       return false;
 766    }
 767 }
 768
 769 bool
 770 backend_instruction::is_3src() const
 771 {
 772    return ::is_3src(opcode);
 773 }
 774
 775 bool
 776 backend_instruction::is_tex() const
 777 {
 778    return (opcode == SHADER_OPCODE_TEX ||
 779            opcode == FS_OPCODE_TXB ||
 780            opcode == SHADER_OPCODE_TXD ||
 781            opcode == SHADER_OPCODE_TXF ||
 782            opcode == SHADER_OPCODE_TXF_CMS ||
 783            opcode == SHADER_OPCODE_TXF_CMS_W ||
 784            opcode == SHADER_OPCODE_TXF_UMS ||
 785            opcode == SHADER_OPCODE_TXF_MCS ||
 786            opcode == SHADER_OPCODE_TXL ||
 787            opcode == SHADER_OPCODE_TXS ||
 788            opcode == SHADER_OPCODE_LOD ||
 789            opcode == SHADER_OPCODE_TG4 ||
 790            opcode == SHADER_OPCODE_TG4_OFFSET);
 791 }
 792
 793 bool
 794 backend_instruction::is_math() const
 795 {
 796    return (opcode == SHADER_OPCODE_RCP ||
 797            opcode == SHADER_OPCODE_RSQ ||
 798            opcode == SHADER_OPCODE_SQRT ||
 799            opcode == SHADER_OPCODE_EXP2 ||
 800            opcode == SHADER_OPCODE_LOG2 ||
 801            opcode == SHADER_OPCODE_SIN ||
 802            opcode == SHADER_OPCODE_COS ||
 803            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 804            opcode == SHADER_OPCODE_INT_REMAINDER ||
 805            opcode == SHADER_OPCODE_POW);
 806 }
 807
 808 bool
 809 backend_instruction::is_control_flow() const
 810 {
 811    switch (opcode) {
 812    case BRW_OPCODE_DO:
 813    case BRW_OPCODE_WHILE:
 814    case BRW_OPCODE_IF:
 815    case BRW_OPCODE_ELSE:
 816    case BRW_OPCODE_ENDIF:
 817    case BRW_OPCODE_BREAK:
 818    case BRW_OPCODE_CONTINUE:
 819       return true;
 820    default:
 821       return false;
 822    }
 823 }
 824
 825 bool
 826 backend_instruction::can_do_source_mods() const
 827 {
 828    switch (opcode) {
 829    case BRW_OPCODE_ADDC:
 830    case BRW_OPCODE_BFE:
 831    case BRW_OPCODE_BFI1:
 832    case BRW_OPCODE_BFI2:
 833    case BRW_OPCODE_BFREV:
 834    case BRW_OPCODE_CBIT:
 835    case BRW_OPCODE_FBH:
 836    case BRW_OPCODE_FBL:
 837    case BRW_OPCODE_SUBB:
 838       return false;
 839    default:
 840       return true;
 841    }
 842 }
 843
 844 bool
 845 backend_instruction::can_do_saturate() const
 846 {
 847    switch (opcode) {
 848    case BRW_OPCODE_ADD:
 849    case BRW_OPCODE_ASR:
 850    case BRW_OPCODE_AVG:
 851    case BRW_OPCODE_DP2:
 852    case BRW_OPCODE_DP3:
 853    case BRW_OPCODE_DP4:
 854    case BRW_OPCODE_DPH:
 855    case BRW_OPCODE_F16TO32:
 856    case BRW_OPCODE_F32TO16:
 857    case BRW_OPCODE_LINE:
 858    case BRW_OPCODE_LRP:
 859    case BRW_OPCODE_MAC:
 860    case BRW_OPCODE_MAD:
 861    case BRW_OPCODE_MATH:
 862    case BRW_OPCODE_MOV:
 863    case BRW_OPCODE_MUL:
 864    case SHADER_OPCODE_MULH:
 865    case BRW_OPCODE_PLN:
 866    case BRW_OPCODE_RNDD:
 867    case BRW_OPCODE_RNDE:
 868    case BRW_OPCODE_RNDU:
 869    case BRW_OPCODE_RNDZ:
 870    case BRW_OPCODE_SEL:
 871    case BRW_OPCODE_SHL:
 872    case BRW_OPCODE_SHR:
 873    case FS_OPCODE_LINTERP:
 874    case SHADER_OPCODE_COS:
 875    case SHADER_OPCODE_EXP2:
 876    case SHADER_OPCODE_LOG2:
 877    case SHADER_OPCODE_POW:
 878    case SHADER_OPCODE_RCP:
 879    case SHADER_OPCODE_RSQ:
 880    case SHADER_OPCODE_SIN:
 881    case SHADER_OPCODE_SQRT:
 882       return true;
 883    default:
 884       return false;
 885    }
 886 }
 887
 888 bool
 889 backend_instruction::can_do_cmod() const
 890 {
 891    switch (opcode) {
 892    case BRW_OPCODE_ADD:
 893    case BRW_OPCODE_ADDC:
 894    case BRW_OPCODE_AND:
 895    case BRW_OPCODE_ASR:
 896    case BRW_OPCODE_AVG:
 897    case BRW_OPCODE_CMP:
 898    case BRW_OPCODE_CMPN:
 899    case BRW_OPCODE_DP2:
 900    case BRW_OPCODE_DP3:
 901    case BRW_OPCODE_DP4:
 902    case BRW_OPCODE_DPH:
 903    case BRW_OPCODE_F16TO32:
 904    case BRW_OPCODE_F32TO16:
 905    case BRW_OPCODE_FRC:
 906    case BRW_OPCODE_LINE:
 907    case BRW_OPCODE_LRP:
 908    case BRW_OPCODE_LZD:
 909    case BRW_OPCODE_MAC:
 910    case BRW_OPCODE_MACH:
 911    case BRW_OPCODE_MAD:
 912    case BRW_OPCODE_MOV:
 913    case BRW_OPCODE_MUL:
 914    case BRW_OPCODE_NOT:
 915    case BRW_OPCODE_OR:
 916    case BRW_OPCODE_PLN:
 917    case BRW_OPCODE_RNDD:
 918    case BRW_OPCODE_RNDE:
 919    case BRW_OPCODE_RNDU:
 920    case BRW_OPCODE_RNDZ:
 921    case BRW_OPCODE_SAD2:
 922    case BRW_OPCODE_SADA2:
 923    case BRW_OPCODE_SHL:
 924    case BRW_OPCODE_SHR:
 925    case BRW_OPCODE_SUBB:
 926    case BRW_OPCODE_XOR:
 927    case FS_OPCODE_CINTERP:
 928    case FS_OPCODE_LINTERP:
 929       return true;
 930    default:
 931       return false;
 932    }
 933 }
 934
 935 bool
 936 backend_instruction::reads_accumulator_implicitly() const
 937 {
 938    switch (opcode) {
 939    case BRW_OPCODE_MAC:
 940    case BRW_OPCODE_MACH:
 941    case BRW_OPCODE_SADA2:
 942       return true;
 943    default:
 944       return false;
 945    }
 946 }
 947
 948 bool
 949 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 950 {
 951    return writes_accumulator ||
 952           (devinfo->gen < 6 &&
 953            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 954             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 955              opcode != FS_OPCODE_CINTERP)));
 956 }
 957
 958 bool
 959 backend_instruction::has_side_effects() const
 960 {
 961    switch (opcode) {
 962    case SHADER_OPCODE_UNTYPED_ATOMIC:
 963    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 964    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 965    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 966    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 967    case SHADER_OPCODE_TYPED_ATOMIC:
 968    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 969    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 970    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 971    case SHADER_OPCODE_MEMORY_FENCE:
 972    case SHADER_OPCODE_URB_WRITE_SIMD8:
 973    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 974    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 975    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 976    case FS_OPCODE_FB_WRITE:
 977    case SHADER_OPCODE_BARRIER:
 978       return true;
 979    default:
 980       return false;
 981    }
 982 }
 983
 984 bool
 985 backend_instruction::is_volatile() const
 986 {
 987    switch (opcode) {
 988    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 989    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 990    case SHADER_OPCODE_TYPED_SURFACE_READ:
 991    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 992       return true;
 993    default:
 994       return false;
 995    }
 996 }
 997
 998 #ifndef NDEBUG
 999 static bool
1000 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1001 {
1002    bool found = false;
1003    foreach_inst_in_block (backend_instruction, i, block) {
1004       if (inst == i) {
1005          found = true;
1006       }
1007    }
1008    return found;
1009 }
1010 #endif
1011
1012 static void
1013 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1014 {
1015    for (bblock_t *block_iter = start_block->next();
1016         !block_iter->link.is_tail_sentinel();
1017         block_iter = block_iter->next()) {
1018       block_iter->start_ip += ip_adjustment;
1019       block_iter->end_ip += ip_adjustment;
1020    }
1021 }
1022
1023 void
1024 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1025 {
1026    if (!this->is_head_sentinel())
1027       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1028
1029    block->end_ip++;
1030
1031    adjust_later_block_ips(block, 1);
1032
1033    exec_node::insert_after(inst);
1034 }
1035
1036 void
1037 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1038 {
1039    if (!this->is_tail_sentinel())
1040       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1041
1042    block->end_ip++;
1043
1044    adjust_later_block_ips(block, 1);
1045
1046    exec_node::insert_before(inst);
1047 }
1048
1049 void
1050 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1051 {
1052    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1053
1054    unsigned num_inst = list->length();
1055
1056    block->end_ip += num_inst;
1057
1058    adjust_later_block_ips(block, num_inst);
1059
1060    exec_node::insert_before(list);
1061 }
1062
1063 void
1064 backend_instruction::remove(bblock_t *block)
1065 {
1066    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    adjust_later_block_ips(block, -1);
1069
1070    if (block->start_ip == block->end_ip) {
1071       block->cfg->remove_block(block);
1072    } else {
1073       block->end_ip--;
1074    }
1075
1076    exec_node::remove();
1077 }
1078
1079 void
1080 backend_shader::dump_instructions()
1081 {
1082    dump_instructions(NULL);
1083 }
1084
1085 void
1086 backend_shader::dump_instructions(const char *name)
1087 {
1088    FILE *file = stderr;
1089    if (name && geteuid() != 0) {
1090       file = fopen(name, "w");
1091       if (!file)
1092          file = stderr;
1093    }
1094
1095    if (cfg) {
1096       int ip = 0;
1097       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1098          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1099             fprintf(file, "%4d: ", ip++);
1100          dump_instruction(inst, file);
1101       }
1102    } else {
1103       int ip = 0;
1104       foreach_in_list(backend_instruction, inst, &instructions) {
1105          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1106             fprintf(file, "%4d: ", ip++);
1107          dump_instruction(inst, file);
1108       }
1109    }
1110
1111    if (file != stderr) {
1112       fclose(file);
1113    }
1114 }
1115
1116 void
1117 backend_shader::calculate_cfg()
1118 {
1119    if (this->cfg)
1120       return;
1121    cfg = new(mem_ctx) cfg_t(&this->instructions);
1122 }
1123
1124 void
1125 backend_shader::invalidate_cfg()
1126 {
1127    ralloc_free(this->cfg);
1128    this->cfg = NULL;
1129 }
1130
1131 /**
1132  * Sets up the starting offsets for the groups of binding table entries
1133  * commong to all pipeline stages.
1134  *
1135  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1136  * unused but also make sure that addition of small offsets to them will
1137  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1138  */
1139 void
1140 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1141                                         const struct brw_device_info *devinfo,
1142                                         const struct gl_shader_program *shader_prog,
1143                                         const struct gl_program *prog,
1144                                         struct brw_stage_prog_data *stage_prog_data,
1145                                         uint32_t next_binding_table_offset)
1146 {
1147    const struct gl_shader *shader = NULL;
1148    int num_textures = _mesa_fls(prog->SamplersUsed);
1149
1150    if (shader_prog)
1151       shader = shader_prog->_LinkedShaders[stage];
1152
1153    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1154    next_binding_table_offset += num_textures;
1155
1156    if (shader) {
1157       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1158       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1159       next_binding_table_offset += shader->NumUniformBlocks;
1160
1161       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1162       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1163       next_binding_table_offset += shader->NumShaderStorageBlocks;
1164    } else {
1165       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1166       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1167    }
1168
1169    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1170       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1171       next_binding_table_offset++;
1172    } else {
1173       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1174    }
1175
1176    if (prog->UsesGather) {
1177       if (devinfo->gen >= 8) {
1178          stage_prog_data->binding_table.gather_texture_start =
1179             stage_prog_data->binding_table.texture_start;
1180       } else {
1181          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1182          next_binding_table_offset += num_textures;
1183       }
1184    } else {
1185       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1186    }
1187
1188    if (shader && shader->NumAtomicBuffers) {
1189       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1190       next_binding_table_offset += shader->NumAtomicBuffers;
1191    } else {
1192       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1193    }
1194
1195    if (shader && shader->NumImages) {
1196       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1197       next_binding_table_offset += shader->NumImages;
1198    } else {
1199       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1200    }
1201
1202    /* This may or may not be used depending on how the compile goes. */
1203    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1204    next_binding_table_offset++;
1205
1206    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1207
1208    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1209 }
1210
1211 static void
1212 setup_vec4_uniform_value(const gl_constant_value **params,
1213                          const gl_constant_value *values,
1214                          unsigned n)
1215 {
1216    static const gl_constant_value zero = { 0 };
1217
1218    for (unsigned i = 0; i < n; ++i)
1219       params[i] = &values[i];
1220
1221    for (unsigned i = n; i < 4; ++i)
1222       params[i] = &zero;
1223 }
1224
1225 void
1226 brw_setup_image_uniform_values(gl_shader_stage stage,
1227                                struct brw_stage_prog_data *stage_prog_data,
1228                                unsigned param_start_index,
1229                                const gl_uniform_storage *storage)
1230 {
1231    const gl_constant_value **param =
1232       &stage_prog_data->param[param_start_index];
1233
1234    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1235       const unsigned image_idx = storage->opaque[stage].index + i;
1236       const brw_image_param *image_param =
1237          &stage_prog_data->image_param[image_idx];
1238
1239       /* Upload the brw_image_param structure.  The order is expected to match
1240        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1241        */
1242       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1243          (const gl_constant_value *)&image_param->surface_idx, 1);
1244       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1245          (const gl_constant_value *)image_param->offset, 2);
1246       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1247          (const gl_constant_value *)image_param->size, 3);
1248       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1249          (const gl_constant_value *)image_param->stride, 4);
1250       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1251          (const gl_constant_value *)image_param->tiling, 3);
1252       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1253          (const gl_constant_value *)image_param->swizzling, 2);
1254       param += BRW_IMAGE_PARAM_SIZE;
1255
1256       brw_mark_surface_used(
1257          stage_prog_data,
1258          stage_prog_data->binding_table.image_start + image_idx);
1259    }
1260 }
1261
1262 /**
1263  * Decide which set of clip planes should be used when clipping via
1264  * gl_Position or gl_ClipVertex.
1265  */
1266 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1267 {
1268    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1269       /* There is currently a GLSL vertex shader, so clip according to GLSL
1270        * rules, which means compare gl_ClipVertex (or gl_Position, if
1271        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1272        * that were stored in EyeUserPlane at the time the clip planes were
1273        * specified.
1274        */
1275       return ctx->Transform.EyeUserPlane;
1276    } else {
1277       /* Either we are using fixed function or an ARB vertex program.  In
1278        * either case the clip planes are going to be compared against
1279        * gl_Position (which is in clip coordinates) so we have to clip using
1280        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1281        * core.
1282        */
1283       return ctx->Transform._ClipUserPlane;
1284    }
1285 }
1286