2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/macros.h"
26 #include "brw_context.h"
29 #include "brw_vec4_gs.h"
32 #include "glsl/ir_optimization.h"
33 #include "glsl/glsl_parser_extras.h"
34 #include "main/shaderapi.h"
37 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
39 struct brw_shader
*shader
;
41 shader
= rzalloc(NULL
, struct brw_shader
);
43 shader
->base
.Type
= type
;
44 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
45 shader
->base
.Name
= name
;
46 _mesa_init_shader(ctx
, &shader
->base
);
52 struct gl_shader_program
*
53 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
55 struct gl_shader_program
*prog
= rzalloc(NULL
, struct gl_shader_program
);
58 _mesa_init_shader_program(ctx
, prog
);
64 * Performs a compile of the shader stages even when we don't know
65 * what non-orthogonal state will be set, in the hope that it reflects
66 * the eventual NOS used, and thus allows us to produce link failures.
69 brw_shader_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
71 struct brw_context
*brw
= brw_context(ctx
);
73 if (brw
->precompile
&& !brw_fs_precompile(ctx
, prog
))
76 if (brw
->precompile
&& !brw_gs_precompile(ctx
, prog
))
79 if (brw
->precompile
&& !brw_vs_precompile(ctx
, prog
))
86 brw_lower_packing_builtins(struct brw_context
*brw
,
87 gl_shader_stage shader_type
,
90 int ops
= LOWER_PACK_SNORM_2x16
91 | LOWER_UNPACK_SNORM_2x16
92 | LOWER_PACK_UNORM_2x16
93 | LOWER_UNPACK_UNORM_2x16
94 | LOWER_PACK_SNORM_4x8
95 | LOWER_UNPACK_SNORM_4x8
96 | LOWER_PACK_UNORM_4x8
97 | LOWER_UNPACK_UNORM_4x8
;
100 /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
101 * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
102 * lowering is needed. For SOA code, the Half2x16 ops must be
105 if (shader_type
== MESA_SHADER_FRAGMENT
) {
106 ops
|= LOWER_PACK_HALF_2x16_TO_SPLIT
107 | LOWER_UNPACK_HALF_2x16_TO_SPLIT
;
110 ops
|= LOWER_PACK_HALF_2x16
111 | LOWER_UNPACK_HALF_2x16
;
114 lower_packing_builtins(ir
, ops
);
118 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*shProg
)
120 struct brw_context
*brw
= brw_context(ctx
);
123 for (stage
= 0; stage
< ARRAY_SIZE(shProg
->_LinkedShaders
); stage
++) {
124 const struct gl_shader_compiler_options
*options
=
125 &ctx
->ShaderCompilerOptions
[stage
];
126 struct brw_shader
*shader
=
127 (struct brw_shader
*)shProg
->_LinkedShaders
[stage
];
132 struct gl_program
*prog
=
133 ctx
->Driver
.NewProgram(ctx
, _mesa_shader_stage_to_program(stage
),
137 prog
->Parameters
= _mesa_new_parameter_list();
139 _mesa_copy_linked_program_data((gl_shader_stage
) stage
, shProg
, prog
);
143 /* lower_packing_builtins() inserts arithmetic instructions, so it
144 * must precede lower_instructions().
146 brw_lower_packing_builtins(brw
, (gl_shader_stage
) stage
, shader
->base
.ir
);
147 do_mat_op_to_vec(shader
->base
.ir
);
148 const int bitfield_insert
= brw
->gen
>= 7
149 ? BITFIELD_INSERT_TO_BFM_BFI
151 lower_instructions(shader
->base
.ir
,
160 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
161 * if-statements need to be flattened.
164 lower_if_to_cond_assign(shader
->base
.ir
, 16);
166 do_lower_texture_projection(shader
->base
.ir
);
167 brw_lower_texture_gradients(brw
, shader
->base
.ir
);
168 do_vec_index_to_cond_assign(shader
->base
.ir
);
169 lower_vector_insert(shader
->base
.ir
, true);
170 brw_do_cubemap_normalize(shader
->base
.ir
);
171 lower_offset_arrays(shader
->base
.ir
);
172 brw_do_lower_unnormalized_offset(shader
->base
.ir
);
173 lower_noise(shader
->base
.ir
);
174 lower_quadop_vector(shader
->base
.ir
, false);
176 bool lowered_variable_indexing
=
177 lower_variable_index_to_cond_assign(shader
->base
.ir
,
178 options
->EmitNoIndirectInput
,
179 options
->EmitNoIndirectOutput
,
180 options
->EmitNoIndirectTemp
,
181 options
->EmitNoIndirectUniform
);
183 if (unlikely(brw
->perf_debug
&& lowered_variable_indexing
)) {
184 perf_debug("Unsupported form of variable indexing in FS; falling "
185 "back to very inefficient code generation\n");
188 lower_ubo_reference(&shader
->base
, shader
->base
.ir
);
193 if (stage
== MESA_SHADER_FRAGMENT
) {
194 brw_do_channel_expressions(shader
->base
.ir
);
195 brw_do_vector_splitting(shader
->base
.ir
);
198 progress
= do_lower_jumps(shader
->base
.ir
, true, true,
199 true, /* main return */
200 false, /* continue */
204 progress
= do_common_optimization(shader
->base
.ir
, true, true,
205 options
, ctx
->Const
.NativeIntegers
)
209 /* Make a pass over the IR to add state references for any built-in
210 * uniforms that are used. This has to be done now (during linking).
211 * Code generation doesn't happen until the first time this shader is
212 * used for rendering. Waiting until then to generate the parameters is
213 * too late. At that point, the values for the built-in uniforms won't
214 * get sent to the shader.
216 foreach_in_list(ir_instruction
, node
, shader
->base
.ir
) {
217 ir_variable
*var
= node
->as_variable();
219 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
220 || (strncmp(var
->name
, "gl_", 3) != 0))
223 const ir_state_slot
*const slots
= var
->state_slots
;
224 assert(var
->state_slots
!= NULL
);
226 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
227 _mesa_add_state_reference(prog
->Parameters
,
228 (gl_state_index
*) slots
[i
].tokens
);
232 validate_ir_tree(shader
->base
.ir
);
234 do_set_program_inouts(shader
->base
.ir
, prog
, shader
->base
.Stage
);
236 prog
->SamplersUsed
= shader
->base
.active_samplers
;
237 _mesa_update_shader_textures_used(shProg
, prog
);
239 _mesa_reference_program(ctx
, &shader
->base
.Program
, prog
);
241 brw_add_texrect_params(prog
);
243 /* This has to be done last. Any operation that can cause
244 * prog->ParameterValues to get reallocated (e.g., anything that adds a
245 * program constant) has to happen before creating this linkage.
247 _mesa_associate_uniform_storage(ctx
, shProg
, prog
->Parameters
);
249 _mesa_reference_program(ctx
, &prog
, NULL
);
251 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
252 fprintf(stderr
, "\n");
253 fprintf(stderr
, "GLSL IR for linked %s program %d:\n",
254 _mesa_shader_stage_to_string(shader
->base
.Stage
),
256 _mesa_print_ir(stderr
, shader
->base
.ir
, NULL
);
257 fprintf(stderr
, "\n");
261 if ((ctx
->_Shader
->Flags
& GLSL_DUMP
) && shProg
->Name
!= 0) {
262 for (unsigned i
= 0; i
< shProg
->NumShaders
; i
++) {
263 const struct gl_shader
*sh
= shProg
->Shaders
[i
];
267 fprintf(stderr
, "GLSL %s shader %d source for linked program %d:\n",
268 _mesa_shader_stage_to_string(sh
->Stage
),
270 fprintf(stderr
, "%s", sh
->Source
);
271 fprintf(stderr
, "\n");
275 if (!brw_shader_precompile(ctx
, shProg
))
283 brw_type_for_base_type(const struct glsl_type
*type
)
285 switch (type
->base_type
) {
286 case GLSL_TYPE_FLOAT
:
287 return BRW_REGISTER_TYPE_F
;
290 return BRW_REGISTER_TYPE_D
;
292 return BRW_REGISTER_TYPE_UD
;
293 case GLSL_TYPE_ARRAY
:
294 return brw_type_for_base_type(type
->fields
.array
);
295 case GLSL_TYPE_STRUCT
:
296 case GLSL_TYPE_SAMPLER
:
297 case GLSL_TYPE_ATOMIC_UINT
:
298 /* These should be overridden with the type of the member when
299 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
300 * way to trip up if we don't.
302 return BRW_REGISTER_TYPE_UD
;
303 case GLSL_TYPE_IMAGE
:
304 return BRW_REGISTER_TYPE_UD
;
306 case GLSL_TYPE_ERROR
:
307 case GLSL_TYPE_INTERFACE
:
308 unreachable("not reached");
311 return BRW_REGISTER_TYPE_F
;
314 enum brw_conditional_mod
315 brw_conditional_for_comparison(unsigned int op
)
319 return BRW_CONDITIONAL_L
;
320 case ir_binop_greater
:
321 return BRW_CONDITIONAL_G
;
322 case ir_binop_lequal
:
323 return BRW_CONDITIONAL_LE
;
324 case ir_binop_gequal
:
325 return BRW_CONDITIONAL_GE
;
327 case ir_binop_all_equal
: /* same as equal for scalars */
328 return BRW_CONDITIONAL_Z
;
329 case ir_binop_nequal
:
330 case ir_binop_any_nequal
: /* same as nequal for scalars */
331 return BRW_CONDITIONAL_NZ
;
333 unreachable("not reached: bad operation for comparison");
338 brw_math_function(enum opcode op
)
341 case SHADER_OPCODE_RCP
:
342 return BRW_MATH_FUNCTION_INV
;
343 case SHADER_OPCODE_RSQ
:
344 return BRW_MATH_FUNCTION_RSQ
;
345 case SHADER_OPCODE_SQRT
:
346 return BRW_MATH_FUNCTION_SQRT
;
347 case SHADER_OPCODE_EXP2
:
348 return BRW_MATH_FUNCTION_EXP
;
349 case SHADER_OPCODE_LOG2
:
350 return BRW_MATH_FUNCTION_LOG
;
351 case SHADER_OPCODE_POW
:
352 return BRW_MATH_FUNCTION_POW
;
353 case SHADER_OPCODE_SIN
:
354 return BRW_MATH_FUNCTION_SIN
;
355 case SHADER_OPCODE_COS
:
356 return BRW_MATH_FUNCTION_COS
;
357 case SHADER_OPCODE_INT_QUOTIENT
:
358 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
359 case SHADER_OPCODE_INT_REMAINDER
:
360 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
362 unreachable("not reached: unknown math function");
367 brw_texture_offset(struct gl_context
*ctx
, ir_constant
*offset
)
369 /* If the driver does not support GL_ARB_gpu_shader5, the offset
372 assert(offset
!= NULL
|| ctx
->Extensions
.ARB_gpu_shader5
);
374 if (!offset
) return 0; /* nonconstant offset; caller will handle it. */
376 signed char offsets
[3];
377 for (unsigned i
= 0; i
< offset
->type
->vector_elements
; i
++)
378 offsets
[i
] = (signed char) offset
->value
.i
[i
];
380 /* Combine all three offsets into a single unsigned dword:
382 * bits 11:8 - U Offset (X component)
383 * bits 7:4 - V Offset (Y component)
384 * bits 3:0 - R Offset (Z component)
386 unsigned offset_bits
= 0;
387 for (unsigned i
= 0; i
< offset
->type
->vector_elements
; i
++) {
388 const unsigned shift
= 4 * (2 - i
);
389 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
395 brw_instruction_name(enum opcode op
)
399 if (op
< ARRAY_SIZE(opcode_descs
) && opcode_descs
[op
].name
)
400 return opcode_descs
[op
].name
;
403 case FS_OPCODE_FB_WRITE
:
405 case FS_OPCODE_BLORP_FB_WRITE
:
406 return "blorp_fb_write";
408 case SHADER_OPCODE_RCP
:
410 case SHADER_OPCODE_RSQ
:
412 case SHADER_OPCODE_SQRT
:
414 case SHADER_OPCODE_EXP2
:
416 case SHADER_OPCODE_LOG2
:
418 case SHADER_OPCODE_POW
:
420 case SHADER_OPCODE_INT_QUOTIENT
:
422 case SHADER_OPCODE_INT_REMAINDER
:
424 case SHADER_OPCODE_SIN
:
426 case SHADER_OPCODE_COS
:
429 case SHADER_OPCODE_TEX
:
431 case SHADER_OPCODE_TXD
:
433 case SHADER_OPCODE_TXF
:
435 case SHADER_OPCODE_TXL
:
437 case SHADER_OPCODE_TXS
:
441 case SHADER_OPCODE_TXF_CMS
:
443 case SHADER_OPCODE_TXF_UMS
:
445 case SHADER_OPCODE_TXF_MCS
:
447 case SHADER_OPCODE_TG4
:
449 case SHADER_OPCODE_TG4_OFFSET
:
451 case SHADER_OPCODE_SHADER_TIME_ADD
:
452 return "shader_time_add";
454 case SHADER_OPCODE_LOAD_PAYLOAD
:
455 return "load_payload";
457 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
458 return "gen4_scratch_read";
459 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
460 return "gen4_scratch_write";
461 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
462 return "gen7_scratch_read";
469 case FS_OPCODE_PIXEL_X
:
471 case FS_OPCODE_PIXEL_Y
:
474 case FS_OPCODE_CINTERP
:
476 case FS_OPCODE_LINTERP
:
479 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
480 return "uniform_pull_const";
481 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
482 return "uniform_pull_const_gen7";
483 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
484 return "varying_pull_const";
485 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
486 return "varying_pull_const_gen7";
488 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
489 return "mov_dispatch_to_flags";
490 case FS_OPCODE_DISCARD_JUMP
:
491 return "discard_jump";
493 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
494 return "set_simd4x2_offset";
496 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
497 return "pack_half_2x16_split";
498 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
499 return "unpack_half_2x16_split_x";
500 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
501 return "unpack_half_2x16_split_y";
503 case FS_OPCODE_PLACEHOLDER_HALT
:
504 return "placeholder_halt";
506 case VS_OPCODE_URB_WRITE
:
507 return "vs_urb_write";
508 case VS_OPCODE_PULL_CONSTANT_LOAD
:
509 return "pull_constant_load";
510 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
511 return "pull_constant_load_gen7";
512 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
513 return "unpack_flags_simd4x2";
515 case GS_OPCODE_URB_WRITE
:
516 return "gs_urb_write";
517 case GS_OPCODE_THREAD_END
:
518 return "gs_thread_end";
519 case GS_OPCODE_SET_WRITE_OFFSET
:
520 return "set_write_offset";
521 case GS_OPCODE_SET_VERTEX_COUNT
:
522 return "set_vertex_count";
523 case GS_OPCODE_SET_DWORD_2_IMMED
:
524 return "set_dword_2_immed";
525 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
526 return "prepare_channel_masks";
527 case GS_OPCODE_SET_CHANNEL_MASKS
:
528 return "set_channel_masks";
529 case GS_OPCODE_GET_INSTANCE_ID
:
530 return "get_instance_id";
533 /* Yes, this leaks. It's in debug code, it should never occur, and if
534 * it does, you should just add the case to the list above.
536 asprintf(&fallback
, "op%d", op
);
541 backend_visitor::backend_visitor(struct brw_context
*brw
,
542 struct gl_shader_program
*shader_prog
,
543 struct gl_program
*prog
,
544 struct brw_stage_prog_data
*stage_prog_data
,
545 gl_shader_stage stage
)
549 (struct brw_shader
*)shader_prog
->_LinkedShaders
[stage
] : NULL
),
550 shader_prog(shader_prog
),
552 stage_prog_data(stage_prog_data
)
557 backend_reg::is_zero() const
562 return fixed_hw_reg
.dw1
.d
== 0;
566 backend_reg::is_one() const
571 return type
== BRW_REGISTER_TYPE_F
572 ? fixed_hw_reg
.dw1
.f
== 1.0
573 : fixed_hw_reg
.dw1
.d
== 1;
577 backend_reg::is_null() const
579 return file
== HW_REG
&&
580 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
581 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
586 backend_reg::is_accumulator() const
588 return file
== HW_REG
&&
589 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
590 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
594 backend_instruction::is_tex() const
596 return (opcode
== SHADER_OPCODE_TEX
||
597 opcode
== FS_OPCODE_TXB
||
598 opcode
== SHADER_OPCODE_TXD
||
599 opcode
== SHADER_OPCODE_TXF
||
600 opcode
== SHADER_OPCODE_TXF_CMS
||
601 opcode
== SHADER_OPCODE_TXF_UMS
||
602 opcode
== SHADER_OPCODE_TXF_MCS
||
603 opcode
== SHADER_OPCODE_TXL
||
604 opcode
== SHADER_OPCODE_TXS
||
605 opcode
== SHADER_OPCODE_LOD
||
606 opcode
== SHADER_OPCODE_TG4
||
607 opcode
== SHADER_OPCODE_TG4_OFFSET
);
611 backend_instruction::is_math() const
613 return (opcode
== SHADER_OPCODE_RCP
||
614 opcode
== SHADER_OPCODE_RSQ
||
615 opcode
== SHADER_OPCODE_SQRT
||
616 opcode
== SHADER_OPCODE_EXP2
||
617 opcode
== SHADER_OPCODE_LOG2
||
618 opcode
== SHADER_OPCODE_SIN
||
619 opcode
== SHADER_OPCODE_COS
||
620 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
621 opcode
== SHADER_OPCODE_INT_REMAINDER
||
622 opcode
== SHADER_OPCODE_POW
);
626 backend_instruction::is_control_flow() const
630 case BRW_OPCODE_WHILE
:
632 case BRW_OPCODE_ELSE
:
633 case BRW_OPCODE_ENDIF
:
634 case BRW_OPCODE_BREAK
:
635 case BRW_OPCODE_CONTINUE
:
643 backend_instruction::can_do_source_mods() const
646 case BRW_OPCODE_ADDC
:
648 case BRW_OPCODE_BFI1
:
649 case BRW_OPCODE_BFI2
:
650 case BRW_OPCODE_BFREV
:
651 case BRW_OPCODE_CBIT
:
654 case BRW_OPCODE_SUBB
:
662 backend_instruction::can_do_saturate() const
672 case BRW_OPCODE_F16TO32
:
673 case BRW_OPCODE_F32TO16
:
674 case BRW_OPCODE_LINE
:
677 case BRW_OPCODE_MACH
:
679 case BRW_OPCODE_MATH
:
683 case BRW_OPCODE_RNDD
:
684 case BRW_OPCODE_RNDE
:
685 case BRW_OPCODE_RNDU
:
686 case BRW_OPCODE_RNDZ
:
690 case FS_OPCODE_LINTERP
:
691 case SHADER_OPCODE_COS
:
692 case SHADER_OPCODE_EXP2
:
693 case SHADER_OPCODE_LOG2
:
694 case SHADER_OPCODE_POW
:
695 case SHADER_OPCODE_RCP
:
696 case SHADER_OPCODE_RSQ
:
697 case SHADER_OPCODE_SIN
:
698 case SHADER_OPCODE_SQRT
:
706 backend_instruction::reads_accumulator_implicitly() const
710 case BRW_OPCODE_MACH
:
711 case BRW_OPCODE_SADA2
:
719 backend_instruction::writes_accumulator_implicitly(struct brw_context
*brw
) const
721 return writes_accumulator
||
723 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
724 (opcode
>= FS_OPCODE_DDX
&& opcode
<= FS_OPCODE_LINTERP
&&
725 opcode
!= FS_OPCODE_CINTERP
)));
729 backend_instruction::has_side_effects() const
732 case SHADER_OPCODE_UNTYPED_ATOMIC
:
740 backend_visitor::dump_instructions()
742 dump_instructions(NULL
);
746 backend_visitor::dump_instructions(const char *name
)
749 if (name
&& geteuid() != 0) {
750 file
= fopen(name
, "w");
756 foreach_in_list(backend_instruction
, inst
, &instructions
) {
758 fprintf(stderr
, "%d: ", ip
++);
759 dump_instruction(inst
, file
);
762 if (file
!= stderr
) {
769 * Sets up the starting offsets for the groups of binding table entries
770 * commong to all pipeline stages.
772 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
773 * unused but also make sure that addition of small offsets to them will
774 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
777 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset
)
779 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
781 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
782 next_binding_table_offset
+= num_textures
;
785 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
786 next_binding_table_offset
+= shader
->base
.NumUniformBlocks
;
788 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
791 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
792 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
793 next_binding_table_offset
++;
795 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
798 if (prog
->UsesGather
) {
800 stage_prog_data
->binding_table
.gather_texture_start
=
801 stage_prog_data
->binding_table
.texture_start
;
803 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
804 next_binding_table_offset
+= num_textures
;
807 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
810 if (shader_prog
&& shader_prog
->NumAtomicBuffers
) {
811 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
812 next_binding_table_offset
+= shader_prog
->NumAtomicBuffers
;
814 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
817 /* This may or may not be used depending on how the compile goes. */
818 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
819 next_binding_table_offset
++;
821 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
823 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */