2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
29 #include "brw_vec4_tes.h"
30 #include "glsl/glsl_parser_extras.h"
31 #include "main/shaderobj.h"
32 #include "main/uniforms.h"
33 #include "util/debug.h"
36 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
38 struct brw_context
*brw
= (struct brw_context
*)data
;
43 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
44 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
45 MESA_DEBUG_TYPE_OTHER
,
46 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
51 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
53 struct brw_context
*brw
= (struct brw_context
*)data
;
58 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
60 va_copy(args_copy
, args
);
61 vfprintf(stderr
, fmt
, args_copy
);
65 if (brw
->perf_debug
) {
67 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
68 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
69 MESA_DEBUG_TYPE_PERFORMANCE
,
70 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
76 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
78 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
80 compiler
->devinfo
= devinfo
;
81 compiler
->shader_debug_log
= shader_debug_log_mesa
;
82 compiler
->shader_perf_log
= shader_perf_log_mesa
;
84 brw_fs_alloc_reg_sets(compiler
);
85 brw_vec4_alloc_reg_set(compiler
);
87 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
88 devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
);
89 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
] = false;
90 compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
] =
91 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
92 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
93 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
94 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
95 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
97 nir_shader_compiler_options
*nir_options
=
98 rzalloc(compiler
, nir_shader_compiler_options
);
99 nir_options
->native_integers
= true;
100 /* In order to help allow for better CSE at the NIR level we tell NIR
101 * to split all ffma instructions during opt_algebraic and we then
102 * re-combine them as a later step.
104 nir_options
->lower_ffma
= true;
105 nir_options
->lower_sub
= true;
106 /* In the vec4 backend, our dpN instruction replicates its result to all
107 * the components of a vec4. We would like NIR to give us replicated fdot
108 * instructions because it can optimize better for us.
110 * For the FS backend, it should be lowered away by the scalarizing pass so
111 * we should never see fdot anyway.
113 nir_options
->fdot_replicates
= true;
115 /* We want the GLSL compiler to emit code that uses condition codes */
116 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
117 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
118 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
119 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
121 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
122 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
123 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
124 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
125 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
126 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
128 bool is_scalar
= compiler
->scalar_stage
[i
];
130 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
131 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
132 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
134 /* !ARB_gpu_shader5 */
135 if (devinfo
->gen
< 7)
136 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
138 compiler
->glsl_compiler_options
[i
].NirOptions
= nir_options
;
140 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
143 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectInput
= false;
144 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_EVAL
].EmitNoIndirectInput
= false;
146 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
147 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
149 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
]
150 .LowerShaderSharedVariables
= true;
155 extern "C" struct gl_shader
*
156 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
158 struct brw_shader
*shader
;
160 shader
= rzalloc(NULL
, struct brw_shader
);
162 shader
->base
.Type
= type
;
163 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
164 shader
->base
.Name
= name
;
165 _mesa_init_shader(ctx
, &shader
->base
);
168 return &shader
->base
;
172 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
175 assert(surf_index
< BRW_MAX_SURFACES
);
177 prog_data
->binding_table
.size_bytes
=
178 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
182 brw_type_for_base_type(const struct glsl_type
*type
)
184 switch (type
->base_type
) {
185 case GLSL_TYPE_FLOAT
:
186 return BRW_REGISTER_TYPE_F
;
189 case GLSL_TYPE_SUBROUTINE
:
190 return BRW_REGISTER_TYPE_D
;
192 return BRW_REGISTER_TYPE_UD
;
193 case GLSL_TYPE_ARRAY
:
194 return brw_type_for_base_type(type
->fields
.array
);
195 case GLSL_TYPE_STRUCT
:
196 case GLSL_TYPE_SAMPLER
:
197 case GLSL_TYPE_ATOMIC_UINT
:
198 /* These should be overridden with the type of the member when
199 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
200 * way to trip up if we don't.
202 return BRW_REGISTER_TYPE_UD
;
203 case GLSL_TYPE_IMAGE
:
204 return BRW_REGISTER_TYPE_UD
;
206 case GLSL_TYPE_ERROR
:
207 case GLSL_TYPE_INTERFACE
:
208 case GLSL_TYPE_DOUBLE
:
209 unreachable("not reached");
212 return BRW_REGISTER_TYPE_F
;
215 enum brw_conditional_mod
216 brw_conditional_for_comparison(unsigned int op
)
220 return BRW_CONDITIONAL_L
;
221 case ir_binop_greater
:
222 return BRW_CONDITIONAL_G
;
223 case ir_binop_lequal
:
224 return BRW_CONDITIONAL_LE
;
225 case ir_binop_gequal
:
226 return BRW_CONDITIONAL_GE
;
228 case ir_binop_all_equal
: /* same as equal for scalars */
229 return BRW_CONDITIONAL_Z
;
230 case ir_binop_nequal
:
231 case ir_binop_any_nequal
: /* same as nequal for scalars */
232 return BRW_CONDITIONAL_NZ
;
234 unreachable("not reached: bad operation for comparison");
239 brw_math_function(enum opcode op
)
242 case SHADER_OPCODE_RCP
:
243 return BRW_MATH_FUNCTION_INV
;
244 case SHADER_OPCODE_RSQ
:
245 return BRW_MATH_FUNCTION_RSQ
;
246 case SHADER_OPCODE_SQRT
:
247 return BRW_MATH_FUNCTION_SQRT
;
248 case SHADER_OPCODE_EXP2
:
249 return BRW_MATH_FUNCTION_EXP
;
250 case SHADER_OPCODE_LOG2
:
251 return BRW_MATH_FUNCTION_LOG
;
252 case SHADER_OPCODE_POW
:
253 return BRW_MATH_FUNCTION_POW
;
254 case SHADER_OPCODE_SIN
:
255 return BRW_MATH_FUNCTION_SIN
;
256 case SHADER_OPCODE_COS
:
257 return BRW_MATH_FUNCTION_COS
;
258 case SHADER_OPCODE_INT_QUOTIENT
:
259 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
260 case SHADER_OPCODE_INT_REMAINDER
:
261 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
263 unreachable("not reached: unknown math function");
268 brw_texture_offset(int *offsets
, unsigned num_components
)
270 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
272 /* Combine all three offsets into a single unsigned dword:
274 * bits 11:8 - U Offset (X component)
275 * bits 7:4 - V Offset (Y component)
276 * bits 3:0 - R Offset (Z component)
278 unsigned offset_bits
= 0;
279 for (unsigned i
= 0; i
< num_components
; i
++) {
280 const unsigned shift
= 4 * (2 - i
);
281 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
287 brw_instruction_name(enum opcode op
)
290 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
291 assert(opcode_descs
[op
].name
);
292 return opcode_descs
[op
].name
;
293 case FS_OPCODE_FB_WRITE
:
295 case FS_OPCODE_FB_WRITE_LOGICAL
:
296 return "fb_write_logical";
297 case FS_OPCODE_PACK_STENCIL_REF
:
298 return "pack_stencil_ref";
299 case FS_OPCODE_BLORP_FB_WRITE
:
300 return "blorp_fb_write";
301 case FS_OPCODE_REP_FB_WRITE
:
302 return "rep_fb_write";
304 case SHADER_OPCODE_RCP
:
306 case SHADER_OPCODE_RSQ
:
308 case SHADER_OPCODE_SQRT
:
310 case SHADER_OPCODE_EXP2
:
312 case SHADER_OPCODE_LOG2
:
314 case SHADER_OPCODE_POW
:
316 case SHADER_OPCODE_INT_QUOTIENT
:
318 case SHADER_OPCODE_INT_REMAINDER
:
320 case SHADER_OPCODE_SIN
:
322 case SHADER_OPCODE_COS
:
325 case SHADER_OPCODE_TEX
:
327 case SHADER_OPCODE_TEX_LOGICAL
:
328 return "tex_logical";
329 case SHADER_OPCODE_TXD
:
331 case SHADER_OPCODE_TXD_LOGICAL
:
332 return "txd_logical";
333 case SHADER_OPCODE_TXF
:
335 case SHADER_OPCODE_TXF_LOGICAL
:
336 return "txf_logical";
337 case SHADER_OPCODE_TXL
:
339 case SHADER_OPCODE_TXL_LOGICAL
:
340 return "txl_logical";
341 case SHADER_OPCODE_TXS
:
343 case SHADER_OPCODE_TXS_LOGICAL
:
344 return "txs_logical";
347 case FS_OPCODE_TXB_LOGICAL
:
348 return "txb_logical";
349 case SHADER_OPCODE_TXF_CMS
:
351 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
352 return "txf_cms_logical";
353 case SHADER_OPCODE_TXF_CMS_W
:
355 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
356 return "txf_cms_w_logical";
357 case SHADER_OPCODE_TXF_UMS
:
359 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
360 return "txf_ums_logical";
361 case SHADER_OPCODE_TXF_MCS
:
363 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
364 return "txf_mcs_logical";
365 case SHADER_OPCODE_LOD
:
367 case SHADER_OPCODE_LOD_LOGICAL
:
368 return "lod_logical";
369 case SHADER_OPCODE_TG4
:
371 case SHADER_OPCODE_TG4_LOGICAL
:
372 return "tg4_logical";
373 case SHADER_OPCODE_TG4_OFFSET
:
375 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
376 return "tg4_offset_logical";
377 case SHADER_OPCODE_SAMPLEINFO
:
380 case SHADER_OPCODE_SHADER_TIME_ADD
:
381 return "shader_time_add";
383 case SHADER_OPCODE_UNTYPED_ATOMIC
:
384 return "untyped_atomic";
385 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
386 return "untyped_atomic_logical";
387 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
388 return "untyped_surface_read";
389 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
390 return "untyped_surface_read_logical";
391 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
392 return "untyped_surface_write";
393 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
394 return "untyped_surface_write_logical";
395 case SHADER_OPCODE_TYPED_ATOMIC
:
396 return "typed_atomic";
397 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
398 return "typed_atomic_logical";
399 case SHADER_OPCODE_TYPED_SURFACE_READ
:
400 return "typed_surface_read";
401 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
402 return "typed_surface_read_logical";
403 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
404 return "typed_surface_write";
405 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
406 return "typed_surface_write_logical";
407 case SHADER_OPCODE_MEMORY_FENCE
:
408 return "memory_fence";
410 case SHADER_OPCODE_LOAD_PAYLOAD
:
411 return "load_payload";
413 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
414 return "gen4_scratch_read";
415 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
416 return "gen4_scratch_write";
417 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
418 return "gen7_scratch_read";
419 case SHADER_OPCODE_URB_WRITE_SIMD8
:
420 return "gen8_urb_write_simd8";
421 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
422 return "gen8_urb_write_simd8_per_slot";
423 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
424 return "gen8_urb_write_simd8_masked";
425 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
426 return "gen8_urb_write_simd8_masked_per_slot";
427 case SHADER_OPCODE_URB_READ_SIMD8
:
428 return "urb_read_simd8";
429 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
430 return "urb_read_simd8_per_slot";
432 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
433 return "find_live_channel";
434 case SHADER_OPCODE_BROADCAST
:
437 case VEC4_OPCODE_MOV_BYTES
:
439 case VEC4_OPCODE_PACK_BYTES
:
441 case VEC4_OPCODE_UNPACK_UNIFORM
:
442 return "unpack_uniform";
444 case FS_OPCODE_DDX_COARSE
:
446 case FS_OPCODE_DDX_FINE
:
448 case FS_OPCODE_DDY_COARSE
:
450 case FS_OPCODE_DDY_FINE
:
453 case FS_OPCODE_CINTERP
:
455 case FS_OPCODE_LINTERP
:
458 case FS_OPCODE_PIXEL_X
:
460 case FS_OPCODE_PIXEL_Y
:
463 case FS_OPCODE_GET_BUFFER_SIZE
:
464 return "fs_get_buffer_size";
466 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
467 return "uniform_pull_const";
468 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
469 return "uniform_pull_const_gen7";
470 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
471 return "varying_pull_const";
472 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
473 return "varying_pull_const_gen7";
475 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
476 return "mov_dispatch_to_flags";
477 case FS_OPCODE_DISCARD_JUMP
:
478 return "discard_jump";
480 case FS_OPCODE_SET_SAMPLE_ID
:
481 return "set_sample_id";
482 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
483 return "set_simd4x2_offset";
485 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
486 return "pack_half_2x16_split";
487 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
488 return "unpack_half_2x16_split_x";
489 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
490 return "unpack_half_2x16_split_y";
492 case FS_OPCODE_PLACEHOLDER_HALT
:
493 return "placeholder_halt";
495 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
496 return "interp_centroid";
497 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
498 return "interp_sample";
499 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
500 return "interp_shared_offset";
501 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
502 return "interp_per_slot_offset";
504 case VS_OPCODE_URB_WRITE
:
505 return "vs_urb_write";
506 case VS_OPCODE_PULL_CONSTANT_LOAD
:
507 return "pull_constant_load";
508 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
509 return "pull_constant_load_gen7";
511 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
512 return "set_simd4x2_header_gen9";
514 case VS_OPCODE_GET_BUFFER_SIZE
:
515 return "vs_get_buffer_size";
517 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
518 return "unpack_flags_simd4x2";
520 case GS_OPCODE_URB_WRITE
:
521 return "gs_urb_write";
522 case GS_OPCODE_URB_WRITE_ALLOCATE
:
523 return "gs_urb_write_allocate";
524 case GS_OPCODE_THREAD_END
:
525 return "gs_thread_end";
526 case GS_OPCODE_SET_WRITE_OFFSET
:
527 return "set_write_offset";
528 case GS_OPCODE_SET_VERTEX_COUNT
:
529 return "set_vertex_count";
530 case GS_OPCODE_SET_DWORD_2
:
531 return "set_dword_2";
532 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
533 return "prepare_channel_masks";
534 case GS_OPCODE_SET_CHANNEL_MASKS
:
535 return "set_channel_masks";
536 case GS_OPCODE_GET_INSTANCE_ID
:
537 return "get_instance_id";
538 case GS_OPCODE_FF_SYNC
:
540 case GS_OPCODE_SET_PRIMITIVE_ID
:
541 return "set_primitive_id";
542 case GS_OPCODE_SVB_WRITE
:
543 return "gs_svb_write";
544 case GS_OPCODE_SVB_SET_DST_INDEX
:
545 return "gs_svb_set_dst_index";
546 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
547 return "gs_ff_sync_set_primitives";
548 case CS_OPCODE_CS_TERMINATE
:
549 return "cs_terminate";
550 case SHADER_OPCODE_BARRIER
:
552 case SHADER_OPCODE_MULH
:
554 case SHADER_OPCODE_MOV_INDIRECT
:
555 return "mov_indirect";
557 case VEC4_OPCODE_URB_READ
:
559 case TCS_OPCODE_GET_INSTANCE_ID
:
560 return "tcs_get_instance_id";
561 case TCS_OPCODE_URB_WRITE
:
562 return "tcs_urb_write";
563 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
564 return "tcs_set_input_urb_offsets";
565 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
566 return "tcs_set_output_urb_offsets";
567 case TCS_OPCODE_GET_PRIMITIVE_ID
:
568 return "tcs_get_primitive_id";
569 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
570 return "tcs_create_barrier_header";
571 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
572 return "tes_create_input_read_header";
573 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
574 return "tes_add_indirect_urb_offset";
575 case TES_OPCODE_GET_PRIMITIVE_ID
:
576 return "tes_get_primitive_id";
579 unreachable("not reached");
583 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
589 } imm
= { reg
->ud
}, sat_imm
= { 0 };
592 case BRW_REGISTER_TYPE_UD
:
593 case BRW_REGISTER_TYPE_D
:
594 case BRW_REGISTER_TYPE_UW
:
595 case BRW_REGISTER_TYPE_W
:
596 case BRW_REGISTER_TYPE_UQ
:
597 case BRW_REGISTER_TYPE_Q
:
600 case BRW_REGISTER_TYPE_F
:
601 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
603 case BRW_REGISTER_TYPE_UB
:
604 case BRW_REGISTER_TYPE_B
:
605 unreachable("no UB/B immediates");
606 case BRW_REGISTER_TYPE_V
:
607 case BRW_REGISTER_TYPE_UV
:
608 case BRW_REGISTER_TYPE_VF
:
609 unreachable("unimplemented: saturate vector immediate");
610 case BRW_REGISTER_TYPE_DF
:
611 case BRW_REGISTER_TYPE_HF
:
612 unreachable("unimplemented: saturate DF/HF immediate");
615 if (imm
.ud
!= sat_imm
.ud
) {
616 reg
->ud
= sat_imm
.ud
;
623 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
626 case BRW_REGISTER_TYPE_D
:
627 case BRW_REGISTER_TYPE_UD
:
630 case BRW_REGISTER_TYPE_W
:
631 case BRW_REGISTER_TYPE_UW
:
632 reg
->d
= -(int16_t)reg
->ud
;
634 case BRW_REGISTER_TYPE_F
:
637 case BRW_REGISTER_TYPE_VF
:
638 reg
->ud
^= 0x80808080;
640 case BRW_REGISTER_TYPE_UB
:
641 case BRW_REGISTER_TYPE_B
:
642 unreachable("no UB/B immediates");
643 case BRW_REGISTER_TYPE_UV
:
644 case BRW_REGISTER_TYPE_V
:
645 assert(!"unimplemented: negate UV/V immediate");
646 case BRW_REGISTER_TYPE_UQ
:
647 case BRW_REGISTER_TYPE_Q
:
648 assert(!"unimplemented: negate UQ/Q immediate");
649 case BRW_REGISTER_TYPE_DF
:
650 case BRW_REGISTER_TYPE_HF
:
651 assert(!"unimplemented: negate DF/HF immediate");
658 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
661 case BRW_REGISTER_TYPE_D
:
662 reg
->d
= abs(reg
->d
);
664 case BRW_REGISTER_TYPE_W
:
665 reg
->d
= abs((int16_t)reg
->ud
);
667 case BRW_REGISTER_TYPE_F
:
668 reg
->f
= fabsf(reg
->f
);
670 case BRW_REGISTER_TYPE_VF
:
671 reg
->ud
&= ~0x80808080;
673 case BRW_REGISTER_TYPE_UB
:
674 case BRW_REGISTER_TYPE_B
:
675 unreachable("no UB/B immediates");
676 case BRW_REGISTER_TYPE_UQ
:
677 case BRW_REGISTER_TYPE_UD
:
678 case BRW_REGISTER_TYPE_UW
:
679 case BRW_REGISTER_TYPE_UV
:
680 /* Presumably the absolute value modifier on an unsigned source is a
681 * nop, but it would be nice to confirm.
683 assert(!"unimplemented: abs unsigned immediate");
684 case BRW_REGISTER_TYPE_V
:
685 assert(!"unimplemented: abs V immediate");
686 case BRW_REGISTER_TYPE_Q
:
687 assert(!"unimplemented: abs Q immediate");
688 case BRW_REGISTER_TYPE_DF
:
689 case BRW_REGISTER_TYPE_HF
:
690 assert(!"unimplemented: abs DF/HF immediate");
696 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
699 const nir_shader
*shader
,
700 struct brw_stage_prog_data
*stage_prog_data
)
701 : compiler(compiler
),
703 devinfo(compiler
->devinfo
),
705 stage_prog_data(stage_prog_data
),
710 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
711 stage_name
= _mesa_shader_stage_to_string(stage
);
712 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
716 backend_reg::equals(const backend_reg
&r
) const
718 return memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
719 reg_offset
== r
.reg_offset
;
723 backend_reg::is_zero() const
732 backend_reg::is_one() const
737 return type
== BRW_REGISTER_TYPE_F
743 backend_reg::is_negative_one() const
749 case BRW_REGISTER_TYPE_F
:
751 case BRW_REGISTER_TYPE_D
:
759 backend_reg::is_null() const
761 return file
== ARF
&& nr
== BRW_ARF_NULL
;
766 backend_reg::is_accumulator() const
768 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
772 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
774 return (file
== r
.file
&&
776 reg_offset
>= r
.reg_offset
&&
777 reg_offset
< r
.reg_offset
+ n
);
781 backend_instruction::is_commutative() const
789 case SHADER_OPCODE_MULH
:
792 /* MIN and MAX are commutative. */
793 if (conditional_mod
== BRW_CONDITIONAL_GE
||
794 conditional_mod
== BRW_CONDITIONAL_L
) {
804 backend_instruction::is_3src() const
806 return ::is_3src(opcode
);
810 backend_instruction::is_tex() const
812 return (opcode
== SHADER_OPCODE_TEX
||
813 opcode
== FS_OPCODE_TXB
||
814 opcode
== SHADER_OPCODE_TXD
||
815 opcode
== SHADER_OPCODE_TXF
||
816 opcode
== SHADER_OPCODE_TXF_CMS
||
817 opcode
== SHADER_OPCODE_TXF_CMS_W
||
818 opcode
== SHADER_OPCODE_TXF_UMS
||
819 opcode
== SHADER_OPCODE_TXF_MCS
||
820 opcode
== SHADER_OPCODE_TXL
||
821 opcode
== SHADER_OPCODE_TXS
||
822 opcode
== SHADER_OPCODE_LOD
||
823 opcode
== SHADER_OPCODE_TG4
||
824 opcode
== SHADER_OPCODE_TG4_OFFSET
);
828 backend_instruction::is_math() const
830 return (opcode
== SHADER_OPCODE_RCP
||
831 opcode
== SHADER_OPCODE_RSQ
||
832 opcode
== SHADER_OPCODE_SQRT
||
833 opcode
== SHADER_OPCODE_EXP2
||
834 opcode
== SHADER_OPCODE_LOG2
||
835 opcode
== SHADER_OPCODE_SIN
||
836 opcode
== SHADER_OPCODE_COS
||
837 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
838 opcode
== SHADER_OPCODE_INT_REMAINDER
||
839 opcode
== SHADER_OPCODE_POW
);
843 backend_instruction::is_control_flow() const
847 case BRW_OPCODE_WHILE
:
849 case BRW_OPCODE_ELSE
:
850 case BRW_OPCODE_ENDIF
:
851 case BRW_OPCODE_BREAK
:
852 case BRW_OPCODE_CONTINUE
:
860 backend_instruction::can_do_source_mods() const
863 case BRW_OPCODE_ADDC
:
865 case BRW_OPCODE_BFI1
:
866 case BRW_OPCODE_BFI2
:
867 case BRW_OPCODE_BFREV
:
868 case BRW_OPCODE_CBIT
:
871 case BRW_OPCODE_SUBB
:
879 backend_instruction::can_do_saturate() const
889 case BRW_OPCODE_F16TO32
:
890 case BRW_OPCODE_F32TO16
:
891 case BRW_OPCODE_LINE
:
895 case BRW_OPCODE_MATH
:
898 case SHADER_OPCODE_MULH
:
900 case BRW_OPCODE_RNDD
:
901 case BRW_OPCODE_RNDE
:
902 case BRW_OPCODE_RNDU
:
903 case BRW_OPCODE_RNDZ
:
907 case FS_OPCODE_LINTERP
:
908 case SHADER_OPCODE_COS
:
909 case SHADER_OPCODE_EXP2
:
910 case SHADER_OPCODE_LOG2
:
911 case SHADER_OPCODE_POW
:
912 case SHADER_OPCODE_RCP
:
913 case SHADER_OPCODE_RSQ
:
914 case SHADER_OPCODE_SIN
:
915 case SHADER_OPCODE_SQRT
:
923 backend_instruction::can_do_cmod() const
927 case BRW_OPCODE_ADDC
:
932 case BRW_OPCODE_CMPN
:
937 case BRW_OPCODE_F16TO32
:
938 case BRW_OPCODE_F32TO16
:
940 case BRW_OPCODE_LINE
:
944 case BRW_OPCODE_MACH
:
951 case BRW_OPCODE_RNDD
:
952 case BRW_OPCODE_RNDE
:
953 case BRW_OPCODE_RNDU
:
954 case BRW_OPCODE_RNDZ
:
955 case BRW_OPCODE_SAD2
:
956 case BRW_OPCODE_SADA2
:
959 case BRW_OPCODE_SUBB
:
961 case FS_OPCODE_CINTERP
:
962 case FS_OPCODE_LINTERP
:
970 backend_instruction::reads_accumulator_implicitly() const
974 case BRW_OPCODE_MACH
:
975 case BRW_OPCODE_SADA2
:
983 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
985 return writes_accumulator
||
987 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
988 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
989 opcode
!= FS_OPCODE_CINTERP
)));
993 backend_instruction::has_side_effects() const
996 case SHADER_OPCODE_UNTYPED_ATOMIC
:
997 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
998 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
999 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1000 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1001 case SHADER_OPCODE_TYPED_ATOMIC
:
1002 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1003 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1004 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1005 case SHADER_OPCODE_MEMORY_FENCE
:
1006 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1007 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1008 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1009 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1010 case FS_OPCODE_FB_WRITE
:
1011 case SHADER_OPCODE_BARRIER
:
1019 backend_instruction::is_volatile() const
1022 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1023 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1024 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1025 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1034 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1037 foreach_inst_in_block (backend_instruction
, i
, block
) {
1047 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1049 for (bblock_t
*block_iter
= start_block
->next();
1050 !block_iter
->link
.is_tail_sentinel();
1051 block_iter
= block_iter
->next()) {
1052 block_iter
->start_ip
+= ip_adjustment
;
1053 block_iter
->end_ip
+= ip_adjustment
;
1058 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1060 if (!this->is_head_sentinel())
1061 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1065 adjust_later_block_ips(block
, 1);
1067 exec_node::insert_after(inst
);
1071 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1073 if (!this->is_tail_sentinel())
1074 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1078 adjust_later_block_ips(block
, 1);
1080 exec_node::insert_before(inst
);
1084 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1086 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1088 unsigned num_inst
= list
->length();
1090 block
->end_ip
+= num_inst
;
1092 adjust_later_block_ips(block
, num_inst
);
1094 exec_node::insert_before(list
);
1098 backend_instruction::remove(bblock_t
*block
)
1100 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1102 adjust_later_block_ips(block
, -1);
1104 if (block
->start_ip
== block
->end_ip
) {
1105 block
->cfg
->remove_block(block
);
1110 exec_node::remove();
1114 backend_shader::dump_instructions()
1116 dump_instructions(NULL
);
1120 backend_shader::dump_instructions(const char *name
)
1122 FILE *file
= stderr
;
1123 if (name
&& geteuid() != 0) {
1124 file
= fopen(name
, "w");
1131 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1132 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1133 fprintf(file
, "%4d: ", ip
++);
1134 dump_instruction(inst
, file
);
1138 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1139 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1140 fprintf(file
, "%4d: ", ip
++);
1141 dump_instruction(inst
, file
);
1145 if (file
!= stderr
) {
1151 backend_shader::calculate_cfg()
1155 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1159 backend_shader::invalidate_cfg()
1161 ralloc_free(this->cfg
);
1166 * Sets up the starting offsets for the groups of binding table entries
1167 * commong to all pipeline stages.
1169 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1170 * unused but also make sure that addition of small offsets to them will
1171 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1174 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1175 const struct brw_device_info
*devinfo
,
1176 const struct gl_shader_program
*shader_prog
,
1177 const struct gl_program
*prog
,
1178 struct brw_stage_prog_data
*stage_prog_data
,
1179 uint32_t next_binding_table_offset
)
1181 const struct gl_shader
*shader
= NULL
;
1182 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1185 shader
= shader_prog
->_LinkedShaders
[stage
];
1187 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1188 next_binding_table_offset
+= num_textures
;
1191 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1192 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1193 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1195 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1196 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1197 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1199 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1200 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1203 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1204 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1205 next_binding_table_offset
++;
1207 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1210 if (prog
->UsesGather
) {
1211 if (devinfo
->gen
>= 8) {
1212 stage_prog_data
->binding_table
.gather_texture_start
=
1213 stage_prog_data
->binding_table
.texture_start
;
1215 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1216 next_binding_table_offset
+= num_textures
;
1219 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1222 if (shader
&& shader
->NumAtomicBuffers
) {
1223 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1224 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1226 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1229 if (shader
&& shader
->NumImages
) {
1230 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1231 next_binding_table_offset
+= shader
->NumImages
;
1233 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1236 /* This may or may not be used depending on how the compile goes. */
1237 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1238 next_binding_table_offset
++;
1240 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1242 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1246 setup_vec4_uniform_value(const gl_constant_value
**params
,
1247 const gl_constant_value
*values
,
1250 static const gl_constant_value zero
= { 0 };
1252 for (unsigned i
= 0; i
< n
; ++i
)
1253 params
[i
] = &values
[i
];
1255 for (unsigned i
= n
; i
< 4; ++i
)
1260 brw_setup_image_uniform_values(gl_shader_stage stage
,
1261 struct brw_stage_prog_data
*stage_prog_data
,
1262 unsigned param_start_index
,
1263 const gl_uniform_storage
*storage
)
1265 const gl_constant_value
**param
=
1266 &stage_prog_data
->param
[param_start_index
];
1268 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1269 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1270 const brw_image_param
*image_param
=
1271 &stage_prog_data
->image_param
[image_idx
];
1273 /* Upload the brw_image_param structure. The order is expected to match
1274 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1276 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1277 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1278 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1279 (const gl_constant_value
*)image_param
->offset
, 2);
1280 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1281 (const gl_constant_value
*)image_param
->size
, 3);
1282 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1283 (const gl_constant_value
*)image_param
->stride
, 4);
1284 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1285 (const gl_constant_value
*)image_param
->tiling
, 3);
1286 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1287 (const gl_constant_value
*)image_param
->swizzling
, 2);
1288 param
+= BRW_IMAGE_PARAM_SIZE
;
1290 brw_mark_surface_used(
1292 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1297 * Decide which set of clip planes should be used when clipping via
1298 * gl_Position or gl_ClipVertex.
1300 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1302 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1303 /* There is currently a GLSL vertex shader, so clip according to GLSL
1304 * rules, which means compare gl_ClipVertex (or gl_Position, if
1305 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1306 * that were stored in EyeUserPlane at the time the clip planes were
1309 return ctx
->Transform
.EyeUserPlane
;
1311 /* Either we are using fixed function or an ARB vertex program. In
1312 * either case the clip planes are going to be compared against
1313 * gl_Position (which is in clip coordinates) so we have to clip using
1314 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1317 return ctx
->Transform
._ClipUserPlane
;
1321 extern "C" const unsigned *
1322 brw_compile_tes(const struct brw_compiler
*compiler
,
1325 const struct brw_tes_prog_key
*key
,
1326 struct brw_tes_prog_data
*prog_data
,
1327 const nir_shader
*src_shader
,
1328 struct gl_shader_program
*shader_prog
,
1329 int shader_time_index
,
1330 unsigned *final_assembly_size
,
1333 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
1334 struct gl_shader
*shader
=
1335 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
1336 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1338 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1339 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
1340 nir
->info
.inputs_read
= key
->inputs_read
;
1341 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1342 nir
= brw_nir_lower_io(nir
, compiler
->devinfo
, is_scalar
);
1343 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
1345 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1346 nir
->info
.outputs_written
,
1347 nir
->info
.separate_shader
);
1349 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1351 assert(output_size_bytes
>= 1);
1352 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1354 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1358 /* URB entry sizes are stored as a multiple of 64 bytes. */
1359 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1361 struct brw_vue_map input_vue_map
;
1362 brw_compute_tess_vue_map(&input_vue_map
,
1363 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
1364 nir
->info
.patch_inputs_read
);
1366 bool need_patch_header
= nir
->info
.system_values_read
&
1367 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER
) |
1368 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER
));
1370 /* The TES will pull most inputs using URB read messages.
1372 * However, we push the patch header for TessLevel factors when required,
1373 * as it's a tiny amount of extra data.
1375 prog_data
->base
.urb_read_length
= need_patch_header
? 1 : 0;
1377 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1378 fprintf(stderr
, "TES Input ");
1379 brw_print_vue_map(stderr
, &input_vue_map
);
1380 fprintf(stderr
, "TES Output ");
1381 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1385 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1386 &prog_data
->base
.base
, shader
->Program
, nir
, 8,
1387 shader_time_index
, &input_vue_map
);
1390 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1394 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1396 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1397 &prog_data
->base
.base
, v
.promoted_constants
, false,
1399 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1400 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1401 "%s tessellation evaluation shader %s",
1402 nir
->info
.label
? nir
->info
.label
1407 g
.generate_code(v
.cfg
, 8);
1409 return g
.get_assembly(final_assembly_size
);
1411 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1412 nir
, mem_ctx
, shader_time_index
);
1415 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1419 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1420 v
.dump_instructions();
1422 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1423 &prog_data
->base
, v
.cfg
,
1424 final_assembly_size
);