2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
29 #include "brw_vec4_tes.h"
30 #include "glsl/glsl_parser_extras.h"
31 #include "main/shaderobj.h"
32 #include "main/uniforms.h"
33 #include "util/debug.h"
36 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
38 struct brw_context
*brw
= (struct brw_context
*)data
;
43 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
44 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
45 MESA_DEBUG_TYPE_OTHER
,
46 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
51 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
53 struct brw_context
*brw
= (struct brw_context
*)data
;
58 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
60 va_copy(args_copy
, args
);
61 vfprintf(stderr
, fmt
, args_copy
);
65 if (brw
->perf_debug
) {
67 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
68 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
69 MESA_DEBUG_TYPE_PERFORMANCE
,
70 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
76 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
78 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
80 compiler
->devinfo
= devinfo
;
81 compiler
->shader_debug_log
= shader_debug_log_mesa
;
82 compiler
->shader_perf_log
= shader_perf_log_mesa
;
84 brw_fs_alloc_reg_sets(compiler
);
85 brw_vec4_alloc_reg_set(compiler
);
87 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
88 devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
);
89 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
] = false;
90 compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
] =
91 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
92 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
93 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
94 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
95 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
97 nir_shader_compiler_options
*nir_options
=
98 rzalloc(compiler
, nir_shader_compiler_options
);
99 nir_options
->native_integers
= true;
100 nir_options
->lower_fdiv
= true;
101 /* In order to help allow for better CSE at the NIR level we tell NIR
102 * to split all ffma instructions during opt_algebraic and we then
103 * re-combine them as a later step.
105 nir_options
->lower_ffma
= true;
106 nir_options
->lower_sub
= true;
107 /* In the vec4 backend, our dpN instruction replicates its result to all
108 * the components of a vec4. We would like NIR to give us replicated fdot
109 * instructions because it can optimize better for us.
111 * For the FS backend, it should be lowered away by the scalarizing pass so
112 * we should never see fdot anyway.
114 nir_options
->fdot_replicates
= true;
116 /* We want the GLSL compiler to emit code that uses condition codes */
117 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
118 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
119 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
120 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
122 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
123 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
124 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
125 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
126 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
127 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
129 bool is_scalar
= compiler
->scalar_stage
[i
];
131 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
132 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
133 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
135 /* !ARB_gpu_shader5 */
136 if (devinfo
->gen
< 7)
137 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
139 compiler
->glsl_compiler_options
[i
].NirOptions
= nir_options
;
141 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
144 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectInput
= false;
145 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_EVAL
].EmitNoIndirectInput
= false;
147 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
148 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
150 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
]
151 .LowerShaderSharedVariables
= true;
156 extern "C" struct gl_shader
*
157 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
159 struct brw_shader
*shader
;
161 shader
= rzalloc(NULL
, struct brw_shader
);
163 shader
->base
.Type
= type
;
164 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
165 shader
->base
.Name
= name
;
166 _mesa_init_shader(ctx
, &shader
->base
);
169 return &shader
->base
;
173 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
176 assert(surf_index
< BRW_MAX_SURFACES
);
178 prog_data
->binding_table
.size_bytes
=
179 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
183 brw_type_for_base_type(const struct glsl_type
*type
)
185 switch (type
->base_type
) {
186 case GLSL_TYPE_FLOAT
:
187 return BRW_REGISTER_TYPE_F
;
190 case GLSL_TYPE_SUBROUTINE
:
191 return BRW_REGISTER_TYPE_D
;
193 return BRW_REGISTER_TYPE_UD
;
194 case GLSL_TYPE_ARRAY
:
195 return brw_type_for_base_type(type
->fields
.array
);
196 case GLSL_TYPE_STRUCT
:
197 case GLSL_TYPE_SAMPLER
:
198 case GLSL_TYPE_ATOMIC_UINT
:
199 /* These should be overridden with the type of the member when
200 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
201 * way to trip up if we don't.
203 return BRW_REGISTER_TYPE_UD
;
204 case GLSL_TYPE_IMAGE
:
205 return BRW_REGISTER_TYPE_UD
;
207 case GLSL_TYPE_ERROR
:
208 case GLSL_TYPE_INTERFACE
:
209 case GLSL_TYPE_DOUBLE
:
210 unreachable("not reached");
213 return BRW_REGISTER_TYPE_F
;
216 enum brw_conditional_mod
217 brw_conditional_for_comparison(unsigned int op
)
221 return BRW_CONDITIONAL_L
;
222 case ir_binop_greater
:
223 return BRW_CONDITIONAL_G
;
224 case ir_binop_lequal
:
225 return BRW_CONDITIONAL_LE
;
226 case ir_binop_gequal
:
227 return BRW_CONDITIONAL_GE
;
229 case ir_binop_all_equal
: /* same as equal for scalars */
230 return BRW_CONDITIONAL_Z
;
231 case ir_binop_nequal
:
232 case ir_binop_any_nequal
: /* same as nequal for scalars */
233 return BRW_CONDITIONAL_NZ
;
235 unreachable("not reached: bad operation for comparison");
240 brw_math_function(enum opcode op
)
243 case SHADER_OPCODE_RCP
:
244 return BRW_MATH_FUNCTION_INV
;
245 case SHADER_OPCODE_RSQ
:
246 return BRW_MATH_FUNCTION_RSQ
;
247 case SHADER_OPCODE_SQRT
:
248 return BRW_MATH_FUNCTION_SQRT
;
249 case SHADER_OPCODE_EXP2
:
250 return BRW_MATH_FUNCTION_EXP
;
251 case SHADER_OPCODE_LOG2
:
252 return BRW_MATH_FUNCTION_LOG
;
253 case SHADER_OPCODE_POW
:
254 return BRW_MATH_FUNCTION_POW
;
255 case SHADER_OPCODE_SIN
:
256 return BRW_MATH_FUNCTION_SIN
;
257 case SHADER_OPCODE_COS
:
258 return BRW_MATH_FUNCTION_COS
;
259 case SHADER_OPCODE_INT_QUOTIENT
:
260 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
261 case SHADER_OPCODE_INT_REMAINDER
:
262 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
264 unreachable("not reached: unknown math function");
269 brw_texture_offset(int *offsets
, unsigned num_components
)
271 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
273 /* Combine all three offsets into a single unsigned dword:
275 * bits 11:8 - U Offset (X component)
276 * bits 7:4 - V Offset (Y component)
277 * bits 3:0 - R Offset (Z component)
279 unsigned offset_bits
= 0;
280 for (unsigned i
= 0; i
< num_components
; i
++) {
281 const unsigned shift
= 4 * (2 - i
);
282 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
288 brw_instruction_name(enum opcode op
)
291 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
292 assert(opcode_descs
[op
].name
);
293 return opcode_descs
[op
].name
;
294 case FS_OPCODE_FB_WRITE
:
296 case FS_OPCODE_FB_WRITE_LOGICAL
:
297 return "fb_write_logical";
298 case FS_OPCODE_PACK_STENCIL_REF
:
299 return "pack_stencil_ref";
300 case FS_OPCODE_BLORP_FB_WRITE
:
301 return "blorp_fb_write";
302 case FS_OPCODE_REP_FB_WRITE
:
303 return "rep_fb_write";
305 case SHADER_OPCODE_RCP
:
307 case SHADER_OPCODE_RSQ
:
309 case SHADER_OPCODE_SQRT
:
311 case SHADER_OPCODE_EXP2
:
313 case SHADER_OPCODE_LOG2
:
315 case SHADER_OPCODE_POW
:
317 case SHADER_OPCODE_INT_QUOTIENT
:
319 case SHADER_OPCODE_INT_REMAINDER
:
321 case SHADER_OPCODE_SIN
:
323 case SHADER_OPCODE_COS
:
326 case SHADER_OPCODE_TEX
:
328 case SHADER_OPCODE_TEX_LOGICAL
:
329 return "tex_logical";
330 case SHADER_OPCODE_TXD
:
332 case SHADER_OPCODE_TXD_LOGICAL
:
333 return "txd_logical";
334 case SHADER_OPCODE_TXF
:
336 case SHADER_OPCODE_TXF_LOGICAL
:
337 return "txf_logical";
338 case SHADER_OPCODE_TXL
:
340 case SHADER_OPCODE_TXL_LOGICAL
:
341 return "txl_logical";
342 case SHADER_OPCODE_TXS
:
344 case SHADER_OPCODE_TXS_LOGICAL
:
345 return "txs_logical";
348 case FS_OPCODE_TXB_LOGICAL
:
349 return "txb_logical";
350 case SHADER_OPCODE_TXF_CMS
:
352 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
353 return "txf_cms_logical";
354 case SHADER_OPCODE_TXF_CMS_W
:
356 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
357 return "txf_cms_w_logical";
358 case SHADER_OPCODE_TXF_UMS
:
360 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
361 return "txf_ums_logical";
362 case SHADER_OPCODE_TXF_MCS
:
364 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
365 return "txf_mcs_logical";
366 case SHADER_OPCODE_LOD
:
368 case SHADER_OPCODE_LOD_LOGICAL
:
369 return "lod_logical";
370 case SHADER_OPCODE_TG4
:
372 case SHADER_OPCODE_TG4_LOGICAL
:
373 return "tg4_logical";
374 case SHADER_OPCODE_TG4_OFFSET
:
376 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
377 return "tg4_offset_logical";
378 case SHADER_OPCODE_SAMPLEINFO
:
381 case SHADER_OPCODE_SHADER_TIME_ADD
:
382 return "shader_time_add";
384 case SHADER_OPCODE_UNTYPED_ATOMIC
:
385 return "untyped_atomic";
386 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
387 return "untyped_atomic_logical";
388 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
389 return "untyped_surface_read";
390 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
391 return "untyped_surface_read_logical";
392 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
393 return "untyped_surface_write";
394 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
395 return "untyped_surface_write_logical";
396 case SHADER_OPCODE_TYPED_ATOMIC
:
397 return "typed_atomic";
398 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
399 return "typed_atomic_logical";
400 case SHADER_OPCODE_TYPED_SURFACE_READ
:
401 return "typed_surface_read";
402 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
403 return "typed_surface_read_logical";
404 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
405 return "typed_surface_write";
406 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
407 return "typed_surface_write_logical";
408 case SHADER_OPCODE_MEMORY_FENCE
:
409 return "memory_fence";
411 case SHADER_OPCODE_LOAD_PAYLOAD
:
412 return "load_payload";
414 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
415 return "gen4_scratch_read";
416 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
417 return "gen4_scratch_write";
418 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
419 return "gen7_scratch_read";
420 case SHADER_OPCODE_URB_WRITE_SIMD8
:
421 return "gen8_urb_write_simd8";
422 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
423 return "gen8_urb_write_simd8_per_slot";
424 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
425 return "gen8_urb_write_simd8_masked";
426 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
427 return "gen8_urb_write_simd8_masked_per_slot";
428 case SHADER_OPCODE_URB_READ_SIMD8
:
429 return "urb_read_simd8";
430 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
431 return "urb_read_simd8_per_slot";
433 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
434 return "find_live_channel";
435 case SHADER_OPCODE_BROADCAST
:
438 case VEC4_OPCODE_MOV_BYTES
:
440 case VEC4_OPCODE_PACK_BYTES
:
442 case VEC4_OPCODE_UNPACK_UNIFORM
:
443 return "unpack_uniform";
445 case FS_OPCODE_DDX_COARSE
:
447 case FS_OPCODE_DDX_FINE
:
449 case FS_OPCODE_DDY_COARSE
:
451 case FS_OPCODE_DDY_FINE
:
454 case FS_OPCODE_CINTERP
:
456 case FS_OPCODE_LINTERP
:
459 case FS_OPCODE_PIXEL_X
:
461 case FS_OPCODE_PIXEL_Y
:
464 case FS_OPCODE_GET_BUFFER_SIZE
:
465 return "fs_get_buffer_size";
467 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
468 return "uniform_pull_const";
469 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
470 return "uniform_pull_const_gen7";
471 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
472 return "varying_pull_const";
473 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
474 return "varying_pull_const_gen7";
476 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
477 return "mov_dispatch_to_flags";
478 case FS_OPCODE_DISCARD_JUMP
:
479 return "discard_jump";
481 case FS_OPCODE_SET_SAMPLE_ID
:
482 return "set_sample_id";
483 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
484 return "set_simd4x2_offset";
486 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
487 return "pack_half_2x16_split";
488 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
489 return "unpack_half_2x16_split_x";
490 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
491 return "unpack_half_2x16_split_y";
493 case FS_OPCODE_PLACEHOLDER_HALT
:
494 return "placeholder_halt";
496 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
497 return "interp_centroid";
498 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
499 return "interp_sample";
500 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
501 return "interp_shared_offset";
502 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
503 return "interp_per_slot_offset";
505 case VS_OPCODE_URB_WRITE
:
506 return "vs_urb_write";
507 case VS_OPCODE_PULL_CONSTANT_LOAD
:
508 return "pull_constant_load";
509 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
510 return "pull_constant_load_gen7";
512 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
513 return "set_simd4x2_header_gen9";
515 case VS_OPCODE_GET_BUFFER_SIZE
:
516 return "vs_get_buffer_size";
518 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
519 return "unpack_flags_simd4x2";
521 case GS_OPCODE_URB_WRITE
:
522 return "gs_urb_write";
523 case GS_OPCODE_URB_WRITE_ALLOCATE
:
524 return "gs_urb_write_allocate";
525 case GS_OPCODE_THREAD_END
:
526 return "gs_thread_end";
527 case GS_OPCODE_SET_WRITE_OFFSET
:
528 return "set_write_offset";
529 case GS_OPCODE_SET_VERTEX_COUNT
:
530 return "set_vertex_count";
531 case GS_OPCODE_SET_DWORD_2
:
532 return "set_dword_2";
533 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
534 return "prepare_channel_masks";
535 case GS_OPCODE_SET_CHANNEL_MASKS
:
536 return "set_channel_masks";
537 case GS_OPCODE_GET_INSTANCE_ID
:
538 return "get_instance_id";
539 case GS_OPCODE_FF_SYNC
:
541 case GS_OPCODE_SET_PRIMITIVE_ID
:
542 return "set_primitive_id";
543 case GS_OPCODE_SVB_WRITE
:
544 return "gs_svb_write";
545 case GS_OPCODE_SVB_SET_DST_INDEX
:
546 return "gs_svb_set_dst_index";
547 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
548 return "gs_ff_sync_set_primitives";
549 case CS_OPCODE_CS_TERMINATE
:
550 return "cs_terminate";
551 case SHADER_OPCODE_BARRIER
:
553 case SHADER_OPCODE_MULH
:
555 case SHADER_OPCODE_MOV_INDIRECT
:
556 return "mov_indirect";
558 case VEC4_OPCODE_URB_READ
:
560 case TCS_OPCODE_GET_INSTANCE_ID
:
561 return "tcs_get_instance_id";
562 case TCS_OPCODE_URB_WRITE
:
563 return "tcs_urb_write";
564 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
565 return "tcs_set_input_urb_offsets";
566 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
567 return "tcs_set_output_urb_offsets";
568 case TCS_OPCODE_GET_PRIMITIVE_ID
:
569 return "tcs_get_primitive_id";
570 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
571 return "tcs_create_barrier_header";
572 case TCS_OPCODE_SRC0_010_IS_ZERO
:
573 return "tcs_src0<0,1,0>_is_zero";
574 case TCS_OPCODE_RELEASE_INPUT
:
575 return "tcs_release_input";
576 case TCS_OPCODE_THREAD_END
:
577 return "tcs_thread_end";
578 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
579 return "tes_create_input_read_header";
580 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
581 return "tes_add_indirect_urb_offset";
582 case TES_OPCODE_GET_PRIMITIVE_ID
:
583 return "tes_get_primitive_id";
586 unreachable("not reached");
590 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
596 } imm
= { reg
->ud
}, sat_imm
= { 0 };
599 case BRW_REGISTER_TYPE_UD
:
600 case BRW_REGISTER_TYPE_D
:
601 case BRW_REGISTER_TYPE_UW
:
602 case BRW_REGISTER_TYPE_W
:
603 case BRW_REGISTER_TYPE_UQ
:
604 case BRW_REGISTER_TYPE_Q
:
607 case BRW_REGISTER_TYPE_F
:
608 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
610 case BRW_REGISTER_TYPE_UB
:
611 case BRW_REGISTER_TYPE_B
:
612 unreachable("no UB/B immediates");
613 case BRW_REGISTER_TYPE_V
:
614 case BRW_REGISTER_TYPE_UV
:
615 case BRW_REGISTER_TYPE_VF
:
616 unreachable("unimplemented: saturate vector immediate");
617 case BRW_REGISTER_TYPE_DF
:
618 case BRW_REGISTER_TYPE_HF
:
619 unreachable("unimplemented: saturate DF/HF immediate");
622 if (imm
.ud
!= sat_imm
.ud
) {
623 reg
->ud
= sat_imm
.ud
;
630 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
633 case BRW_REGISTER_TYPE_D
:
634 case BRW_REGISTER_TYPE_UD
:
637 case BRW_REGISTER_TYPE_W
:
638 case BRW_REGISTER_TYPE_UW
:
639 reg
->d
= -(int16_t)reg
->ud
;
641 case BRW_REGISTER_TYPE_F
:
644 case BRW_REGISTER_TYPE_VF
:
645 reg
->ud
^= 0x80808080;
647 case BRW_REGISTER_TYPE_UB
:
648 case BRW_REGISTER_TYPE_B
:
649 unreachable("no UB/B immediates");
650 case BRW_REGISTER_TYPE_UV
:
651 case BRW_REGISTER_TYPE_V
:
652 assert(!"unimplemented: negate UV/V immediate");
653 case BRW_REGISTER_TYPE_UQ
:
654 case BRW_REGISTER_TYPE_Q
:
655 assert(!"unimplemented: negate UQ/Q immediate");
656 case BRW_REGISTER_TYPE_DF
:
657 case BRW_REGISTER_TYPE_HF
:
658 assert(!"unimplemented: negate DF/HF immediate");
665 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
668 case BRW_REGISTER_TYPE_D
:
669 reg
->d
= abs(reg
->d
);
671 case BRW_REGISTER_TYPE_W
:
672 reg
->d
= abs((int16_t)reg
->ud
);
674 case BRW_REGISTER_TYPE_F
:
675 reg
->f
= fabsf(reg
->f
);
677 case BRW_REGISTER_TYPE_VF
:
678 reg
->ud
&= ~0x80808080;
680 case BRW_REGISTER_TYPE_UB
:
681 case BRW_REGISTER_TYPE_B
:
682 unreachable("no UB/B immediates");
683 case BRW_REGISTER_TYPE_UQ
:
684 case BRW_REGISTER_TYPE_UD
:
685 case BRW_REGISTER_TYPE_UW
:
686 case BRW_REGISTER_TYPE_UV
:
687 /* Presumably the absolute value modifier on an unsigned source is a
688 * nop, but it would be nice to confirm.
690 assert(!"unimplemented: abs unsigned immediate");
691 case BRW_REGISTER_TYPE_V
:
692 assert(!"unimplemented: abs V immediate");
693 case BRW_REGISTER_TYPE_Q
:
694 assert(!"unimplemented: abs Q immediate");
695 case BRW_REGISTER_TYPE_DF
:
696 case BRW_REGISTER_TYPE_HF
:
697 assert(!"unimplemented: abs DF/HF immediate");
703 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
706 const nir_shader
*shader
,
707 struct brw_stage_prog_data
*stage_prog_data
)
708 : compiler(compiler
),
710 devinfo(compiler
->devinfo
),
712 stage_prog_data(stage_prog_data
),
717 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
718 stage_name
= _mesa_shader_stage_to_string(stage
);
719 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
723 backend_reg::equals(const backend_reg
&r
) const
725 return memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
726 reg_offset
== r
.reg_offset
;
730 backend_reg::is_zero() const
739 backend_reg::is_one() const
744 return type
== BRW_REGISTER_TYPE_F
750 backend_reg::is_negative_one() const
756 case BRW_REGISTER_TYPE_F
:
758 case BRW_REGISTER_TYPE_D
:
766 backend_reg::is_null() const
768 return file
== ARF
&& nr
== BRW_ARF_NULL
;
773 backend_reg::is_accumulator() const
775 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
779 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
781 return (file
== r
.file
&&
783 reg_offset
>= r
.reg_offset
&&
784 reg_offset
< r
.reg_offset
+ n
);
788 backend_instruction::is_commutative() const
796 case SHADER_OPCODE_MULH
:
799 /* MIN and MAX are commutative. */
800 if (conditional_mod
== BRW_CONDITIONAL_GE
||
801 conditional_mod
== BRW_CONDITIONAL_L
) {
811 backend_instruction::is_3src() const
813 return ::is_3src(opcode
);
817 backend_instruction::is_tex() const
819 return (opcode
== SHADER_OPCODE_TEX
||
820 opcode
== FS_OPCODE_TXB
||
821 opcode
== SHADER_OPCODE_TXD
||
822 opcode
== SHADER_OPCODE_TXF
||
823 opcode
== SHADER_OPCODE_TXF_CMS
||
824 opcode
== SHADER_OPCODE_TXF_CMS_W
||
825 opcode
== SHADER_OPCODE_TXF_UMS
||
826 opcode
== SHADER_OPCODE_TXF_MCS
||
827 opcode
== SHADER_OPCODE_TXL
||
828 opcode
== SHADER_OPCODE_TXS
||
829 opcode
== SHADER_OPCODE_LOD
||
830 opcode
== SHADER_OPCODE_TG4
||
831 opcode
== SHADER_OPCODE_TG4_OFFSET
);
835 backend_instruction::is_math() const
837 return (opcode
== SHADER_OPCODE_RCP
||
838 opcode
== SHADER_OPCODE_RSQ
||
839 opcode
== SHADER_OPCODE_SQRT
||
840 opcode
== SHADER_OPCODE_EXP2
||
841 opcode
== SHADER_OPCODE_LOG2
||
842 opcode
== SHADER_OPCODE_SIN
||
843 opcode
== SHADER_OPCODE_COS
||
844 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
845 opcode
== SHADER_OPCODE_INT_REMAINDER
||
846 opcode
== SHADER_OPCODE_POW
);
850 backend_instruction::is_control_flow() const
854 case BRW_OPCODE_WHILE
:
856 case BRW_OPCODE_ELSE
:
857 case BRW_OPCODE_ENDIF
:
858 case BRW_OPCODE_BREAK
:
859 case BRW_OPCODE_CONTINUE
:
867 backend_instruction::can_do_source_mods() const
870 case BRW_OPCODE_ADDC
:
872 case BRW_OPCODE_BFI1
:
873 case BRW_OPCODE_BFI2
:
874 case BRW_OPCODE_BFREV
:
875 case BRW_OPCODE_CBIT
:
878 case BRW_OPCODE_SUBB
:
886 backend_instruction::can_do_saturate() const
896 case BRW_OPCODE_F16TO32
:
897 case BRW_OPCODE_F32TO16
:
898 case BRW_OPCODE_LINE
:
902 case BRW_OPCODE_MATH
:
905 case SHADER_OPCODE_MULH
:
907 case BRW_OPCODE_RNDD
:
908 case BRW_OPCODE_RNDE
:
909 case BRW_OPCODE_RNDU
:
910 case BRW_OPCODE_RNDZ
:
914 case FS_OPCODE_LINTERP
:
915 case SHADER_OPCODE_COS
:
916 case SHADER_OPCODE_EXP2
:
917 case SHADER_OPCODE_LOG2
:
918 case SHADER_OPCODE_POW
:
919 case SHADER_OPCODE_RCP
:
920 case SHADER_OPCODE_RSQ
:
921 case SHADER_OPCODE_SIN
:
922 case SHADER_OPCODE_SQRT
:
930 backend_instruction::can_do_cmod() const
934 case BRW_OPCODE_ADDC
:
939 case BRW_OPCODE_CMPN
:
944 case BRW_OPCODE_F16TO32
:
945 case BRW_OPCODE_F32TO16
:
947 case BRW_OPCODE_LINE
:
951 case BRW_OPCODE_MACH
:
958 case BRW_OPCODE_RNDD
:
959 case BRW_OPCODE_RNDE
:
960 case BRW_OPCODE_RNDU
:
961 case BRW_OPCODE_RNDZ
:
962 case BRW_OPCODE_SAD2
:
963 case BRW_OPCODE_SADA2
:
966 case BRW_OPCODE_SUBB
:
968 case FS_OPCODE_CINTERP
:
969 case FS_OPCODE_LINTERP
:
977 backend_instruction::reads_accumulator_implicitly() const
981 case BRW_OPCODE_MACH
:
982 case BRW_OPCODE_SADA2
:
990 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
992 return writes_accumulator
||
994 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
995 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
996 opcode
!= FS_OPCODE_CINTERP
)));
1000 backend_instruction::has_side_effects() const
1003 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1004 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
1005 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1006 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1007 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1008 case SHADER_OPCODE_TYPED_ATOMIC
:
1009 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1010 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1011 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1012 case SHADER_OPCODE_MEMORY_FENCE
:
1013 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1014 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1015 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1016 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1017 case FS_OPCODE_FB_WRITE
:
1018 case SHADER_OPCODE_BARRIER
:
1019 case TCS_OPCODE_RELEASE_INPUT
:
1027 backend_instruction::is_volatile() const
1030 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1031 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1032 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1033 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1042 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1045 foreach_inst_in_block (backend_instruction
, i
, block
) {
1055 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1057 for (bblock_t
*block_iter
= start_block
->next();
1058 !block_iter
->link
.is_tail_sentinel();
1059 block_iter
= block_iter
->next()) {
1060 block_iter
->start_ip
+= ip_adjustment
;
1061 block_iter
->end_ip
+= ip_adjustment
;
1066 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1068 if (!this->is_head_sentinel())
1069 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1073 adjust_later_block_ips(block
, 1);
1075 exec_node::insert_after(inst
);
1079 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1081 if (!this->is_tail_sentinel())
1082 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1086 adjust_later_block_ips(block
, 1);
1088 exec_node::insert_before(inst
);
1092 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1094 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1096 unsigned num_inst
= list
->length();
1098 block
->end_ip
+= num_inst
;
1100 adjust_later_block_ips(block
, num_inst
);
1102 exec_node::insert_before(list
);
1106 backend_instruction::remove(bblock_t
*block
)
1108 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1110 adjust_later_block_ips(block
, -1);
1112 if (block
->start_ip
== block
->end_ip
) {
1113 block
->cfg
->remove_block(block
);
1118 exec_node::remove();
1122 backend_shader::dump_instructions()
1124 dump_instructions(NULL
);
1128 backend_shader::dump_instructions(const char *name
)
1130 FILE *file
= stderr
;
1131 if (name
&& geteuid() != 0) {
1132 file
= fopen(name
, "w");
1139 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1140 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1141 fprintf(file
, "%4d: ", ip
++);
1142 dump_instruction(inst
, file
);
1146 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1147 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1148 fprintf(file
, "%4d: ", ip
++);
1149 dump_instruction(inst
, file
);
1153 if (file
!= stderr
) {
1159 backend_shader::calculate_cfg()
1163 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1167 backend_shader::invalidate_cfg()
1169 ralloc_free(this->cfg
);
1174 * Sets up the starting offsets for the groups of binding table entries
1175 * commong to all pipeline stages.
1177 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1178 * unused but also make sure that addition of small offsets to them will
1179 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1182 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1183 const struct brw_device_info
*devinfo
,
1184 const struct gl_shader_program
*shader_prog
,
1185 const struct gl_program
*prog
,
1186 struct brw_stage_prog_data
*stage_prog_data
,
1187 uint32_t next_binding_table_offset
)
1189 const struct gl_shader
*shader
= NULL
;
1190 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1193 shader
= shader_prog
->_LinkedShaders
[stage
];
1195 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1196 next_binding_table_offset
+= num_textures
;
1199 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1200 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1201 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1203 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1204 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1205 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1207 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1208 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1211 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1212 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1213 next_binding_table_offset
++;
1215 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1218 if (prog
->UsesGather
) {
1219 if (devinfo
->gen
>= 8) {
1220 stage_prog_data
->binding_table
.gather_texture_start
=
1221 stage_prog_data
->binding_table
.texture_start
;
1223 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1224 next_binding_table_offset
+= num_textures
;
1227 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1230 if (shader
&& shader
->NumAtomicBuffers
) {
1231 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1232 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1234 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1237 if (shader
&& shader
->NumImages
) {
1238 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1239 next_binding_table_offset
+= shader
->NumImages
;
1241 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1244 /* This may or may not be used depending on how the compile goes. */
1245 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1246 next_binding_table_offset
++;
1248 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1250 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1254 setup_vec4_uniform_value(const gl_constant_value
**params
,
1255 const gl_constant_value
*values
,
1258 static const gl_constant_value zero
= { 0 };
1260 for (unsigned i
= 0; i
< n
; ++i
)
1261 params
[i
] = &values
[i
];
1263 for (unsigned i
= n
; i
< 4; ++i
)
1268 brw_setup_image_uniform_values(gl_shader_stage stage
,
1269 struct brw_stage_prog_data
*stage_prog_data
,
1270 unsigned param_start_index
,
1271 const gl_uniform_storage
*storage
)
1273 const gl_constant_value
**param
=
1274 &stage_prog_data
->param
[param_start_index
];
1276 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1277 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1278 const brw_image_param
*image_param
=
1279 &stage_prog_data
->image_param
[image_idx
];
1281 /* Upload the brw_image_param structure. The order is expected to match
1282 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1284 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1285 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1286 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1287 (const gl_constant_value
*)image_param
->offset
, 2);
1288 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1289 (const gl_constant_value
*)image_param
->size
, 3);
1290 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1291 (const gl_constant_value
*)image_param
->stride
, 4);
1292 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1293 (const gl_constant_value
*)image_param
->tiling
, 3);
1294 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1295 (const gl_constant_value
*)image_param
->swizzling
, 2);
1296 param
+= BRW_IMAGE_PARAM_SIZE
;
1298 brw_mark_surface_used(
1300 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1305 * Decide which set of clip planes should be used when clipping via
1306 * gl_Position or gl_ClipVertex.
1308 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1310 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1311 /* There is currently a GLSL vertex shader, so clip according to GLSL
1312 * rules, which means compare gl_ClipVertex (or gl_Position, if
1313 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1314 * that were stored in EyeUserPlane at the time the clip planes were
1317 return ctx
->Transform
.EyeUserPlane
;
1319 /* Either we are using fixed function or an ARB vertex program. In
1320 * either case the clip planes are going to be compared against
1321 * gl_Position (which is in clip coordinates) so we have to clip using
1322 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1325 return ctx
->Transform
._ClipUserPlane
;
1329 extern "C" const unsigned *
1330 brw_compile_tes(const struct brw_compiler
*compiler
,
1333 const struct brw_tes_prog_key
*key
,
1334 struct brw_tes_prog_data
*prog_data
,
1335 const nir_shader
*src_shader
,
1336 struct gl_shader_program
*shader_prog
,
1337 int shader_time_index
,
1338 unsigned *final_assembly_size
,
1341 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
1342 struct gl_shader
*shader
=
1343 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
1344 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1346 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1347 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
1348 nir
->info
.inputs_read
= key
->inputs_read
;
1349 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1350 nir
= brw_nir_lower_io(nir
, compiler
->devinfo
, is_scalar
);
1351 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
1353 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1354 nir
->info
.outputs_written
,
1355 nir
->info
.separate_shader
);
1357 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1359 assert(output_size_bytes
>= 1);
1360 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1362 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1366 /* URB entry sizes are stored as a multiple of 64 bytes. */
1367 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1369 struct brw_vue_map input_vue_map
;
1370 brw_compute_tess_vue_map(&input_vue_map
,
1371 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
1372 nir
->info
.patch_inputs_read
);
1374 bool need_patch_header
= nir
->info
.system_values_read
&
1375 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER
) |
1376 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER
));
1378 /* The TES will pull most inputs using URB read messages.
1380 * However, we push the patch header for TessLevel factors when required,
1381 * as it's a tiny amount of extra data.
1383 prog_data
->base
.urb_read_length
= need_patch_header
? 1 : 0;
1385 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1386 fprintf(stderr
, "TES Input ");
1387 brw_print_vue_map(stderr
, &input_vue_map
);
1388 fprintf(stderr
, "TES Output ");
1389 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1393 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1394 &prog_data
->base
.base
, shader
->Program
, nir
, 8,
1395 shader_time_index
, &input_vue_map
);
1398 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1402 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1404 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1405 &prog_data
->base
.base
, v
.promoted_constants
, false,
1407 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1408 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1409 "%s tessellation evaluation shader %s",
1410 nir
->info
.label
? nir
->info
.label
1415 g
.generate_code(v
.cfg
, 8);
1417 return g
.get_assembly(final_assembly_size
);
1419 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1420 nir
, mem_ctx
, shader_time_index
);
1423 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1427 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1428 v
.dump_instructions();
1430 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1431 &prog_data
->base
, v
.cfg
,
1432 final_assembly_size
);