src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32
  33 extern "C" struct gl_shader *
  34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  35 {
  36    struct brw_shader *shader;
  37
  38    shader = rzalloc(NULL, struct brw_shader);
  39    if (shader) {
  40       shader->base.Type = type;
  41       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  42       shader->base.Name = name;
  43       _mesa_init_shader(ctx, &shader->base);
  44    }
  45
  46    return &shader->base;
  47 }
  48
  49 extern "C" void
  50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  51                       unsigned surf_index)
  52 {
  53    assert(surf_index < BRW_MAX_SURFACES);
  54
  55    prog_data->binding_table.size_bytes =
  56       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  57 }
  58
  59 enum brw_reg_type
  60 brw_type_for_base_type(const struct glsl_type *type)
  61 {
  62    switch (type->base_type) {
  63    case GLSL_TYPE_FLOAT:
  64       return BRW_REGISTER_TYPE_F;
  65    case GLSL_TYPE_INT:
  66    case GLSL_TYPE_BOOL:
  67    case GLSL_TYPE_SUBROUTINE:
  68       return BRW_REGISTER_TYPE_D;
  69    case GLSL_TYPE_UINT:
  70       return BRW_REGISTER_TYPE_UD;
  71    case GLSL_TYPE_ARRAY:
  72       return brw_type_for_base_type(type->fields.array);
  73    case GLSL_TYPE_STRUCT:
  74    case GLSL_TYPE_SAMPLER:
  75    case GLSL_TYPE_ATOMIC_UINT:
  76       /* These should be overridden with the type of the member when
  77        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  78        * way to trip up if we don't.
  79        */
  80       return BRW_REGISTER_TYPE_UD;
  81    case GLSL_TYPE_IMAGE:
  82       return BRW_REGISTER_TYPE_UD;
  83    case GLSL_TYPE_DOUBLE:
  84       return BRW_REGISTER_TYPE_DF;
  85    case GLSL_TYPE_VOID:
  86    case GLSL_TYPE_ERROR:
  87    case GLSL_TYPE_INTERFACE:
  88    case GLSL_TYPE_FUNCTION:
  89       unreachable("not reached");
  90    }
  91
  92    return BRW_REGISTER_TYPE_F;
  93 }
  94
  95 enum brw_conditional_mod
  96 brw_conditional_for_comparison(unsigned int op)
  97 {
  98    switch (op) {
  99    case ir_binop_less:
 100       return BRW_CONDITIONAL_L;
 101    case ir_binop_greater:
 102       return BRW_CONDITIONAL_G;
 103    case ir_binop_lequal:
 104       return BRW_CONDITIONAL_LE;
 105    case ir_binop_gequal:
 106       return BRW_CONDITIONAL_GE;
 107    case ir_binop_equal:
 108    case ir_binop_all_equal: /* same as equal for scalars */
 109       return BRW_CONDITIONAL_Z;
 110    case ir_binop_nequal:
 111    case ir_binop_any_nequal: /* same as nequal for scalars */
 112       return BRW_CONDITIONAL_NZ;
 113    default:
 114       unreachable("not reached: bad operation for comparison");
 115    }
 116 }
 117
 118 uint32_t
 119 brw_math_function(enum opcode op)
 120 {
 121    switch (op) {
 122    case SHADER_OPCODE_RCP:
 123       return BRW_MATH_FUNCTION_INV;
 124    case SHADER_OPCODE_RSQ:
 125       return BRW_MATH_FUNCTION_RSQ;
 126    case SHADER_OPCODE_SQRT:
 127       return BRW_MATH_FUNCTION_SQRT;
 128    case SHADER_OPCODE_EXP2:
 129       return BRW_MATH_FUNCTION_EXP;
 130    case SHADER_OPCODE_LOG2:
 131       return BRW_MATH_FUNCTION_LOG;
 132    case SHADER_OPCODE_POW:
 133       return BRW_MATH_FUNCTION_POW;
 134    case SHADER_OPCODE_SIN:
 135       return BRW_MATH_FUNCTION_SIN;
 136    case SHADER_OPCODE_COS:
 137       return BRW_MATH_FUNCTION_COS;
 138    case SHADER_OPCODE_INT_QUOTIENT:
 139       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 140    case SHADER_OPCODE_INT_REMAINDER:
 141       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 142    default:
 143       unreachable("not reached: unknown math function");
 144    }
 145 }
 146
 147 uint32_t
 148 brw_texture_offset(int *offsets, unsigned num_components)
 149 {
 150    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 151
 152    /* Combine all three offsets into a single unsigned dword:
 153     *
 154     *    bits 11:8 - U Offset (X component)
 155     *    bits  7:4 - V Offset (Y component)
 156     *    bits  3:0 - R Offset (Z component)
 157     */
 158    unsigned offset_bits = 0;
 159    for (unsigned i = 0; i < num_components; i++) {
 160       const unsigned shift = 4 * (2 - i);
 161       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 162    }
 163    return offset_bits;
 164 }
 165
 166 const char *
 167 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
 168 {
 169    switch (op) {
 170    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 171       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 172        * start of a loop in the IR.
 173        */
 174       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 175          return "do";
 176
 177       assert(brw_opcode_desc(devinfo, op)->name);
 178       return brw_opcode_desc(devinfo, op)->name;
 179    case FS_OPCODE_FB_WRITE:
 180       return "fb_write";
 181    case FS_OPCODE_FB_WRITE_LOGICAL:
 182       return "fb_write_logical";
 183    case FS_OPCODE_PACK_STENCIL_REF:
 184       return "pack_stencil_ref";
 185    case FS_OPCODE_REP_FB_WRITE:
 186       return "rep_fb_write";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_TEX:
 210       return "tex";
 211    case SHADER_OPCODE_TEX_LOGICAL:
 212       return "tex_logical";
 213    case SHADER_OPCODE_TXD:
 214       return "txd";
 215    case SHADER_OPCODE_TXD_LOGICAL:
 216       return "txd_logical";
 217    case SHADER_OPCODE_TXF:
 218       return "txf";
 219    case SHADER_OPCODE_TXF_LOGICAL:
 220       return "txf_logical";
 221    case SHADER_OPCODE_TXL:
 222       return "txl";
 223    case SHADER_OPCODE_TXL_LOGICAL:
 224       return "txl_logical";
 225    case SHADER_OPCODE_TXS:
 226       return "txs";
 227    case SHADER_OPCODE_TXS_LOGICAL:
 228       return "txs_logical";
 229    case FS_OPCODE_TXB:
 230       return "txb";
 231    case FS_OPCODE_TXB_LOGICAL:
 232       return "txb_logical";
 233    case SHADER_OPCODE_TXF_CMS:
 234       return "txf_cms";
 235    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 236       return "txf_cms_logical";
 237    case SHADER_OPCODE_TXF_CMS_W:
 238       return "txf_cms_w";
 239    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 240       return "txf_cms_w_logical";
 241    case SHADER_OPCODE_TXF_UMS:
 242       return "txf_ums";
 243    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 244       return "txf_ums_logical";
 245    case SHADER_OPCODE_TXF_MCS:
 246       return "txf_mcs";
 247    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 248       return "txf_mcs_logical";
 249    case SHADER_OPCODE_LOD:
 250       return "lod";
 251    case SHADER_OPCODE_LOD_LOGICAL:
 252       return "lod_logical";
 253    case SHADER_OPCODE_TG4:
 254       return "tg4";
 255    case SHADER_OPCODE_TG4_LOGICAL:
 256       return "tg4_logical";
 257    case SHADER_OPCODE_TG4_OFFSET:
 258       return "tg4_offset";
 259    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 260       return "tg4_offset_logical";
 261    case SHADER_OPCODE_SAMPLEINFO:
 262       return "sampleinfo";
 263
 264    case SHADER_OPCODE_SHADER_TIME_ADD:
 265       return "shader_time_add";
 266
 267    case SHADER_OPCODE_UNTYPED_ATOMIC:
 268       return "untyped_atomic";
 269    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 270       return "untyped_atomic_logical";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 272       return "untyped_surface_read";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 274       return "untyped_surface_read_logical";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 276       return "untyped_surface_write";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 278       return "untyped_surface_write_logical";
 279    case SHADER_OPCODE_TYPED_ATOMIC:
 280       return "typed_atomic";
 281    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 282       return "typed_atomic_logical";
 283    case SHADER_OPCODE_TYPED_SURFACE_READ:
 284       return "typed_surface_read";
 285    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 286       return "typed_surface_read_logical";
 287    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 288       return "typed_surface_write";
 289    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 290       return "typed_surface_write_logical";
 291    case SHADER_OPCODE_MEMORY_FENCE:
 292       return "memory_fence";
 293
 294    case SHADER_OPCODE_LOAD_PAYLOAD:
 295       return "load_payload";
 296    case FS_OPCODE_PACK:
 297       return "pack";
 298
 299    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 300       return "gen4_scratch_read";
 301    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 302       return "gen4_scratch_write";
 303    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 304       return "gen7_scratch_read";
 305    case SHADER_OPCODE_URB_WRITE_SIMD8:
 306       return "gen8_urb_write_simd8";
 307    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 308       return "gen8_urb_write_simd8_per_slot";
 309    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 310       return "gen8_urb_write_simd8_masked";
 311    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 312       return "gen8_urb_write_simd8_masked_per_slot";
 313    case SHADER_OPCODE_URB_READ_SIMD8:
 314       return "urb_read_simd8";
 315    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 316       return "urb_read_simd8_per_slot";
 317
 318    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 319       return "find_live_channel";
 320    case SHADER_OPCODE_BROADCAST:
 321       return "broadcast";
 322
 323    case SHADER_OPCODE_EXTRACT_BYTE:
 324       return "extract_byte";
 325    case SHADER_OPCODE_EXTRACT_WORD:
 326       return "extract_word";
 327    case VEC4_OPCODE_MOV_BYTES:
 328       return "mov_bytes";
 329    case VEC4_OPCODE_PACK_BYTES:
 330       return "pack_bytes";
 331    case VEC4_OPCODE_UNPACK_UNIFORM:
 332       return "unpack_uniform";
 333
 334    case FS_OPCODE_DDX_COARSE:
 335       return "ddx_coarse";
 336    case FS_OPCODE_DDX_FINE:
 337       return "ddx_fine";
 338    case FS_OPCODE_DDY_COARSE:
 339       return "ddy_coarse";
 340    case FS_OPCODE_DDY_FINE:
 341       return "ddy_fine";
 342
 343    case FS_OPCODE_CINTERP:
 344       return "cinterp";
 345    case FS_OPCODE_LINTERP:
 346       return "linterp";
 347
 348    case FS_OPCODE_PIXEL_X:
 349       return "pixel_x";
 350    case FS_OPCODE_PIXEL_Y:
 351       return "pixel_y";
 352
 353    case FS_OPCODE_GET_BUFFER_SIZE:
 354       return "fs_get_buffer_size";
 355
 356    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 357       return "uniform_pull_const";
 358    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 359       return "uniform_pull_const_gen7";
 360    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 361       return "varying_pull_const";
 362    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 363       return "varying_pull_const_gen7";
 364
 365    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 366       return "mov_dispatch_to_flags";
 367    case FS_OPCODE_DISCARD_JUMP:
 368       return "discard_jump";
 369
 370    case FS_OPCODE_SET_SAMPLE_ID:
 371       return "set_sample_id";
 372    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 373       return "set_simd4x2_offset";
 374
 375    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 376       return "pack_half_2x16_split";
 377    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 378       return "unpack_half_2x16_split_x";
 379    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 380       return "unpack_half_2x16_split_y";
 381
 382    case FS_OPCODE_PLACEHOLDER_HALT:
 383       return "placeholder_halt";
 384
 385    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 386       return "interp_centroid";
 387    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 388       return "interp_sample";
 389    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 390       return "interp_shared_offset";
 391    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 392       return "interp_per_slot_offset";
 393
 394    case VS_OPCODE_URB_WRITE:
 395       return "vs_urb_write";
 396    case VS_OPCODE_PULL_CONSTANT_LOAD:
 397       return "pull_constant_load";
 398    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 399       return "pull_constant_load_gen7";
 400
 401    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 402       return "set_simd4x2_header_gen9";
 403
 404    case VS_OPCODE_GET_BUFFER_SIZE:
 405       return "vs_get_buffer_size";
 406
 407    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 408       return "unpack_flags_simd4x2";
 409
 410    case GS_OPCODE_URB_WRITE:
 411       return "gs_urb_write";
 412    case GS_OPCODE_URB_WRITE_ALLOCATE:
 413       return "gs_urb_write_allocate";
 414    case GS_OPCODE_THREAD_END:
 415       return "gs_thread_end";
 416    case GS_OPCODE_SET_WRITE_OFFSET:
 417       return "set_write_offset";
 418    case GS_OPCODE_SET_VERTEX_COUNT:
 419       return "set_vertex_count";
 420    case GS_OPCODE_SET_DWORD_2:
 421       return "set_dword_2";
 422    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 423       return "prepare_channel_masks";
 424    case GS_OPCODE_SET_CHANNEL_MASKS:
 425       return "set_channel_masks";
 426    case GS_OPCODE_GET_INSTANCE_ID:
 427       return "get_instance_id";
 428    case GS_OPCODE_FF_SYNC:
 429       return "ff_sync";
 430    case GS_OPCODE_SET_PRIMITIVE_ID:
 431       return "set_primitive_id";
 432    case GS_OPCODE_SVB_WRITE:
 433       return "gs_svb_write";
 434    case GS_OPCODE_SVB_SET_DST_INDEX:
 435       return "gs_svb_set_dst_index";
 436    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 437       return "gs_ff_sync_set_primitives";
 438    case CS_OPCODE_CS_TERMINATE:
 439       return "cs_terminate";
 440    case SHADER_OPCODE_BARRIER:
 441       return "barrier";
 442    case SHADER_OPCODE_MULH:
 443       return "mulh";
 444    case SHADER_OPCODE_MOV_INDIRECT:
 445       return "mov_indirect";
 446
 447    case VEC4_OPCODE_URB_READ:
 448       return "urb_read";
 449    case TCS_OPCODE_GET_INSTANCE_ID:
 450       return "tcs_get_instance_id";
 451    case TCS_OPCODE_URB_WRITE:
 452       return "tcs_urb_write";
 453    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 454       return "tcs_set_input_urb_offsets";
 455    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 456       return "tcs_set_output_urb_offsets";
 457    case TCS_OPCODE_GET_PRIMITIVE_ID:
 458       return "tcs_get_primitive_id";
 459    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 460       return "tcs_create_barrier_header";
 461    case TCS_OPCODE_SRC0_010_IS_ZERO:
 462       return "tcs_src0<0,1,0>_is_zero";
 463    case TCS_OPCODE_RELEASE_INPUT:
 464       return "tcs_release_input";
 465    case TCS_OPCODE_THREAD_END:
 466       return "tcs_thread_end";
 467    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 468       return "tes_create_input_read_header";
 469    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 470       return "tes_add_indirect_urb_offset";
 471    case TES_OPCODE_GET_PRIMITIVE_ID:
 472       return "tes_get_primitive_id";
 473    }
 474
 475    unreachable("not reached");
 476 }
 477
 478 bool
 479 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 480 {
 481    union {
 482       unsigned ud;
 483       int d;
 484       float f;
 485       double df;
 486    } imm, sat_imm = { 0 };
 487
 488    const unsigned size = type_sz(type);
 489
 490    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 491     * irrelevant, so just check the size of the type and copy from/to an
 492     * appropriately sized field.
 493     */
 494    if (size < 8)
 495       imm.ud = reg->ud;
 496    else
 497       imm.df = reg->df;
 498
 499    switch (type) {
 500    case BRW_REGISTER_TYPE_UD:
 501    case BRW_REGISTER_TYPE_D:
 502    case BRW_REGISTER_TYPE_UW:
 503    case BRW_REGISTER_TYPE_W:
 504    case BRW_REGISTER_TYPE_UQ:
 505    case BRW_REGISTER_TYPE_Q:
 506       /* Nothing to do. */
 507       return false;
 508    case BRW_REGISTER_TYPE_F:
 509       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 510       break;
 511    case BRW_REGISTER_TYPE_DF:
 512       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 513       break;
 514    case BRW_REGISTER_TYPE_UB:
 515    case BRW_REGISTER_TYPE_B:
 516       unreachable("no UB/B immediates");
 517    case BRW_REGISTER_TYPE_V:
 518    case BRW_REGISTER_TYPE_UV:
 519    case BRW_REGISTER_TYPE_VF:
 520       unreachable("unimplemented: saturate vector immediate");
 521    case BRW_REGISTER_TYPE_HF:
 522       unreachable("unimplemented: saturate HF immediate");
 523    }
 524
 525    if (size < 8) {
 526       if (imm.ud != sat_imm.ud) {
 527          reg->ud = sat_imm.ud;
 528          return true;
 529       }
 530    } else {
 531       if (imm.df != sat_imm.df) {
 532          reg->df = sat_imm.df;
 533          return true;
 534       }
 535    }
 536    return false;
 537 }
 538
 539 bool
 540 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 541 {
 542    switch (type) {
 543    case BRW_REGISTER_TYPE_D:
 544    case BRW_REGISTER_TYPE_UD:
 545       reg->d = -reg->d;
 546       return true;
 547    case BRW_REGISTER_TYPE_W:
 548    case BRW_REGISTER_TYPE_UW:
 549       reg->d = -(int16_t)reg->ud;
 550       return true;
 551    case BRW_REGISTER_TYPE_F:
 552       reg->f = -reg->f;
 553       return true;
 554    case BRW_REGISTER_TYPE_VF:
 555       reg->ud ^= 0x80808080;
 556       return true;
 557    case BRW_REGISTER_TYPE_DF:
 558       reg->df = -reg->df;
 559       return true;
 560    case BRW_REGISTER_TYPE_UB:
 561    case BRW_REGISTER_TYPE_B:
 562       unreachable("no UB/B immediates");
 563    case BRW_REGISTER_TYPE_UV:
 564    case BRW_REGISTER_TYPE_V:
 565       assert(!"unimplemented: negate UV/V immediate");
 566    case BRW_REGISTER_TYPE_UQ:
 567    case BRW_REGISTER_TYPE_Q:
 568       assert(!"unimplemented: negate UQ/Q immediate");
 569    case BRW_REGISTER_TYPE_HF:
 570       assert(!"unimplemented: negate HF immediate");
 571    }
 572
 573    return false;
 574 }
 575
 576 bool
 577 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 578 {
 579    switch (type) {
 580    case BRW_REGISTER_TYPE_D:
 581       reg->d = abs(reg->d);
 582       return true;
 583    case BRW_REGISTER_TYPE_W:
 584       reg->d = abs((int16_t)reg->ud);
 585       return true;
 586    case BRW_REGISTER_TYPE_F:
 587       reg->f = fabsf(reg->f);
 588       return true;
 589    case BRW_REGISTER_TYPE_DF:
 590       reg->df = fabs(reg->df);
 591       return true;
 592    case BRW_REGISTER_TYPE_VF:
 593       reg->ud &= ~0x80808080;
 594       return true;
 595    case BRW_REGISTER_TYPE_UB:
 596    case BRW_REGISTER_TYPE_B:
 597       unreachable("no UB/B immediates");
 598    case BRW_REGISTER_TYPE_UQ:
 599    case BRW_REGISTER_TYPE_UD:
 600    case BRW_REGISTER_TYPE_UW:
 601    case BRW_REGISTER_TYPE_UV:
 602       /* Presumably the absolute value modifier on an unsigned source is a
 603        * nop, but it would be nice to confirm.
 604        */
 605       assert(!"unimplemented: abs unsigned immediate");
 606    case BRW_REGISTER_TYPE_V:
 607       assert(!"unimplemented: abs V immediate");
 608    case BRW_REGISTER_TYPE_Q:
 609       assert(!"unimplemented: abs Q immediate");
 610    case BRW_REGISTER_TYPE_HF:
 611       assert(!"unimplemented: abs HF immediate");
 612    }
 613
 614    return false;
 615 }
 616
 617 unsigned
 618 tesslevel_outer_components(GLenum tes_primitive_mode)
 619 {
 620    switch (tes_primitive_mode) {
 621    case GL_QUADS:
 622       return 4;
 623    case GL_TRIANGLES:
 624       return 3;
 625    case GL_ISOLINES:
 626       return 2;
 627    default:
 628       unreachable("Bogus tessellation domain");
 629    }
 630    return 0;
 631 }
 632
 633 unsigned
 634 tesslevel_inner_components(GLenum tes_primitive_mode)
 635 {
 636    switch (tes_primitive_mode) {
 637    case GL_QUADS:
 638       return 2;
 639    case GL_TRIANGLES:
 640       return 1;
 641    case GL_ISOLINES:
 642       return 0;
 643    default:
 644       unreachable("Bogus tessellation domain");
 645    }
 646    return 0;
 647 }
 648
 649 /**
 650  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 651  * that's stored backwards, i.e. .wzyx.
 652  */
 653 unsigned
 654 writemask_for_backwards_vector(unsigned mask)
 655 {
 656    unsigned new_mask = 0;
 657
 658    for (int i = 0; i < 4; i++)
 659       new_mask |= ((mask >> i) & 1) << (3 - i);
 660
 661    return new_mask;
 662 }
 663
 664 backend_shader::backend_shader(const struct brw_compiler *compiler,
 665                                void *log_data,
 666                                void *mem_ctx,
 667                                const nir_shader *shader,
 668                                struct brw_stage_prog_data *stage_prog_data)
 669    : compiler(compiler),
 670      log_data(log_data),
 671      devinfo(compiler->devinfo),
 672      nir(shader),
 673      stage_prog_data(stage_prog_data),
 674      mem_ctx(mem_ctx),
 675      cfg(NULL),
 676      stage(shader->stage)
 677 {
 678    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 679    stage_name = _mesa_shader_stage_to_string(stage);
 680    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 681    is_passthrough_shader =
 682       nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
 683 }
 684
 685 bool
 686 backend_reg::equals(const backend_reg &r) const
 687 {
 688    return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
 689 }
 690
 691 bool
 692 backend_reg::is_zero() const
 693 {
 694    if (file != IMM)
 695       return false;
 696
 697    switch (type) {
 698    case BRW_REGISTER_TYPE_F:
 699       return f == 0;
 700    case BRW_REGISTER_TYPE_DF:
 701       return df == 0;
 702    case BRW_REGISTER_TYPE_D:
 703    case BRW_REGISTER_TYPE_UD:
 704       return d == 0;
 705    default:
 706       return false;
 707    }
 708 }
 709
 710 bool
 711 backend_reg::is_one() const
 712 {
 713    if (file != IMM)
 714       return false;
 715
 716    switch (type) {
 717    case BRW_REGISTER_TYPE_F:
 718       return f == 1.0f;
 719    case BRW_REGISTER_TYPE_DF:
 720       return df == 1.0;
 721    case BRW_REGISTER_TYPE_D:
 722    case BRW_REGISTER_TYPE_UD:
 723       return d == 1;
 724    default:
 725       return false;
 726    }
 727 }
 728
 729 bool
 730 backend_reg::is_negative_one() const
 731 {
 732    if (file != IMM)
 733       return false;
 734
 735    switch (type) {
 736    case BRW_REGISTER_TYPE_F:
 737       return f == -1.0;
 738    case BRW_REGISTER_TYPE_DF:
 739       return df == -1.0;
 740    case BRW_REGISTER_TYPE_D:
 741       return d == -1;
 742    default:
 743       return false;
 744    }
 745 }
 746
 747 bool
 748 backend_reg::is_null() const
 749 {
 750    return file == ARF && nr == BRW_ARF_NULL;
 751 }
 752
 753
 754 bool
 755 backend_reg::is_accumulator() const
 756 {
 757    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 758 }
 759
 760 bool
 761 backend_reg::in_range(const backend_reg &r, unsigned n) const
 762 {
 763    return (file == r.file &&
 764            nr == r.nr &&
 765            reg_offset >= r.reg_offset &&
 766            reg_offset < r.reg_offset + n);
 767 }
 768
 769 bool
 770 backend_instruction::is_commutative() const
 771 {
 772    switch (opcode) {
 773    case BRW_OPCODE_AND:
 774    case BRW_OPCODE_OR:
 775    case BRW_OPCODE_XOR:
 776    case BRW_OPCODE_ADD:
 777    case BRW_OPCODE_MUL:
 778    case SHADER_OPCODE_MULH:
 779       return true;
 780    case BRW_OPCODE_SEL:
 781       /* MIN and MAX are commutative. */
 782       if (conditional_mod == BRW_CONDITIONAL_GE ||
 783           conditional_mod == BRW_CONDITIONAL_L) {
 784          return true;
 785       }
 786       /* fallthrough */
 787    default:
 788       return false;
 789    }
 790 }
 791
 792 bool
 793 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
 794 {
 795    return ::is_3src(devinfo, opcode);
 796 }
 797
 798 bool
 799 backend_instruction::is_tex() const
 800 {
 801    return (opcode == SHADER_OPCODE_TEX ||
 802            opcode == FS_OPCODE_TXB ||
 803            opcode == SHADER_OPCODE_TXD ||
 804            opcode == SHADER_OPCODE_TXF ||
 805            opcode == SHADER_OPCODE_TXF_CMS ||
 806            opcode == SHADER_OPCODE_TXF_CMS_W ||
 807            opcode == SHADER_OPCODE_TXF_UMS ||
 808            opcode == SHADER_OPCODE_TXF_MCS ||
 809            opcode == SHADER_OPCODE_TXL ||
 810            opcode == SHADER_OPCODE_TXS ||
 811            opcode == SHADER_OPCODE_LOD ||
 812            opcode == SHADER_OPCODE_TG4 ||
 813            opcode == SHADER_OPCODE_TG4_OFFSET ||
 814            opcode == SHADER_OPCODE_SAMPLEINFO);
 815 }
 816
 817 bool
 818 backend_instruction::is_math() const
 819 {
 820    return (opcode == SHADER_OPCODE_RCP ||
 821            opcode == SHADER_OPCODE_RSQ ||
 822            opcode == SHADER_OPCODE_SQRT ||
 823            opcode == SHADER_OPCODE_EXP2 ||
 824            opcode == SHADER_OPCODE_LOG2 ||
 825            opcode == SHADER_OPCODE_SIN ||
 826            opcode == SHADER_OPCODE_COS ||
 827            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 828            opcode == SHADER_OPCODE_INT_REMAINDER ||
 829            opcode == SHADER_OPCODE_POW);
 830 }
 831
 832 bool
 833 backend_instruction::is_control_flow() const
 834 {
 835    switch (opcode) {
 836    case BRW_OPCODE_DO:
 837    case BRW_OPCODE_WHILE:
 838    case BRW_OPCODE_IF:
 839    case BRW_OPCODE_ELSE:
 840    case BRW_OPCODE_ENDIF:
 841    case BRW_OPCODE_BREAK:
 842    case BRW_OPCODE_CONTINUE:
 843       return true;
 844    default:
 845       return false;
 846    }
 847 }
 848
 849 bool
 850 backend_instruction::can_do_source_mods() const
 851 {
 852    switch (opcode) {
 853    case BRW_OPCODE_ADDC:
 854    case BRW_OPCODE_BFE:
 855    case BRW_OPCODE_BFI1:
 856    case BRW_OPCODE_BFI2:
 857    case BRW_OPCODE_BFREV:
 858    case BRW_OPCODE_CBIT:
 859    case BRW_OPCODE_FBH:
 860    case BRW_OPCODE_FBL:
 861    case BRW_OPCODE_SUBB:
 862       return false;
 863    default:
 864       return true;
 865    }
 866 }
 867
 868 bool
 869 backend_instruction::can_do_saturate() const
 870 {
 871    switch (opcode) {
 872    case BRW_OPCODE_ADD:
 873    case BRW_OPCODE_ASR:
 874    case BRW_OPCODE_AVG:
 875    case BRW_OPCODE_DP2:
 876    case BRW_OPCODE_DP3:
 877    case BRW_OPCODE_DP4:
 878    case BRW_OPCODE_DPH:
 879    case BRW_OPCODE_F16TO32:
 880    case BRW_OPCODE_F32TO16:
 881    case BRW_OPCODE_LINE:
 882    case BRW_OPCODE_LRP:
 883    case BRW_OPCODE_MAC:
 884    case BRW_OPCODE_MAD:
 885    case BRW_OPCODE_MATH:
 886    case BRW_OPCODE_MOV:
 887    case BRW_OPCODE_MUL:
 888    case SHADER_OPCODE_MULH:
 889    case BRW_OPCODE_PLN:
 890    case BRW_OPCODE_RNDD:
 891    case BRW_OPCODE_RNDE:
 892    case BRW_OPCODE_RNDU:
 893    case BRW_OPCODE_RNDZ:
 894    case BRW_OPCODE_SEL:
 895    case BRW_OPCODE_SHL:
 896    case BRW_OPCODE_SHR:
 897    case FS_OPCODE_LINTERP:
 898    case SHADER_OPCODE_COS:
 899    case SHADER_OPCODE_EXP2:
 900    case SHADER_OPCODE_LOG2:
 901    case SHADER_OPCODE_POW:
 902    case SHADER_OPCODE_RCP:
 903    case SHADER_OPCODE_RSQ:
 904    case SHADER_OPCODE_SIN:
 905    case SHADER_OPCODE_SQRT:
 906       return true;
 907    default:
 908       return false;
 909    }
 910 }
 911
 912 bool
 913 backend_instruction::can_do_cmod() const
 914 {
 915    switch (opcode) {
 916    case BRW_OPCODE_ADD:
 917    case BRW_OPCODE_ADDC:
 918    case BRW_OPCODE_AND:
 919    case BRW_OPCODE_ASR:
 920    case BRW_OPCODE_AVG:
 921    case BRW_OPCODE_CMP:
 922    case BRW_OPCODE_CMPN:
 923    case BRW_OPCODE_DP2:
 924    case BRW_OPCODE_DP3:
 925    case BRW_OPCODE_DP4:
 926    case BRW_OPCODE_DPH:
 927    case BRW_OPCODE_F16TO32:
 928    case BRW_OPCODE_F32TO16:
 929    case BRW_OPCODE_FRC:
 930    case BRW_OPCODE_LINE:
 931    case BRW_OPCODE_LRP:
 932    case BRW_OPCODE_LZD:
 933    case BRW_OPCODE_MAC:
 934    case BRW_OPCODE_MACH:
 935    case BRW_OPCODE_MAD:
 936    case BRW_OPCODE_MOV:
 937    case BRW_OPCODE_MUL:
 938    case BRW_OPCODE_NOT:
 939    case BRW_OPCODE_OR:
 940    case BRW_OPCODE_PLN:
 941    case BRW_OPCODE_RNDD:
 942    case BRW_OPCODE_RNDE:
 943    case BRW_OPCODE_RNDU:
 944    case BRW_OPCODE_RNDZ:
 945    case BRW_OPCODE_SAD2:
 946    case BRW_OPCODE_SADA2:
 947    case BRW_OPCODE_SHL:
 948    case BRW_OPCODE_SHR:
 949    case BRW_OPCODE_SUBB:
 950    case BRW_OPCODE_XOR:
 951    case FS_OPCODE_CINTERP:
 952    case FS_OPCODE_LINTERP:
 953       return true;
 954    default:
 955       return false;
 956    }
 957 }
 958
 959 bool
 960 backend_instruction::reads_accumulator_implicitly() const
 961 {
 962    switch (opcode) {
 963    case BRW_OPCODE_MAC:
 964    case BRW_OPCODE_MACH:
 965    case BRW_OPCODE_SADA2:
 966       return true;
 967    default:
 968       return false;
 969    }
 970 }
 971
 972 bool
 973 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 974 {
 975    return writes_accumulator ||
 976           (devinfo->gen < 6 &&
 977            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 978             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 979              opcode != FS_OPCODE_CINTERP)));
 980 }
 981
 982 bool
 983 backend_instruction::has_side_effects() const
 984 {
 985    switch (opcode) {
 986    case SHADER_OPCODE_UNTYPED_ATOMIC:
 987    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 988    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 989    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 990    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 991    case SHADER_OPCODE_TYPED_ATOMIC:
 992    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 993    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 994    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 995    case SHADER_OPCODE_MEMORY_FENCE:
 996    case SHADER_OPCODE_URB_WRITE_SIMD8:
 997    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 998    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 999    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1000    case FS_OPCODE_FB_WRITE:
1001    case SHADER_OPCODE_BARRIER:
1002    case TCS_OPCODE_URB_WRITE:
1003    case TCS_OPCODE_RELEASE_INPUT:
1004       return true;
1005    default:
1006       return false;
1007    }
1008 }
1009
1010 bool
1011 backend_instruction::is_volatile() const
1012 {
1013    switch (opcode) {
1014    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1015    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1016    case SHADER_OPCODE_TYPED_SURFACE_READ:
1017    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1018    case SHADER_OPCODE_URB_READ_SIMD8:
1019    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1020    case VEC4_OPCODE_URB_READ:
1021       return true;
1022    default:
1023       return false;
1024    }
1025 }
1026
1027 #ifndef NDEBUG
1028 static bool
1029 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1030 {
1031    bool found = false;
1032    foreach_inst_in_block (backend_instruction, i, block) {
1033       if (inst == i) {
1034          found = true;
1035       }
1036    }
1037    return found;
1038 }
1039 #endif
1040
1041 static void
1042 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1043 {
1044    for (bblock_t *block_iter = start_block->next();
1045         block_iter;
1046         block_iter = block_iter->next()) {
1047       block_iter->start_ip += ip_adjustment;
1048       block_iter->end_ip += ip_adjustment;
1049    }
1050 }
1051
1052 void
1053 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1054 {
1055    assert(this != inst);
1056
1057    if (!this->is_head_sentinel())
1058       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1059
1060    block->end_ip++;
1061
1062    adjust_later_block_ips(block, 1);
1063
1064    exec_node::insert_after(inst);
1065 }
1066
1067 void
1068 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1069 {
1070    assert(this != inst);
1071
1072    if (!this->is_tail_sentinel())
1073       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1074
1075    block->end_ip++;
1076
1077    adjust_later_block_ips(block, 1);
1078
1079    exec_node::insert_before(inst);
1080 }
1081
1082 void
1083 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1084 {
1085    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1086
1087    unsigned num_inst = list->length();
1088
1089    block->end_ip += num_inst;
1090
1091    adjust_later_block_ips(block, num_inst);
1092
1093    exec_node::insert_before(list);
1094 }
1095
1096 void
1097 backend_instruction::remove(bblock_t *block)
1098 {
1099    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1100
1101    adjust_later_block_ips(block, -1);
1102
1103    if (block->start_ip == block->end_ip) {
1104       block->cfg->remove_block(block);
1105    } else {
1106       block->end_ip--;
1107    }
1108
1109    exec_node::remove();
1110 }
1111
1112 void
1113 backend_shader::dump_instructions()
1114 {
1115    dump_instructions(NULL);
1116 }
1117
1118 void
1119 backend_shader::dump_instructions(const char *name)
1120 {
1121    FILE *file = stderr;
1122    if (name && geteuid() != 0) {
1123       file = fopen(name, "w");
1124       if (!file)
1125          file = stderr;
1126    }
1127
1128    if (cfg) {
1129       int ip = 0;
1130       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1131          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1132             fprintf(file, "%4d: ", ip++);
1133          dump_instruction(inst, file);
1134       }
1135    } else {
1136       int ip = 0;
1137       foreach_in_list(backend_instruction, inst, &instructions) {
1138          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1139             fprintf(file, "%4d: ", ip++);
1140          dump_instruction(inst, file);
1141       }
1142    }
1143
1144    if (file != stderr) {
1145       fclose(file);
1146    }
1147 }
1148
1149 void
1150 backend_shader::calculate_cfg()
1151 {
1152    if (this->cfg)
1153       return;
1154    cfg = new(mem_ctx) cfg_t(&this->instructions);
1155 }
1156
1157 /**
1158  * Sets up the starting offsets for the groups of binding table entries
1159  * commong to all pipeline stages.
1160  *
1161  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1162  * unused but also make sure that addition of small offsets to them will
1163  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1164  */
1165 void
1166 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1167                                         const struct brw_device_info *devinfo,
1168                                         const struct gl_shader_program *shader_prog,
1169                                         const struct gl_program *prog,
1170                                         struct brw_stage_prog_data *stage_prog_data,
1171                                         uint32_t next_binding_table_offset)
1172 {
1173    const struct gl_shader *shader = NULL;
1174    int num_textures = _mesa_fls(prog->SamplersUsed);
1175
1176    if (shader_prog)
1177       shader = shader_prog->_LinkedShaders[stage];
1178
1179    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1180    next_binding_table_offset += num_textures;
1181
1182    if (shader) {
1183       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1184       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1185       next_binding_table_offset += shader->NumUniformBlocks;
1186
1187       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1188       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1189       next_binding_table_offset += shader->NumShaderStorageBlocks;
1190    } else {
1191       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1192       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1193    }
1194
1195    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1196       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1197       next_binding_table_offset++;
1198    } else {
1199       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1200    }
1201
1202    if (prog->UsesGather) {
1203       if (devinfo->gen >= 8) {
1204          stage_prog_data->binding_table.gather_texture_start =
1205             stage_prog_data->binding_table.texture_start;
1206       } else {
1207          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1208          next_binding_table_offset += num_textures;
1209       }
1210    } else {
1211       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1212    }
1213
1214    if (shader && shader->NumAtomicBuffers) {
1215       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1216       next_binding_table_offset += shader->NumAtomicBuffers;
1217    } else {
1218       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1219    }
1220
1221    if (shader && shader->NumImages) {
1222       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1223       next_binding_table_offset += shader->NumImages;
1224    } else {
1225       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1226    }
1227
1228    /* This may or may not be used depending on how the compile goes. */
1229    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1230    next_binding_table_offset++;
1231
1232    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1233
1234    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1235 }
1236
1237 static void
1238 setup_vec4_uniform_value(const gl_constant_value **params,
1239                          const gl_constant_value *values,
1240                          unsigned n)
1241 {
1242    static const gl_constant_value zero = { 0 };
1243
1244    for (unsigned i = 0; i < n; ++i)
1245       params[i] = &values[i];
1246
1247    for (unsigned i = n; i < 4; ++i)
1248       params[i] = &zero;
1249 }
1250
1251 void
1252 brw_setup_image_uniform_values(gl_shader_stage stage,
1253                                struct brw_stage_prog_data *stage_prog_data,
1254                                unsigned param_start_index,
1255                                const gl_uniform_storage *storage)
1256 {
1257    const gl_constant_value **param =
1258       &stage_prog_data->param[param_start_index];
1259
1260    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1261       const unsigned image_idx = storage->opaque[stage].index + i;
1262       const brw_image_param *image_param =
1263          &stage_prog_data->image_param[image_idx];
1264
1265       /* Upload the brw_image_param structure.  The order is expected to match
1266        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1267        */
1268       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1269          (const gl_constant_value *)&image_param->surface_idx, 1);
1270       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1271          (const gl_constant_value *)image_param->offset, 2);
1272       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1273          (const gl_constant_value *)image_param->size, 3);
1274       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1275          (const gl_constant_value *)image_param->stride, 4);
1276       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1277          (const gl_constant_value *)image_param->tiling, 3);
1278       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1279          (const gl_constant_value *)image_param->swizzling, 2);
1280       param += BRW_IMAGE_PARAM_SIZE;
1281
1282       brw_mark_surface_used(
1283          stage_prog_data,
1284          stage_prog_data->binding_table.image_start + image_idx);
1285    }
1286 }
1287
1288 /**
1289  * Decide which set of clip planes should be used when clipping via
1290  * gl_Position or gl_ClipVertex.
1291  */
1292 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1293 {
1294    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1295       /* There is currently a GLSL vertex shader, so clip according to GLSL
1296        * rules, which means compare gl_ClipVertex (or gl_Position, if
1297        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1298        * that were stored in EyeUserPlane at the time the clip planes were
1299        * specified.
1300        */
1301       return ctx->Transform.EyeUserPlane;
1302    } else {
1303       /* Either we are using fixed function or an ARB vertex program.  In
1304        * either case the clip planes are going to be compared against
1305        * gl_Position (which is in clip coordinates) so we have to clip using
1306        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1307        * core.
1308        */
1309       return ctx->Transform._ClipUserPlane;
1310    }
1311 }
1312
1313 extern "C" const unsigned *
1314 brw_compile_tes(const struct brw_compiler *compiler,
1315                 void *log_data,
1316                 void *mem_ctx,
1317                 const struct brw_tes_prog_key *key,
1318                 struct brw_tes_prog_data *prog_data,
1319                 const nir_shader *src_shader,
1320                 struct gl_shader_program *shader_prog,
1321                 int shader_time_index,
1322                 unsigned *final_assembly_size,
1323                 char **error_str)
1324 {
1325    const struct brw_device_info *devinfo = compiler->devinfo;
1326    struct gl_shader *shader =
1327       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1328    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1329
1330    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1331    nir->info.inputs_read = key->inputs_read;
1332    nir->info.patch_inputs_read = key->patch_inputs_read;
1333
1334    struct brw_vue_map input_vue_map;
1335    brw_compute_tess_vue_map(&input_vue_map,
1336                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1337                             nir->info.patch_inputs_read);
1338
1339    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1340    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1341    brw_nir_lower_vue_outputs(nir, is_scalar);
1342    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1343
1344    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1345                        nir->info.outputs_written,
1346                        nir->info.separate_shader);
1347
1348    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1349
1350    assert(output_size_bytes >= 1);
1351    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1352       if (error_str)
1353          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1354       return NULL;
1355    }
1356
1357    /* URB entry sizes are stored as a multiple of 64 bytes. */
1358    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1359
1360    bool need_patch_header = nir->info.system_values_read &
1361       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1362        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1363
1364    /* The TES will pull most inputs using URB read messages.
1365     *
1366     * However, we push the patch header for TessLevel factors when required,
1367     * as it's a tiny amount of extra data.
1368     */
1369    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1370
1371    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1372       fprintf(stderr, "TES Input ");
1373       brw_print_vue_map(stderr, &input_vue_map);
1374       fprintf(stderr, "TES Output ");
1375       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1376    }
1377
1378    if (is_scalar) {
1379       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1380                    &prog_data->base.base, shader->Program, nir, 8,
1381                    shader_time_index, &input_vue_map);
1382       if (!v.run_tes()) {
1383          if (error_str)
1384             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1385          return NULL;
1386       }
1387
1388       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1389       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1390
1391       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1392                      &prog_data->base.base, v.promoted_constants, false,
1393                      MESA_SHADER_TESS_EVAL);
1394       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1395          g.enable_debug(ralloc_asprintf(mem_ctx,
1396                                         "%s tessellation evaluation shader %s",
1397                                         nir->info.label ? nir->info.label
1398                                                         : "unnamed",
1399                                         nir->info.name));
1400       }
1401
1402       g.generate_code(v.cfg, 8);
1403
1404       return g.get_assembly(final_assembly_size);
1405    } else {
1406       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1407                               nir, mem_ctx, shader_time_index);
1408       if (!v.run()) {
1409          if (error_str)
1410             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1411          return NULL;
1412       }
1413
1414       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1415          v.dump_instructions();
1416
1417       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1418                                         &prog_data->base, v.cfg,
1419                                         final_assembly_size);
1420    }
1421 }