src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
  88       compiler->scalar_vs = true;
  89
  90    nir_shader_compiler_options *nir_options =
  91       rzalloc(compiler, nir_shader_compiler_options);
  92    nir_options->native_integers = true;
  93    /* In order to help allow for better CSE at the NIR level we tell NIR
  94     * to split all ffma instructions during opt_algebraic and we then
  95     * re-combine them as a later step.
  96     */
  97    nir_options->lower_ffma = true;
  98    nir_options->lower_sub = true;
  99
 100    /* We want the GLSL compiler to emit code that uses condition codes */
 101    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 102       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 103       compiler->glsl_compiler_options[i].MaxIfDepth =
 104          devinfo->gen < 6 ? 16 : UINT_MAX;
 105
 106       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 107       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 108       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 109       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 110       compiler->glsl_compiler_options[i].EmitNoIndirectOutput =
 111          (i == MESA_SHADER_FRAGMENT);
 112       compiler->glsl_compiler_options[i].EmitNoIndirectTemp =
 113          (i == MESA_SHADER_FRAGMENT);
 114       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 115       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 116
 117       /* !ARB_gpu_shader5 */
 118       if (devinfo->gen < 7)
 119          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 120    }
 121
 122    compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = true;
 123    compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].OptimizeForAOS = true;
 124
 125    if (compiler->scalar_vs || brw_env_var_as_boolean("INTEL_USE_NIR", false)) {
 126       if (compiler->scalar_vs) {
 127          /* If we're using the scalar backend for vertex shaders, we need to
 128           * configure these accordingly.
 129           */
 130          compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectOutput = true;
 131          compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectTemp = true;
 132       }
 133       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = false;
 134
 135       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions = nir_options;
 136    }
 137
 138    compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions = nir_options;
 139    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions = nir_options;
 140
 141    return compiler;
 142 }
 143
 144 struct gl_shader *
 145 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 146 {
 147    struct brw_shader *shader;
 148
 149    shader = rzalloc(NULL, struct brw_shader);
 150    if (shader) {
 151       shader->base.Type = type;
 152       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 153       shader->base.Name = name;
 154       _mesa_init_shader(ctx, &shader->base);
 155    }
 156
 157    return &shader->base;
 158 }
 159
 160 /**
 161  * Performs a compile of the shader stages even when we don't know
 162  * what non-orthogonal state will be set, in the hope that it reflects
 163  * the eventual NOS used, and thus allows us to produce link failures.
 164  */
 165 static bool
 166 brw_shader_precompile(struct gl_context *ctx,
 167                       struct gl_shader_program *sh_prog)
 168 {
 169    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 170    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 171    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 172    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 173
 174    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 175       return false;
 176
 177    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 178       return false;
 179
 180    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 181       return false;
 182
 183    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 184       return false;
 185
 186    return true;
 187 }
 188
 189 static inline bool
 190 is_scalar_shader_stage(struct brw_context *brw, int stage)
 191 {
 192    switch (stage) {
 193    case MESA_SHADER_FRAGMENT:
 194       return true;
 195    case MESA_SHADER_VERTEX:
 196       return brw->intelScreen->compiler->scalar_vs;
 197    default:
 198       return false;
 199    }
 200 }
 201
 202 static void
 203 brw_lower_packing_builtins(struct brw_context *brw,
 204                            gl_shader_stage shader_type,
 205                            exec_list *ir)
 206 {
 207    int ops = LOWER_PACK_SNORM_2x16
 208            | LOWER_UNPACK_SNORM_2x16
 209            | LOWER_PACK_UNORM_2x16
 210            | LOWER_UNPACK_UNORM_2x16;
 211
 212    if (is_scalar_shader_stage(brw, shader_type)) {
 213       ops |= LOWER_UNPACK_UNORM_4x8
 214            | LOWER_UNPACK_SNORM_4x8
 215            | LOWER_PACK_UNORM_4x8
 216            | LOWER_PACK_SNORM_4x8;
 217    }
 218
 219    if (brw->gen >= 7) {
 220       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 221        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 222        * lowering is needed. For SOA code, the Half2x16 ops must be
 223        * scalarized.
 224        */
 225       if (is_scalar_shader_stage(brw, shader_type)) {
 226          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 227              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 228       }
 229    } else {
 230       ops |= LOWER_PACK_HALF_2x16
 231           |  LOWER_UNPACK_HALF_2x16;
 232    }
 233
 234    lower_packing_builtins(ir, ops);
 235 }
 236
 237 static void
 238 process_glsl_ir(gl_shader_stage stage,
 239                 struct brw_context *brw,
 240                 struct gl_shader_program *shader_prog,
 241                 struct gl_shader *shader)
 242 {
 243    struct gl_context *ctx = &brw->ctx;
 244    const struct gl_shader_compiler_options *options =
 245       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 246
 247    /* Temporary memory context for any new IR. */
 248    void *mem_ctx = ralloc_context(NULL);
 249
 250    ralloc_adopt(mem_ctx, shader->ir);
 251
 252    /* lower_packing_builtins() inserts arithmetic instructions, so it
 253     * must precede lower_instructions().
 254     */
 255    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 256    do_mat_op_to_vec(shader->ir);
 257    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 258    lower_instructions(shader->ir,
 259                       MOD_TO_FLOOR |
 260                       DIV_TO_MUL_RCP |
 261                       SUB_TO_ADD_NEG |
 262                       EXP_TO_EXP2 |
 263                       LOG_TO_LOG2 |
 264                       bitfield_insert |
 265                       LDEXP_TO_ARITH |
 266                       CARRY_TO_ARITH |
 267                       BORROW_TO_ARITH);
 268
 269    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 270     * if-statements need to be flattened.
 271     */
 272    if (brw->gen < 6)
 273       lower_if_to_cond_assign(shader->ir, 16);
 274
 275    do_lower_texture_projection(shader->ir);
 276    brw_lower_texture_gradients(brw, shader->ir);
 277    do_vec_index_to_cond_assign(shader->ir);
 278    lower_vector_insert(shader->ir, true);
 279    if (options->NirOptions == NULL)
 280       brw_do_cubemap_normalize(shader->ir);
 281    lower_offset_arrays(shader->ir);
 282    brw_do_lower_unnormalized_offset(shader->ir);
 283    lower_noise(shader->ir);
 284    lower_quadop_vector(shader->ir, false);
 285
 286    bool lowered_variable_indexing =
 287       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 288                                           shader->ir,
 289                                           options->EmitNoIndirectInput,
 290                                           options->EmitNoIndirectOutput,
 291                                           options->EmitNoIndirectTemp,
 292                                           options->EmitNoIndirectUniform);
 293
 294    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 295       perf_debug("Unsupported form of variable indexing in %s; falling "
 296                  "back to very inefficient code generation\n",
 297                  _mesa_shader_stage_to_abbrev(shader->Stage));
 298    }
 299
 300    lower_ubo_reference(shader, shader->ir);
 301
 302    bool progress;
 303    do {
 304       progress = false;
 305
 306       if (is_scalar_shader_stage(brw, shader->Stage)) {
 307          brw_do_channel_expressions(shader->ir);
 308          brw_do_vector_splitting(shader->ir);
 309       }
 310
 311       progress = do_lower_jumps(shader->ir, true, true,
 312                                 true, /* main return */
 313                                 false, /* continue */
 314                                 false /* loops */
 315                                 ) || progress;
 316
 317       progress = do_common_optimization(shader->ir, true, true,
 318                                         options, ctx->Const.NativeIntegers) || progress;
 319    } while (progress);
 320
 321    if (options->NirOptions != NULL)
 322       lower_output_reads(stage, shader->ir);
 323
 324    validate_ir_tree(shader->ir);
 325
 326    /* Now that we've finished altering the linked IR, reparent any live IR back
 327     * to the permanent memory context, and free the temporary one (discarding any
 328     * junk we optimized away).
 329     */
 330    reparent_ir(shader->ir, shader->ir);
 331    ralloc_free(mem_ctx);
 332
 333    if (ctx->_Shader->Flags & GLSL_DUMP) {
 334       fprintf(stderr, "\n");
 335       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 336               _mesa_shader_stage_to_string(shader->Stage),
 337               shader_prog->Name);
 338       _mesa_print_ir(stderr, shader->ir, NULL);
 339       fprintf(stderr, "\n");
 340    }
 341 }
 342
 343 GLboolean
 344 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 345 {
 346    struct brw_context *brw = brw_context(ctx);
 347    unsigned int stage;
 348
 349    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 350       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 351       const struct gl_shader_compiler_options *options =
 352          &ctx->Const.ShaderCompilerOptions[stage];
 353
 354       if (!shader)
 355          continue;
 356
 357       struct gl_program *prog =
 358          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 359                                 shader->Name);
 360       if (!prog)
 361         return false;
 362       prog->Parameters = _mesa_new_parameter_list();
 363
 364       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 365
 366       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 367
 368       /* Make a pass over the IR to add state references for any built-in
 369        * uniforms that are used.  This has to be done now (during linking).
 370        * Code generation doesn't happen until the first time this shader is
 371        * used for rendering.  Waiting until then to generate the parameters is
 372        * too late.  At that point, the values for the built-in uniforms won't
 373        * get sent to the shader.
 374        */
 375       foreach_in_list(ir_instruction, node, shader->ir) {
 376          ir_variable *var = node->as_variable();
 377
 378          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 379              || (strncmp(var->name, "gl_", 3) != 0))
 380             continue;
 381
 382          const ir_state_slot *const slots = var->get_state_slots();
 383          assert(slots != NULL);
 384
 385          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 386             _mesa_add_state_reference(prog->Parameters,
 387                                       (gl_state_index *) slots[i].tokens);
 388          }
 389       }
 390
 391       do_set_program_inouts(shader->ir, prog, shader->Stage);
 392
 393       prog->SamplersUsed = shader->active_samplers;
 394       prog->ShadowSamplers = shader->shadow_samplers;
 395       _mesa_update_shader_textures_used(shProg, prog);
 396
 397       _mesa_reference_program(ctx, &shader->Program, prog);
 398
 399       brw_add_texrect_params(prog);
 400
 401       if (options->NirOptions)
 402          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 403
 404       _mesa_reference_program(ctx, &prog, NULL);
 405    }
 406
 407    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 408       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 409          const struct gl_shader *sh = shProg->Shaders[i];
 410          if (!sh)
 411             continue;
 412
 413          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 414                  _mesa_shader_stage_to_string(sh->Stage),
 415                  i, shProg->Name);
 416          fprintf(stderr, "%s", sh->Source);
 417          fprintf(stderr, "\n");
 418       }
 419    }
 420
 421    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 422       return false;
 423
 424    return true;
 425 }
 426
 427
 428 enum brw_reg_type
 429 brw_type_for_base_type(const struct glsl_type *type)
 430 {
 431    switch (type->base_type) {
 432    case GLSL_TYPE_FLOAT:
 433       return BRW_REGISTER_TYPE_F;
 434    case GLSL_TYPE_INT:
 435    case GLSL_TYPE_BOOL:
 436    case GLSL_TYPE_SUBROUTINE:
 437       return BRW_REGISTER_TYPE_D;
 438    case GLSL_TYPE_UINT:
 439       return BRW_REGISTER_TYPE_UD;
 440    case GLSL_TYPE_ARRAY:
 441       return brw_type_for_base_type(type->fields.array);
 442    case GLSL_TYPE_STRUCT:
 443    case GLSL_TYPE_SAMPLER:
 444    case GLSL_TYPE_ATOMIC_UINT:
 445       /* These should be overridden with the type of the member when
 446        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 447        * way to trip up if we don't.
 448        */
 449       return BRW_REGISTER_TYPE_UD;
 450    case GLSL_TYPE_IMAGE:
 451       return BRW_REGISTER_TYPE_UD;
 452    case GLSL_TYPE_VOID:
 453    case GLSL_TYPE_ERROR:
 454    case GLSL_TYPE_INTERFACE:
 455    case GLSL_TYPE_DOUBLE:
 456       unreachable("not reached");
 457    }
 458
 459    return BRW_REGISTER_TYPE_F;
 460 }
 461
 462 enum brw_conditional_mod
 463 brw_conditional_for_comparison(unsigned int op)
 464 {
 465    switch (op) {
 466    case ir_binop_less:
 467       return BRW_CONDITIONAL_L;
 468    case ir_binop_greater:
 469       return BRW_CONDITIONAL_G;
 470    case ir_binop_lequal:
 471       return BRW_CONDITIONAL_LE;
 472    case ir_binop_gequal:
 473       return BRW_CONDITIONAL_GE;
 474    case ir_binop_equal:
 475    case ir_binop_all_equal: /* same as equal for scalars */
 476       return BRW_CONDITIONAL_Z;
 477    case ir_binop_nequal:
 478    case ir_binop_any_nequal: /* same as nequal for scalars */
 479       return BRW_CONDITIONAL_NZ;
 480    default:
 481       unreachable("not reached: bad operation for comparison");
 482    }
 483 }
 484
 485 uint32_t
 486 brw_math_function(enum opcode op)
 487 {
 488    switch (op) {
 489    case SHADER_OPCODE_RCP:
 490       return BRW_MATH_FUNCTION_INV;
 491    case SHADER_OPCODE_RSQ:
 492       return BRW_MATH_FUNCTION_RSQ;
 493    case SHADER_OPCODE_SQRT:
 494       return BRW_MATH_FUNCTION_SQRT;
 495    case SHADER_OPCODE_EXP2:
 496       return BRW_MATH_FUNCTION_EXP;
 497    case SHADER_OPCODE_LOG2:
 498       return BRW_MATH_FUNCTION_LOG;
 499    case SHADER_OPCODE_POW:
 500       return BRW_MATH_FUNCTION_POW;
 501    case SHADER_OPCODE_SIN:
 502       return BRW_MATH_FUNCTION_SIN;
 503    case SHADER_OPCODE_COS:
 504       return BRW_MATH_FUNCTION_COS;
 505    case SHADER_OPCODE_INT_QUOTIENT:
 506       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 507    case SHADER_OPCODE_INT_REMAINDER:
 508       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 509    default:
 510       unreachable("not reached: unknown math function");
 511    }
 512 }
 513
 514 uint32_t
 515 brw_texture_offset(int *offsets, unsigned num_components)
 516 {
 517    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 518
 519    /* Combine all three offsets into a single unsigned dword:
 520     *
 521     *    bits 11:8 - U Offset (X component)
 522     *    bits  7:4 - V Offset (Y component)
 523     *    bits  3:0 - R Offset (Z component)
 524     */
 525    unsigned offset_bits = 0;
 526    for (unsigned i = 0; i < num_components; i++) {
 527       const unsigned shift = 4 * (2 - i);
 528       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 529    }
 530    return offset_bits;
 531 }
 532
 533 const char *
 534 brw_instruction_name(enum opcode op)
 535 {
 536    switch (op) {
 537    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 538       assert(opcode_descs[op].name);
 539       return opcode_descs[op].name;
 540    case FS_OPCODE_FB_WRITE:
 541       return "fb_write";
 542    case FS_OPCODE_FB_WRITE_LOGICAL:
 543       return "fb_write_logical";
 544    case FS_OPCODE_BLORP_FB_WRITE:
 545       return "blorp_fb_write";
 546    case FS_OPCODE_REP_FB_WRITE:
 547       return "rep_fb_write";
 548
 549    case SHADER_OPCODE_RCP:
 550       return "rcp";
 551    case SHADER_OPCODE_RSQ:
 552       return "rsq";
 553    case SHADER_OPCODE_SQRT:
 554       return "sqrt";
 555    case SHADER_OPCODE_EXP2:
 556       return "exp2";
 557    case SHADER_OPCODE_LOG2:
 558       return "log2";
 559    case SHADER_OPCODE_POW:
 560       return "pow";
 561    case SHADER_OPCODE_INT_QUOTIENT:
 562       return "int_quot";
 563    case SHADER_OPCODE_INT_REMAINDER:
 564       return "int_rem";
 565    case SHADER_OPCODE_SIN:
 566       return "sin";
 567    case SHADER_OPCODE_COS:
 568       return "cos";
 569
 570    case SHADER_OPCODE_TEX:
 571       return "tex";
 572    case SHADER_OPCODE_TEX_LOGICAL:
 573       return "tex_logical";
 574    case SHADER_OPCODE_TXD:
 575       return "txd";
 576    case SHADER_OPCODE_TXD_LOGICAL:
 577       return "txd_logical";
 578    case SHADER_OPCODE_TXF:
 579       return "txf";
 580    case SHADER_OPCODE_TXF_LOGICAL:
 581       return "txf_logical";
 582    case SHADER_OPCODE_TXL:
 583       return "txl";
 584    case SHADER_OPCODE_TXL_LOGICAL:
 585       return "txl_logical";
 586    case SHADER_OPCODE_TXS:
 587       return "txs";
 588    case SHADER_OPCODE_TXS_LOGICAL:
 589       return "txs_logical";
 590    case FS_OPCODE_TXB:
 591       return "txb";
 592    case FS_OPCODE_TXB_LOGICAL:
 593       return "txb_logical";
 594    case SHADER_OPCODE_TXF_CMS:
 595       return "txf_cms";
 596    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 597       return "txf_cms_logical";
 598    case SHADER_OPCODE_TXF_UMS:
 599       return "txf_ums";
 600    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 601       return "txf_ums_logical";
 602    case SHADER_OPCODE_TXF_MCS:
 603       return "txf_mcs";
 604    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 605       return "txf_mcs_logical";
 606    case SHADER_OPCODE_LOD:
 607       return "lod";
 608    case SHADER_OPCODE_LOD_LOGICAL:
 609       return "lod_logical";
 610    case SHADER_OPCODE_TG4:
 611       return "tg4";
 612    case SHADER_OPCODE_TG4_LOGICAL:
 613       return "tg4_logical";
 614    case SHADER_OPCODE_TG4_OFFSET:
 615       return "tg4_offset";
 616    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 617       return "tg4_offset_logical";
 618
 619    case SHADER_OPCODE_SHADER_TIME_ADD:
 620       return "shader_time_add";
 621
 622    case SHADER_OPCODE_UNTYPED_ATOMIC:
 623       return "untyped_atomic";
 624    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 625       return "untyped_atomic_logical";
 626    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 627       return "untyped_surface_read";
 628    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 629       return "untyped_surface_read_logical";
 630    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 631       return "untyped_surface_write";
 632    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 633       return "untyped_surface_write_logical";
 634    case SHADER_OPCODE_TYPED_ATOMIC:
 635       return "typed_atomic";
 636    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 637       return "typed_atomic_logical";
 638    case SHADER_OPCODE_TYPED_SURFACE_READ:
 639       return "typed_surface_read";
 640    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 641       return "typed_surface_read_logical";
 642    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 643       return "typed_surface_write";
 644    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 645       return "typed_surface_write_logical";
 646    case SHADER_OPCODE_MEMORY_FENCE:
 647       return "memory_fence";
 648
 649    case SHADER_OPCODE_LOAD_PAYLOAD:
 650       return "load_payload";
 651
 652    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 653       return "gen4_scratch_read";
 654    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 655       return "gen4_scratch_write";
 656    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 657       return "gen7_scratch_read";
 658    case SHADER_OPCODE_URB_WRITE_SIMD8:
 659       return "gen8_urb_write_simd8";
 660
 661    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 662       return "find_live_channel";
 663    case SHADER_OPCODE_BROADCAST:
 664       return "broadcast";
 665
 666    case VEC4_OPCODE_MOV_BYTES:
 667       return "mov_bytes";
 668    case VEC4_OPCODE_PACK_BYTES:
 669       return "pack_bytes";
 670    case VEC4_OPCODE_UNPACK_UNIFORM:
 671       return "unpack_uniform";
 672
 673    case FS_OPCODE_DDX_COARSE:
 674       return "ddx_coarse";
 675    case FS_OPCODE_DDX_FINE:
 676       return "ddx_fine";
 677    case FS_OPCODE_DDY_COARSE:
 678       return "ddy_coarse";
 679    case FS_OPCODE_DDY_FINE:
 680       return "ddy_fine";
 681
 682    case FS_OPCODE_CINTERP:
 683       return "cinterp";
 684    case FS_OPCODE_LINTERP:
 685       return "linterp";
 686
 687    case FS_OPCODE_PIXEL_X:
 688       return "pixel_x";
 689    case FS_OPCODE_PIXEL_Y:
 690       return "pixel_y";
 691
 692    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 693       return "uniform_pull_const";
 694    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 695       return "uniform_pull_const_gen7";
 696    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 697       return "varying_pull_const";
 698    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 699       return "varying_pull_const_gen7";
 700
 701    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 702       return "mov_dispatch_to_flags";
 703    case FS_OPCODE_DISCARD_JUMP:
 704       return "discard_jump";
 705
 706    case FS_OPCODE_SET_SAMPLE_ID:
 707       return "set_sample_id";
 708    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 709       return "set_simd4x2_offset";
 710
 711    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 712       return "pack_half_2x16_split";
 713    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 714       return "unpack_half_2x16_split_x";
 715    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 716       return "unpack_half_2x16_split_y";
 717
 718    case FS_OPCODE_PLACEHOLDER_HALT:
 719       return "placeholder_halt";
 720
 721    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 722       return "interp_centroid";
 723    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 724       return "interp_sample";
 725    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 726       return "interp_shared_offset";
 727    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 728       return "interp_per_slot_offset";
 729
 730    case VS_OPCODE_URB_WRITE:
 731       return "vs_urb_write";
 732    case VS_OPCODE_PULL_CONSTANT_LOAD:
 733       return "pull_constant_load";
 734    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 735       return "pull_constant_load_gen7";
 736
 737    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 738       return "set_simd4x2_header_gen9";
 739
 740    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 741       return "unpack_flags_simd4x2";
 742
 743    case GS_OPCODE_URB_WRITE:
 744       return "gs_urb_write";
 745    case GS_OPCODE_URB_WRITE_ALLOCATE:
 746       return "gs_urb_write_allocate";
 747    case GS_OPCODE_THREAD_END:
 748       return "gs_thread_end";
 749    case GS_OPCODE_SET_WRITE_OFFSET:
 750       return "set_write_offset";
 751    case GS_OPCODE_SET_VERTEX_COUNT:
 752       return "set_vertex_count";
 753    case GS_OPCODE_SET_DWORD_2:
 754       return "set_dword_2";
 755    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 756       return "prepare_channel_masks";
 757    case GS_OPCODE_SET_CHANNEL_MASKS:
 758       return "set_channel_masks";
 759    case GS_OPCODE_GET_INSTANCE_ID:
 760       return "get_instance_id";
 761    case GS_OPCODE_FF_SYNC:
 762       return "ff_sync";
 763    case GS_OPCODE_SET_PRIMITIVE_ID:
 764       return "set_primitive_id";
 765    case GS_OPCODE_SVB_WRITE:
 766       return "gs_svb_write";
 767    case GS_OPCODE_SVB_SET_DST_INDEX:
 768       return "gs_svb_set_dst_index";
 769    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 770       return "gs_ff_sync_set_primitives";
 771    case CS_OPCODE_CS_TERMINATE:
 772       return "cs_terminate";
 773    case SHADER_OPCODE_BARRIER:
 774       return "barrier";
 775    }
 776
 777    unreachable("not reached");
 778 }
 779
 780 bool
 781 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 782 {
 783    union {
 784       unsigned ud;
 785       int d;
 786       float f;
 787    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 788
 789    switch (type) {
 790    case BRW_REGISTER_TYPE_UD:
 791    case BRW_REGISTER_TYPE_D:
 792    case BRW_REGISTER_TYPE_UQ:
 793    case BRW_REGISTER_TYPE_Q:
 794       /* Nothing to do. */
 795       return false;
 796    case BRW_REGISTER_TYPE_UW:
 797       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 798       break;
 799    case BRW_REGISTER_TYPE_W:
 800       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 801       break;
 802    case BRW_REGISTER_TYPE_F:
 803       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 804       break;
 805    case BRW_REGISTER_TYPE_UB:
 806    case BRW_REGISTER_TYPE_B:
 807       unreachable("no UB/B immediates");
 808    case BRW_REGISTER_TYPE_V:
 809    case BRW_REGISTER_TYPE_UV:
 810    case BRW_REGISTER_TYPE_VF:
 811       unreachable("unimplemented: saturate vector immediate");
 812    case BRW_REGISTER_TYPE_DF:
 813    case BRW_REGISTER_TYPE_HF:
 814       unreachable("unimplemented: saturate DF/HF immediate");
 815    }
 816
 817    if (imm.ud != sat_imm.ud) {
 818       reg->dw1.ud = sat_imm.ud;
 819       return true;
 820    }
 821    return false;
 822 }
 823
 824 bool
 825 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 826 {
 827    switch (type) {
 828    case BRW_REGISTER_TYPE_D:
 829    case BRW_REGISTER_TYPE_UD:
 830       reg->dw1.d = -reg->dw1.d;
 831       return true;
 832    case BRW_REGISTER_TYPE_W:
 833    case BRW_REGISTER_TYPE_UW:
 834       reg->dw1.d = -(int16_t)reg->dw1.ud;
 835       return true;
 836    case BRW_REGISTER_TYPE_F:
 837       reg->dw1.f = -reg->dw1.f;
 838       return true;
 839    case BRW_REGISTER_TYPE_VF:
 840       reg->dw1.ud ^= 0x80808080;
 841       return true;
 842    case BRW_REGISTER_TYPE_UB:
 843    case BRW_REGISTER_TYPE_B:
 844       unreachable("no UB/B immediates");
 845    case BRW_REGISTER_TYPE_UV:
 846    case BRW_REGISTER_TYPE_V:
 847       assert(!"unimplemented: negate UV/V immediate");
 848    case BRW_REGISTER_TYPE_UQ:
 849    case BRW_REGISTER_TYPE_Q:
 850       assert(!"unimplemented: negate UQ/Q immediate");
 851    case BRW_REGISTER_TYPE_DF:
 852    case BRW_REGISTER_TYPE_HF:
 853       assert(!"unimplemented: negate DF/HF immediate");
 854    }
 855
 856    return false;
 857 }
 858
 859 bool
 860 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 861 {
 862    switch (type) {
 863    case BRW_REGISTER_TYPE_D:
 864       reg->dw1.d = abs(reg->dw1.d);
 865       return true;
 866    case BRW_REGISTER_TYPE_W:
 867       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 868       return true;
 869    case BRW_REGISTER_TYPE_F:
 870       reg->dw1.f = fabsf(reg->dw1.f);
 871       return true;
 872    case BRW_REGISTER_TYPE_VF:
 873       reg->dw1.ud &= ~0x80808080;
 874       return true;
 875    case BRW_REGISTER_TYPE_UB:
 876    case BRW_REGISTER_TYPE_B:
 877       unreachable("no UB/B immediates");
 878    case BRW_REGISTER_TYPE_UQ:
 879    case BRW_REGISTER_TYPE_UD:
 880    case BRW_REGISTER_TYPE_UW:
 881    case BRW_REGISTER_TYPE_UV:
 882       /* Presumably the absolute value modifier on an unsigned source is a
 883        * nop, but it would be nice to confirm.
 884        */
 885       assert(!"unimplemented: abs unsigned immediate");
 886    case BRW_REGISTER_TYPE_V:
 887       assert(!"unimplemented: abs V immediate");
 888    case BRW_REGISTER_TYPE_Q:
 889       assert(!"unimplemented: abs Q immediate");
 890    case BRW_REGISTER_TYPE_DF:
 891    case BRW_REGISTER_TYPE_HF:
 892       assert(!"unimplemented: abs DF/HF immediate");
 893    }
 894
 895    return false;
 896 }
 897
 898 backend_shader::backend_shader(const struct brw_compiler *compiler,
 899                                void *log_data,
 900                                void *mem_ctx,
 901                                struct gl_shader_program *shader_prog,
 902                                struct gl_program *prog,
 903                                struct brw_stage_prog_data *stage_prog_data,
 904                                gl_shader_stage stage)
 905    : compiler(compiler),
 906      log_data(log_data),
 907      devinfo(compiler->devinfo),
 908      shader(shader_prog ?
 909         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 910      shader_prog(shader_prog),
 911      prog(prog),
 912      stage_prog_data(stage_prog_data),
 913      mem_ctx(mem_ctx),
 914      cfg(NULL),
 915      stage(stage)
 916 {
 917    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 918    stage_name = _mesa_shader_stage_to_string(stage);
 919    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 920 }
 921
 922 bool
 923 backend_reg::is_zero() const
 924 {
 925    if (file != IMM)
 926       return false;
 927
 928    return fixed_hw_reg.dw1.d == 0;
 929 }
 930
 931 bool
 932 backend_reg::is_one() const
 933 {
 934    if (file != IMM)
 935       return false;
 936
 937    return type == BRW_REGISTER_TYPE_F
 938           ? fixed_hw_reg.dw1.f == 1.0
 939           : fixed_hw_reg.dw1.d == 1;
 940 }
 941
 942 bool
 943 backend_reg::is_negative_one() const
 944 {
 945    if (file != IMM)
 946       return false;
 947
 948    switch (type) {
 949    case BRW_REGISTER_TYPE_F:
 950       return fixed_hw_reg.dw1.f == -1.0;
 951    case BRW_REGISTER_TYPE_D:
 952       return fixed_hw_reg.dw1.d == -1;
 953    default:
 954       return false;
 955    }
 956 }
 957
 958 bool
 959 backend_reg::is_null() const
 960 {
 961    return file == HW_REG &&
 962           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 963           fixed_hw_reg.nr == BRW_ARF_NULL;
 964 }
 965
 966
 967 bool
 968 backend_reg::is_accumulator() const
 969 {
 970    return file == HW_REG &&
 971           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 972           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 973 }
 974
 975 bool
 976 backend_reg::in_range(const backend_reg &r, unsigned n) const
 977 {
 978    return (file == r.file &&
 979            reg == r.reg &&
 980            reg_offset >= r.reg_offset &&
 981            reg_offset < r.reg_offset + n);
 982 }
 983
 984 bool
 985 backend_instruction::is_commutative() const
 986 {
 987    switch (opcode) {
 988    case BRW_OPCODE_AND:
 989    case BRW_OPCODE_OR:
 990    case BRW_OPCODE_XOR:
 991    case BRW_OPCODE_ADD:
 992    case BRW_OPCODE_MUL:
 993       return true;
 994    case BRW_OPCODE_SEL:
 995       /* MIN and MAX are commutative. */
 996       if (conditional_mod == BRW_CONDITIONAL_GE ||
 997           conditional_mod == BRW_CONDITIONAL_L) {
 998          return true;
 999       }
1000       /* fallthrough */
1001    default:
1002       return false;
1003    }
1004 }
1005
1006 bool
1007 backend_instruction::is_3src() const
1008 {
1009    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
1010 }
1011
1012 bool
1013 backend_instruction::is_tex() const
1014 {
1015    return (opcode == SHADER_OPCODE_TEX ||
1016            opcode == FS_OPCODE_TXB ||
1017            opcode == SHADER_OPCODE_TXD ||
1018            opcode == SHADER_OPCODE_TXF ||
1019            opcode == SHADER_OPCODE_TXF_CMS ||
1020            opcode == SHADER_OPCODE_TXF_UMS ||
1021            opcode == SHADER_OPCODE_TXF_MCS ||
1022            opcode == SHADER_OPCODE_TXL ||
1023            opcode == SHADER_OPCODE_TXS ||
1024            opcode == SHADER_OPCODE_LOD ||
1025            opcode == SHADER_OPCODE_TG4 ||
1026            opcode == SHADER_OPCODE_TG4_OFFSET);
1027 }
1028
1029 bool
1030 backend_instruction::is_math() const
1031 {
1032    return (opcode == SHADER_OPCODE_RCP ||
1033            opcode == SHADER_OPCODE_RSQ ||
1034            opcode == SHADER_OPCODE_SQRT ||
1035            opcode == SHADER_OPCODE_EXP2 ||
1036            opcode == SHADER_OPCODE_LOG2 ||
1037            opcode == SHADER_OPCODE_SIN ||
1038            opcode == SHADER_OPCODE_COS ||
1039            opcode == SHADER_OPCODE_INT_QUOTIENT ||
1040            opcode == SHADER_OPCODE_INT_REMAINDER ||
1041            opcode == SHADER_OPCODE_POW);
1042 }
1043
1044 bool
1045 backend_instruction::is_control_flow() const
1046 {
1047    switch (opcode) {
1048    case BRW_OPCODE_DO:
1049    case BRW_OPCODE_WHILE:
1050    case BRW_OPCODE_IF:
1051    case BRW_OPCODE_ELSE:
1052    case BRW_OPCODE_ENDIF:
1053    case BRW_OPCODE_BREAK:
1054    case BRW_OPCODE_CONTINUE:
1055       return true;
1056    default:
1057       return false;
1058    }
1059 }
1060
1061 bool
1062 backend_instruction::can_do_source_mods() const
1063 {
1064    switch (opcode) {
1065    case BRW_OPCODE_ADDC:
1066    case BRW_OPCODE_BFE:
1067    case BRW_OPCODE_BFI1:
1068    case BRW_OPCODE_BFI2:
1069    case BRW_OPCODE_BFREV:
1070    case BRW_OPCODE_CBIT:
1071    case BRW_OPCODE_FBH:
1072    case BRW_OPCODE_FBL:
1073    case BRW_OPCODE_SUBB:
1074       return false;
1075    default:
1076       return true;
1077    }
1078 }
1079
1080 bool
1081 backend_instruction::can_do_saturate() const
1082 {
1083    switch (opcode) {
1084    case BRW_OPCODE_ADD:
1085    case BRW_OPCODE_ASR:
1086    case BRW_OPCODE_AVG:
1087    case BRW_OPCODE_DP2:
1088    case BRW_OPCODE_DP3:
1089    case BRW_OPCODE_DP4:
1090    case BRW_OPCODE_DPH:
1091    case BRW_OPCODE_F16TO32:
1092    case BRW_OPCODE_F32TO16:
1093    case BRW_OPCODE_LINE:
1094    case BRW_OPCODE_LRP:
1095    case BRW_OPCODE_MAC:
1096    case BRW_OPCODE_MAD:
1097    case BRW_OPCODE_MATH:
1098    case BRW_OPCODE_MOV:
1099    case BRW_OPCODE_MUL:
1100    case BRW_OPCODE_PLN:
1101    case BRW_OPCODE_RNDD:
1102    case BRW_OPCODE_RNDE:
1103    case BRW_OPCODE_RNDU:
1104    case BRW_OPCODE_RNDZ:
1105    case BRW_OPCODE_SEL:
1106    case BRW_OPCODE_SHL:
1107    case BRW_OPCODE_SHR:
1108    case FS_OPCODE_LINTERP:
1109    case SHADER_OPCODE_COS:
1110    case SHADER_OPCODE_EXP2:
1111    case SHADER_OPCODE_LOG2:
1112    case SHADER_OPCODE_POW:
1113    case SHADER_OPCODE_RCP:
1114    case SHADER_OPCODE_RSQ:
1115    case SHADER_OPCODE_SIN:
1116    case SHADER_OPCODE_SQRT:
1117       return true;
1118    default:
1119       return false;
1120    }
1121 }
1122
1123 bool
1124 backend_instruction::can_do_cmod() const
1125 {
1126    switch (opcode) {
1127    case BRW_OPCODE_ADD:
1128    case BRW_OPCODE_ADDC:
1129    case BRW_OPCODE_AND:
1130    case BRW_OPCODE_ASR:
1131    case BRW_OPCODE_AVG:
1132    case BRW_OPCODE_CMP:
1133    case BRW_OPCODE_CMPN:
1134    case BRW_OPCODE_DP2:
1135    case BRW_OPCODE_DP3:
1136    case BRW_OPCODE_DP4:
1137    case BRW_OPCODE_DPH:
1138    case BRW_OPCODE_F16TO32:
1139    case BRW_OPCODE_F32TO16:
1140    case BRW_OPCODE_FRC:
1141    case BRW_OPCODE_LINE:
1142    case BRW_OPCODE_LRP:
1143    case BRW_OPCODE_LZD:
1144    case BRW_OPCODE_MAC:
1145    case BRW_OPCODE_MACH:
1146    case BRW_OPCODE_MAD:
1147    case BRW_OPCODE_MOV:
1148    case BRW_OPCODE_MUL:
1149    case BRW_OPCODE_NOT:
1150    case BRW_OPCODE_OR:
1151    case BRW_OPCODE_PLN:
1152    case BRW_OPCODE_RNDD:
1153    case BRW_OPCODE_RNDE:
1154    case BRW_OPCODE_RNDU:
1155    case BRW_OPCODE_RNDZ:
1156    case BRW_OPCODE_SAD2:
1157    case BRW_OPCODE_SADA2:
1158    case BRW_OPCODE_SHL:
1159    case BRW_OPCODE_SHR:
1160    case BRW_OPCODE_SUBB:
1161    case BRW_OPCODE_XOR:
1162    case FS_OPCODE_CINTERP:
1163    case FS_OPCODE_LINTERP:
1164       return true;
1165    default:
1166       return false;
1167    }
1168 }
1169
1170 bool
1171 backend_instruction::reads_accumulator_implicitly() const
1172 {
1173    switch (opcode) {
1174    case BRW_OPCODE_MAC:
1175    case BRW_OPCODE_MACH:
1176    case BRW_OPCODE_SADA2:
1177       return true;
1178    default:
1179       return false;
1180    }
1181 }
1182
1183 bool
1184 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1185 {
1186    return writes_accumulator ||
1187           (devinfo->gen < 6 &&
1188            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1189             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1190              opcode != FS_OPCODE_CINTERP)));
1191 }
1192
1193 bool
1194 backend_instruction::has_side_effects() const
1195 {
1196    switch (opcode) {
1197    case SHADER_OPCODE_UNTYPED_ATOMIC:
1198    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1199    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1200    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1201    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1202    case SHADER_OPCODE_TYPED_ATOMIC:
1203    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1204    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1205    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1206    case SHADER_OPCODE_MEMORY_FENCE:
1207    case SHADER_OPCODE_URB_WRITE_SIMD8:
1208    case FS_OPCODE_FB_WRITE:
1209    case SHADER_OPCODE_BARRIER:
1210       return true;
1211    default:
1212       return false;
1213    }
1214 }
1215
1216 #ifndef NDEBUG
1217 static bool
1218 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1219 {
1220    bool found = false;
1221    foreach_inst_in_block (backend_instruction, i, block) {
1222       if (inst == i) {
1223          found = true;
1224       }
1225    }
1226    return found;
1227 }
1228 #endif
1229
1230 static void
1231 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1232 {
1233    for (bblock_t *block_iter = start_block->next();
1234         !block_iter->link.is_tail_sentinel();
1235         block_iter = block_iter->next()) {
1236       block_iter->start_ip += ip_adjustment;
1237       block_iter->end_ip += ip_adjustment;
1238    }
1239 }
1240
1241 void
1242 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1243 {
1244    if (!this->is_head_sentinel())
1245       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1246
1247    block->end_ip++;
1248
1249    adjust_later_block_ips(block, 1);
1250
1251    exec_node::insert_after(inst);
1252 }
1253
1254 void
1255 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1256 {
1257    if (!this->is_tail_sentinel())
1258       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1259
1260    block->end_ip++;
1261
1262    adjust_later_block_ips(block, 1);
1263
1264    exec_node::insert_before(inst);
1265 }
1266
1267 void
1268 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1269 {
1270    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1271
1272    unsigned num_inst = list->length();
1273
1274    block->end_ip += num_inst;
1275
1276    adjust_later_block_ips(block, num_inst);
1277
1278    exec_node::insert_before(list);
1279 }
1280
1281 void
1282 backend_instruction::remove(bblock_t *block)
1283 {
1284    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1285
1286    adjust_later_block_ips(block, -1);
1287
1288    if (block->start_ip == block->end_ip) {
1289       block->cfg->remove_block(block);
1290    } else {
1291       block->end_ip--;
1292    }
1293
1294    exec_node::remove();
1295 }
1296
1297 void
1298 backend_shader::dump_instructions()
1299 {
1300    dump_instructions(NULL);
1301 }
1302
1303 void
1304 backend_shader::dump_instructions(const char *name)
1305 {
1306    FILE *file = stderr;
1307    if (name && geteuid() != 0) {
1308       file = fopen(name, "w");
1309       if (!file)
1310          file = stderr;
1311    }
1312
1313    if (cfg) {
1314       int ip = 0;
1315       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1316          fprintf(file, "%4d: ", ip++);
1317          dump_instruction(inst, file);
1318       }
1319    } else {
1320       int ip = 0;
1321       foreach_in_list(backend_instruction, inst, &instructions) {
1322          fprintf(file, "%4d: ", ip++);
1323          dump_instruction(inst, file);
1324       }
1325    }
1326
1327    if (file != stderr) {
1328       fclose(file);
1329    }
1330 }
1331
1332 void
1333 backend_shader::calculate_cfg()
1334 {
1335    if (this->cfg)
1336       return;
1337    cfg = new(mem_ctx) cfg_t(&this->instructions);
1338 }
1339
1340 void
1341 backend_shader::invalidate_cfg()
1342 {
1343    ralloc_free(this->cfg);
1344    this->cfg = NULL;
1345 }
1346
1347 /**
1348  * Sets up the starting offsets for the groups of binding table entries
1349  * commong to all pipeline stages.
1350  *
1351  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1352  * unused but also make sure that addition of small offsets to them will
1353  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1354  */
1355 void
1356 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1357 {
1358    int num_textures = _mesa_fls(prog->SamplersUsed);
1359
1360    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1361    next_binding_table_offset += num_textures;
1362
1363    if (shader) {
1364       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1365       next_binding_table_offset += shader->base.NumUniformBlocks;
1366    } else {
1367       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1368    }
1369
1370    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1371       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1372       next_binding_table_offset++;
1373    } else {
1374       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1375    }
1376
1377    if (prog->UsesGather) {
1378       if (devinfo->gen >= 8) {
1379          stage_prog_data->binding_table.gather_texture_start =
1380             stage_prog_data->binding_table.texture_start;
1381       } else {
1382          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1383          next_binding_table_offset += num_textures;
1384       }
1385    } else {
1386       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1387    }
1388
1389    if (shader_prog && shader_prog->NumAtomicBuffers) {
1390       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1391       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1392    } else {
1393       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1394    }
1395
1396    if (shader && shader->base.NumImages) {
1397       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1398       next_binding_table_offset += shader->base.NumImages;
1399    } else {
1400       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1401    }
1402
1403    /* This may or may not be used depending on how the compile goes. */
1404    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1405    next_binding_table_offset++;
1406
1407    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1408
1409    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1410 }