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[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_cfg.h"
26 #include "brw_eu.h"
27 #include "brw_fs.h"
28 #include "brw_nir.h"
29 #include "brw_vec4_tes.h"
30 #include "main/shaderobj.h"
31 #include "main/uniforms.h"
32
33 extern "C" struct gl_shader *
34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
35 {
36 struct brw_shader *shader;
37
38 shader = rzalloc(NULL, struct brw_shader);
39 if (shader) {
40 shader->base.Type = type;
41 shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
42 shader->base.Name = name;
43 _mesa_init_shader(ctx, &shader->base);
44 }
45
46 return &shader->base;
47 }
48
49 extern "C" void
50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
51 unsigned surf_index)
52 {
53 assert(surf_index < BRW_MAX_SURFACES);
54
55 prog_data->binding_table.size_bytes =
56 MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
57 }
58
59 enum brw_reg_type
60 brw_type_for_base_type(const struct glsl_type *type)
61 {
62 switch (type->base_type) {
63 case GLSL_TYPE_FLOAT:
64 return BRW_REGISTER_TYPE_F;
65 case GLSL_TYPE_INT:
66 case GLSL_TYPE_BOOL:
67 case GLSL_TYPE_SUBROUTINE:
68 return BRW_REGISTER_TYPE_D;
69 case GLSL_TYPE_UINT:
70 return BRW_REGISTER_TYPE_UD;
71 case GLSL_TYPE_ARRAY:
72 return brw_type_for_base_type(type->fields.array);
73 case GLSL_TYPE_STRUCT:
74 case GLSL_TYPE_SAMPLER:
75 case GLSL_TYPE_ATOMIC_UINT:
76 /* These should be overridden with the type of the member when
77 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
78 * way to trip up if we don't.
79 */
80 return BRW_REGISTER_TYPE_UD;
81 case GLSL_TYPE_IMAGE:
82 return BRW_REGISTER_TYPE_UD;
83 case GLSL_TYPE_DOUBLE:
84 return BRW_REGISTER_TYPE_DF;
85 case GLSL_TYPE_VOID:
86 case GLSL_TYPE_ERROR:
87 case GLSL_TYPE_INTERFACE:
88 case GLSL_TYPE_FUNCTION:
89 unreachable("not reached");
90 }
91
92 return BRW_REGISTER_TYPE_F;
93 }
94
95 enum brw_conditional_mod
96 brw_conditional_for_comparison(unsigned int op)
97 {
98 switch (op) {
99 case ir_binop_less:
100 return BRW_CONDITIONAL_L;
101 case ir_binop_greater:
102 return BRW_CONDITIONAL_G;
103 case ir_binop_lequal:
104 return BRW_CONDITIONAL_LE;
105 case ir_binop_gequal:
106 return BRW_CONDITIONAL_GE;
107 case ir_binop_equal:
108 case ir_binop_all_equal: /* same as equal for scalars */
109 return BRW_CONDITIONAL_Z;
110 case ir_binop_nequal:
111 case ir_binop_any_nequal: /* same as nequal for scalars */
112 return BRW_CONDITIONAL_NZ;
113 default:
114 unreachable("not reached: bad operation for comparison");
115 }
116 }
117
118 uint32_t
119 brw_math_function(enum opcode op)
120 {
121 switch (op) {
122 case SHADER_OPCODE_RCP:
123 return BRW_MATH_FUNCTION_INV;
124 case SHADER_OPCODE_RSQ:
125 return BRW_MATH_FUNCTION_RSQ;
126 case SHADER_OPCODE_SQRT:
127 return BRW_MATH_FUNCTION_SQRT;
128 case SHADER_OPCODE_EXP2:
129 return BRW_MATH_FUNCTION_EXP;
130 case SHADER_OPCODE_LOG2:
131 return BRW_MATH_FUNCTION_LOG;
132 case SHADER_OPCODE_POW:
133 return BRW_MATH_FUNCTION_POW;
134 case SHADER_OPCODE_SIN:
135 return BRW_MATH_FUNCTION_SIN;
136 case SHADER_OPCODE_COS:
137 return BRW_MATH_FUNCTION_COS;
138 case SHADER_OPCODE_INT_QUOTIENT:
139 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
140 case SHADER_OPCODE_INT_REMAINDER:
141 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
142 default:
143 unreachable("not reached: unknown math function");
144 }
145 }
146
147 uint32_t
148 brw_texture_offset(int *offsets, unsigned num_components)
149 {
150 if (!offsets) return 0; /* nonconstant offset; caller will handle it. */
151
152 /* Combine all three offsets into a single unsigned dword:
153 *
154 * bits 11:8 - U Offset (X component)
155 * bits 7:4 - V Offset (Y component)
156 * bits 3:0 - R Offset (Z component)
157 */
158 unsigned offset_bits = 0;
159 for (unsigned i = 0; i < num_components; i++) {
160 const unsigned shift = 4 * (2 - i);
161 offset_bits |= (offsets[i] << shift) & (0xF << shift);
162 }
163 return offset_bits;
164 }
165
166 const char *
167 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
168 {
169 switch (op) {
170 case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
171 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
172 * start of a loop in the IR.
173 */
174 if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
175 return "do";
176
177 assert(brw_opcode_desc(devinfo, op)->name);
178 return brw_opcode_desc(devinfo, op)->name;
179 case FS_OPCODE_FB_WRITE:
180 return "fb_write";
181 case FS_OPCODE_FB_WRITE_LOGICAL:
182 return "fb_write_logical";
183 case FS_OPCODE_PACK_STENCIL_REF:
184 return "pack_stencil_ref";
185 case FS_OPCODE_REP_FB_WRITE:
186 return "rep_fb_write";
187
188 case SHADER_OPCODE_RCP:
189 return "rcp";
190 case SHADER_OPCODE_RSQ:
191 return "rsq";
192 case SHADER_OPCODE_SQRT:
193 return "sqrt";
194 case SHADER_OPCODE_EXP2:
195 return "exp2";
196 case SHADER_OPCODE_LOG2:
197 return "log2";
198 case SHADER_OPCODE_POW:
199 return "pow";
200 case SHADER_OPCODE_INT_QUOTIENT:
201 return "int_quot";
202 case SHADER_OPCODE_INT_REMAINDER:
203 return "int_rem";
204 case SHADER_OPCODE_SIN:
205 return "sin";
206 case SHADER_OPCODE_COS:
207 return "cos";
208
209 case SHADER_OPCODE_TEX:
210 return "tex";
211 case SHADER_OPCODE_TEX_LOGICAL:
212 return "tex_logical";
213 case SHADER_OPCODE_TXD:
214 return "txd";
215 case SHADER_OPCODE_TXD_LOGICAL:
216 return "txd_logical";
217 case SHADER_OPCODE_TXF:
218 return "txf";
219 case SHADER_OPCODE_TXF_LOGICAL:
220 return "txf_logical";
221 case SHADER_OPCODE_TXF_LZ:
222 return "txf_lz";
223 case SHADER_OPCODE_TXL:
224 return "txl";
225 case SHADER_OPCODE_TXL_LOGICAL:
226 return "txl_logical";
227 case SHADER_OPCODE_TXL_LZ:
228 return "txl_lz";
229 case SHADER_OPCODE_TXS:
230 return "txs";
231 case SHADER_OPCODE_TXS_LOGICAL:
232 return "txs_logical";
233 case FS_OPCODE_TXB:
234 return "txb";
235 case FS_OPCODE_TXB_LOGICAL:
236 return "txb_logical";
237 case SHADER_OPCODE_TXF_CMS:
238 return "txf_cms";
239 case SHADER_OPCODE_TXF_CMS_LOGICAL:
240 return "txf_cms_logical";
241 case SHADER_OPCODE_TXF_CMS_W:
242 return "txf_cms_w";
243 case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
244 return "txf_cms_w_logical";
245 case SHADER_OPCODE_TXF_UMS:
246 return "txf_ums";
247 case SHADER_OPCODE_TXF_UMS_LOGICAL:
248 return "txf_ums_logical";
249 case SHADER_OPCODE_TXF_MCS:
250 return "txf_mcs";
251 case SHADER_OPCODE_TXF_MCS_LOGICAL:
252 return "txf_mcs_logical";
253 case SHADER_OPCODE_LOD:
254 return "lod";
255 case SHADER_OPCODE_LOD_LOGICAL:
256 return "lod_logical";
257 case SHADER_OPCODE_TG4:
258 return "tg4";
259 case SHADER_OPCODE_TG4_LOGICAL:
260 return "tg4_logical";
261 case SHADER_OPCODE_TG4_OFFSET:
262 return "tg4_offset";
263 case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
264 return "tg4_offset_logical";
265 case SHADER_OPCODE_SAMPLEINFO:
266 return "sampleinfo";
267
268 case SHADER_OPCODE_SHADER_TIME_ADD:
269 return "shader_time_add";
270
271 case SHADER_OPCODE_UNTYPED_ATOMIC:
272 return "untyped_atomic";
273 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
274 return "untyped_atomic_logical";
275 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
276 return "untyped_surface_read";
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
278 return "untyped_surface_read_logical";
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
280 return "untyped_surface_write";
281 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
282 return "untyped_surface_write_logical";
283 case SHADER_OPCODE_TYPED_ATOMIC:
284 return "typed_atomic";
285 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
286 return "typed_atomic_logical";
287 case SHADER_OPCODE_TYPED_SURFACE_READ:
288 return "typed_surface_read";
289 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
290 return "typed_surface_read_logical";
291 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
292 return "typed_surface_write";
293 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
294 return "typed_surface_write_logical";
295 case SHADER_OPCODE_MEMORY_FENCE:
296 return "memory_fence";
297
298 case SHADER_OPCODE_LOAD_PAYLOAD:
299 return "load_payload";
300 case FS_OPCODE_PACK:
301 return "pack";
302
303 case SHADER_OPCODE_GEN4_SCRATCH_READ:
304 return "gen4_scratch_read";
305 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
306 return "gen4_scratch_write";
307 case SHADER_OPCODE_GEN7_SCRATCH_READ:
308 return "gen7_scratch_read";
309 case SHADER_OPCODE_URB_WRITE_SIMD8:
310 return "gen8_urb_write_simd8";
311 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
312 return "gen8_urb_write_simd8_per_slot";
313 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
314 return "gen8_urb_write_simd8_masked";
315 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
316 return "gen8_urb_write_simd8_masked_per_slot";
317 case SHADER_OPCODE_URB_READ_SIMD8:
318 return "urb_read_simd8";
319 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
320 return "urb_read_simd8_per_slot";
321
322 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
323 return "find_live_channel";
324 case SHADER_OPCODE_BROADCAST:
325 return "broadcast";
326
327 case SHADER_OPCODE_EXTRACT_BYTE:
328 return "extract_byte";
329 case SHADER_OPCODE_EXTRACT_WORD:
330 return "extract_word";
331 case VEC4_OPCODE_MOV_BYTES:
332 return "mov_bytes";
333 case VEC4_OPCODE_PACK_BYTES:
334 return "pack_bytes";
335 case VEC4_OPCODE_UNPACK_UNIFORM:
336 return "unpack_uniform";
337
338 case FS_OPCODE_DDX_COARSE:
339 return "ddx_coarse";
340 case FS_OPCODE_DDX_FINE:
341 return "ddx_fine";
342 case FS_OPCODE_DDY_COARSE:
343 return "ddy_coarse";
344 case FS_OPCODE_DDY_FINE:
345 return "ddy_fine";
346
347 case FS_OPCODE_CINTERP:
348 return "cinterp";
349 case FS_OPCODE_LINTERP:
350 return "linterp";
351
352 case FS_OPCODE_PIXEL_X:
353 return "pixel_x";
354 case FS_OPCODE_PIXEL_Y:
355 return "pixel_y";
356
357 case FS_OPCODE_GET_BUFFER_SIZE:
358 return "fs_get_buffer_size";
359
360 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
361 return "uniform_pull_const";
362 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
363 return "uniform_pull_const_gen7";
364 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
365 return "varying_pull_const";
366 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
367 return "varying_pull_const_gen7";
368
369 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
370 return "mov_dispatch_to_flags";
371 case FS_OPCODE_DISCARD_JUMP:
372 return "discard_jump";
373
374 case FS_OPCODE_SET_SAMPLE_ID:
375 return "set_sample_id";
376 case FS_OPCODE_SET_SIMD4X2_OFFSET:
377 return "set_simd4x2_offset";
378
379 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
380 return "pack_half_2x16_split";
381 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
382 return "unpack_half_2x16_split_x";
383 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
384 return "unpack_half_2x16_split_y";
385
386 case FS_OPCODE_PLACEHOLDER_HALT:
387 return "placeholder_halt";
388
389 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
390 return "interp_centroid";
391 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
392 return "interp_sample";
393 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
394 return "interp_shared_offset";
395 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
396 return "interp_per_slot_offset";
397
398 case VS_OPCODE_URB_WRITE:
399 return "vs_urb_write";
400 case VS_OPCODE_PULL_CONSTANT_LOAD:
401 return "pull_constant_load";
402 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
403 return "pull_constant_load_gen7";
404
405 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
406 return "set_simd4x2_header_gen9";
407
408 case VS_OPCODE_GET_BUFFER_SIZE:
409 return "vs_get_buffer_size";
410
411 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
412 return "unpack_flags_simd4x2";
413
414 case GS_OPCODE_URB_WRITE:
415 return "gs_urb_write";
416 case GS_OPCODE_URB_WRITE_ALLOCATE:
417 return "gs_urb_write_allocate";
418 case GS_OPCODE_THREAD_END:
419 return "gs_thread_end";
420 case GS_OPCODE_SET_WRITE_OFFSET:
421 return "set_write_offset";
422 case GS_OPCODE_SET_VERTEX_COUNT:
423 return "set_vertex_count";
424 case GS_OPCODE_SET_DWORD_2:
425 return "set_dword_2";
426 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
427 return "prepare_channel_masks";
428 case GS_OPCODE_SET_CHANNEL_MASKS:
429 return "set_channel_masks";
430 case GS_OPCODE_GET_INSTANCE_ID:
431 return "get_instance_id";
432 case GS_OPCODE_FF_SYNC:
433 return "ff_sync";
434 case GS_OPCODE_SET_PRIMITIVE_ID:
435 return "set_primitive_id";
436 case GS_OPCODE_SVB_WRITE:
437 return "gs_svb_write";
438 case GS_OPCODE_SVB_SET_DST_INDEX:
439 return "gs_svb_set_dst_index";
440 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
441 return "gs_ff_sync_set_primitives";
442 case CS_OPCODE_CS_TERMINATE:
443 return "cs_terminate";
444 case SHADER_OPCODE_BARRIER:
445 return "barrier";
446 case SHADER_OPCODE_MULH:
447 return "mulh";
448 case SHADER_OPCODE_MOV_INDIRECT:
449 return "mov_indirect";
450
451 case VEC4_OPCODE_URB_READ:
452 return "urb_read";
453 case TCS_OPCODE_GET_INSTANCE_ID:
454 return "tcs_get_instance_id";
455 case TCS_OPCODE_URB_WRITE:
456 return "tcs_urb_write";
457 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
458 return "tcs_set_input_urb_offsets";
459 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
460 return "tcs_set_output_urb_offsets";
461 case TCS_OPCODE_GET_PRIMITIVE_ID:
462 return "tcs_get_primitive_id";
463 case TCS_OPCODE_CREATE_BARRIER_HEADER:
464 return "tcs_create_barrier_header";
465 case TCS_OPCODE_SRC0_010_IS_ZERO:
466 return "tcs_src0<0,1,0>_is_zero";
467 case TCS_OPCODE_RELEASE_INPUT:
468 return "tcs_release_input";
469 case TCS_OPCODE_THREAD_END:
470 return "tcs_thread_end";
471 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
472 return "tes_create_input_read_header";
473 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
474 return "tes_add_indirect_urb_offset";
475 case TES_OPCODE_GET_PRIMITIVE_ID:
476 return "tes_get_primitive_id";
477 }
478
479 unreachable("not reached");
480 }
481
482 bool
483 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
484 {
485 union {
486 unsigned ud;
487 int d;
488 float f;
489 double df;
490 } imm, sat_imm = { 0 };
491
492 const unsigned size = type_sz(type);
493
494 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
495 * irrelevant, so just check the size of the type and copy from/to an
496 * appropriately sized field.
497 */
498 if (size < 8)
499 imm.ud = reg->ud;
500 else
501 imm.df = reg->df;
502
503 switch (type) {
504 case BRW_REGISTER_TYPE_UD:
505 case BRW_REGISTER_TYPE_D:
506 case BRW_REGISTER_TYPE_UW:
507 case BRW_REGISTER_TYPE_W:
508 case BRW_REGISTER_TYPE_UQ:
509 case BRW_REGISTER_TYPE_Q:
510 /* Nothing to do. */
511 return false;
512 case BRW_REGISTER_TYPE_F:
513 sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
514 break;
515 case BRW_REGISTER_TYPE_DF:
516 sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
517 break;
518 case BRW_REGISTER_TYPE_UB:
519 case BRW_REGISTER_TYPE_B:
520 unreachable("no UB/B immediates");
521 case BRW_REGISTER_TYPE_V:
522 case BRW_REGISTER_TYPE_UV:
523 case BRW_REGISTER_TYPE_VF:
524 unreachable("unimplemented: saturate vector immediate");
525 case BRW_REGISTER_TYPE_HF:
526 unreachable("unimplemented: saturate HF immediate");
527 }
528
529 if (size < 8) {
530 if (imm.ud != sat_imm.ud) {
531 reg->ud = sat_imm.ud;
532 return true;
533 }
534 } else {
535 if (imm.df != sat_imm.df) {
536 reg->df = sat_imm.df;
537 return true;
538 }
539 }
540 return false;
541 }
542
543 bool
544 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
545 {
546 switch (type) {
547 case BRW_REGISTER_TYPE_D:
548 case BRW_REGISTER_TYPE_UD:
549 reg->d = -reg->d;
550 return true;
551 case BRW_REGISTER_TYPE_W:
552 case BRW_REGISTER_TYPE_UW:
553 reg->d = -(int16_t)reg->ud;
554 return true;
555 case BRW_REGISTER_TYPE_F:
556 reg->f = -reg->f;
557 return true;
558 case BRW_REGISTER_TYPE_VF:
559 reg->ud ^= 0x80808080;
560 return true;
561 case BRW_REGISTER_TYPE_DF:
562 reg->df = -reg->df;
563 return true;
564 case BRW_REGISTER_TYPE_UB:
565 case BRW_REGISTER_TYPE_B:
566 unreachable("no UB/B immediates");
567 case BRW_REGISTER_TYPE_UV:
568 case BRW_REGISTER_TYPE_V:
569 assert(!"unimplemented: negate UV/V immediate");
570 case BRW_REGISTER_TYPE_UQ:
571 case BRW_REGISTER_TYPE_Q:
572 assert(!"unimplemented: negate UQ/Q immediate");
573 case BRW_REGISTER_TYPE_HF:
574 assert(!"unimplemented: negate HF immediate");
575 }
576
577 return false;
578 }
579
580 bool
581 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
582 {
583 switch (type) {
584 case BRW_REGISTER_TYPE_D:
585 reg->d = abs(reg->d);
586 return true;
587 case BRW_REGISTER_TYPE_W:
588 reg->d = abs((int16_t)reg->ud);
589 return true;
590 case BRW_REGISTER_TYPE_F:
591 reg->f = fabsf(reg->f);
592 return true;
593 case BRW_REGISTER_TYPE_DF:
594 reg->df = fabs(reg->df);
595 return true;
596 case BRW_REGISTER_TYPE_VF:
597 reg->ud &= ~0x80808080;
598 return true;
599 case BRW_REGISTER_TYPE_UB:
600 case BRW_REGISTER_TYPE_B:
601 unreachable("no UB/B immediates");
602 case BRW_REGISTER_TYPE_UQ:
603 case BRW_REGISTER_TYPE_UD:
604 case BRW_REGISTER_TYPE_UW:
605 case BRW_REGISTER_TYPE_UV:
606 /* Presumably the absolute value modifier on an unsigned source is a
607 * nop, but it would be nice to confirm.
608 */
609 assert(!"unimplemented: abs unsigned immediate");
610 case BRW_REGISTER_TYPE_V:
611 assert(!"unimplemented: abs V immediate");
612 case BRW_REGISTER_TYPE_Q:
613 assert(!"unimplemented: abs Q immediate");
614 case BRW_REGISTER_TYPE_HF:
615 assert(!"unimplemented: abs HF immediate");
616 }
617
618 return false;
619 }
620
621 unsigned
622 tesslevel_outer_components(GLenum tes_primitive_mode)
623 {
624 switch (tes_primitive_mode) {
625 case GL_QUADS:
626 return 4;
627 case GL_TRIANGLES:
628 return 3;
629 case GL_ISOLINES:
630 return 2;
631 default:
632 unreachable("Bogus tessellation domain");
633 }
634 return 0;
635 }
636
637 unsigned
638 tesslevel_inner_components(GLenum tes_primitive_mode)
639 {
640 switch (tes_primitive_mode) {
641 case GL_QUADS:
642 return 2;
643 case GL_TRIANGLES:
644 return 1;
645 case GL_ISOLINES:
646 return 0;
647 default:
648 unreachable("Bogus tessellation domain");
649 }
650 return 0;
651 }
652
653 /**
654 * Given a normal .xyzw writemask, convert it to a writemask for a vector
655 * that's stored backwards, i.e. .wzyx.
656 */
657 unsigned
658 writemask_for_backwards_vector(unsigned mask)
659 {
660 unsigned new_mask = 0;
661
662 for (int i = 0; i < 4; i++)
663 new_mask |= ((mask >> i) & 1) << (3 - i);
664
665 return new_mask;
666 }
667
668 backend_shader::backend_shader(const struct brw_compiler *compiler,
669 void *log_data,
670 void *mem_ctx,
671 const nir_shader *shader,
672 struct brw_stage_prog_data *stage_prog_data)
673 : compiler(compiler),
674 log_data(log_data),
675 devinfo(compiler->devinfo),
676 nir(shader),
677 stage_prog_data(stage_prog_data),
678 mem_ctx(mem_ctx),
679 cfg(NULL),
680 stage(shader->stage)
681 {
682 debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
683 stage_name = _mesa_shader_stage_to_string(stage);
684 stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
685 is_passthrough_shader =
686 nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
687 }
688
689 bool
690 backend_reg::equals(const backend_reg &r) const
691 {
692 return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
693 }
694
695 bool
696 backend_reg::is_zero() const
697 {
698 if (file != IMM)
699 return false;
700
701 switch (type) {
702 case BRW_REGISTER_TYPE_F:
703 return f == 0;
704 case BRW_REGISTER_TYPE_DF:
705 return df == 0;
706 case BRW_REGISTER_TYPE_D:
707 case BRW_REGISTER_TYPE_UD:
708 return d == 0;
709 default:
710 return false;
711 }
712 }
713
714 bool
715 backend_reg::is_one() const
716 {
717 if (file != IMM)
718 return false;
719
720 switch (type) {
721 case BRW_REGISTER_TYPE_F:
722 return f == 1.0f;
723 case BRW_REGISTER_TYPE_DF:
724 return df == 1.0;
725 case BRW_REGISTER_TYPE_D:
726 case BRW_REGISTER_TYPE_UD:
727 return d == 1;
728 default:
729 return false;
730 }
731 }
732
733 bool
734 backend_reg::is_negative_one() const
735 {
736 if (file != IMM)
737 return false;
738
739 switch (type) {
740 case BRW_REGISTER_TYPE_F:
741 return f == -1.0;
742 case BRW_REGISTER_TYPE_DF:
743 return df == -1.0;
744 case BRW_REGISTER_TYPE_D:
745 return d == -1;
746 default:
747 return false;
748 }
749 }
750
751 bool
752 backend_reg::is_null() const
753 {
754 return file == ARF && nr == BRW_ARF_NULL;
755 }
756
757
758 bool
759 backend_reg::is_accumulator() const
760 {
761 return file == ARF && nr == BRW_ARF_ACCUMULATOR;
762 }
763
764 bool
765 backend_reg::in_range(const backend_reg &r, unsigned n) const
766 {
767 return (file == r.file &&
768 nr == r.nr &&
769 reg_offset >= r.reg_offset &&
770 reg_offset < r.reg_offset + n);
771 }
772
773 bool
774 backend_instruction::is_commutative() const
775 {
776 switch (opcode) {
777 case BRW_OPCODE_AND:
778 case BRW_OPCODE_OR:
779 case BRW_OPCODE_XOR:
780 case BRW_OPCODE_ADD:
781 case BRW_OPCODE_MUL:
782 case SHADER_OPCODE_MULH:
783 return true;
784 case BRW_OPCODE_SEL:
785 /* MIN and MAX are commutative. */
786 if (conditional_mod == BRW_CONDITIONAL_GE ||
787 conditional_mod == BRW_CONDITIONAL_L) {
788 return true;
789 }
790 /* fallthrough */
791 default:
792 return false;
793 }
794 }
795
796 bool
797 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
798 {
799 return ::is_3src(devinfo, opcode);
800 }
801
802 bool
803 backend_instruction::is_tex() const
804 {
805 return (opcode == SHADER_OPCODE_TEX ||
806 opcode == FS_OPCODE_TXB ||
807 opcode == SHADER_OPCODE_TXD ||
808 opcode == SHADER_OPCODE_TXF ||
809 opcode == SHADER_OPCODE_TXF_LZ ||
810 opcode == SHADER_OPCODE_TXF_CMS ||
811 opcode == SHADER_OPCODE_TXF_CMS_W ||
812 opcode == SHADER_OPCODE_TXF_UMS ||
813 opcode == SHADER_OPCODE_TXF_MCS ||
814 opcode == SHADER_OPCODE_TXL ||
815 opcode == SHADER_OPCODE_TXL_LZ ||
816 opcode == SHADER_OPCODE_TXS ||
817 opcode == SHADER_OPCODE_LOD ||
818 opcode == SHADER_OPCODE_TG4 ||
819 opcode == SHADER_OPCODE_TG4_OFFSET ||
820 opcode == SHADER_OPCODE_SAMPLEINFO);
821 }
822
823 bool
824 backend_instruction::is_math() const
825 {
826 return (opcode == SHADER_OPCODE_RCP ||
827 opcode == SHADER_OPCODE_RSQ ||
828 opcode == SHADER_OPCODE_SQRT ||
829 opcode == SHADER_OPCODE_EXP2 ||
830 opcode == SHADER_OPCODE_LOG2 ||
831 opcode == SHADER_OPCODE_SIN ||
832 opcode == SHADER_OPCODE_COS ||
833 opcode == SHADER_OPCODE_INT_QUOTIENT ||
834 opcode == SHADER_OPCODE_INT_REMAINDER ||
835 opcode == SHADER_OPCODE_POW);
836 }
837
838 bool
839 backend_instruction::is_control_flow() const
840 {
841 switch (opcode) {
842 case BRW_OPCODE_DO:
843 case BRW_OPCODE_WHILE:
844 case BRW_OPCODE_IF:
845 case BRW_OPCODE_ELSE:
846 case BRW_OPCODE_ENDIF:
847 case BRW_OPCODE_BREAK:
848 case BRW_OPCODE_CONTINUE:
849 return true;
850 default:
851 return false;
852 }
853 }
854
855 bool
856 backend_instruction::can_do_source_mods() const
857 {
858 switch (opcode) {
859 case BRW_OPCODE_ADDC:
860 case BRW_OPCODE_BFE:
861 case BRW_OPCODE_BFI1:
862 case BRW_OPCODE_BFI2:
863 case BRW_OPCODE_BFREV:
864 case BRW_OPCODE_CBIT:
865 case BRW_OPCODE_FBH:
866 case BRW_OPCODE_FBL:
867 case BRW_OPCODE_SUBB:
868 return false;
869 default:
870 return true;
871 }
872 }
873
874 bool
875 backend_instruction::can_do_saturate() const
876 {
877 switch (opcode) {
878 case BRW_OPCODE_ADD:
879 case BRW_OPCODE_ASR:
880 case BRW_OPCODE_AVG:
881 case BRW_OPCODE_DP2:
882 case BRW_OPCODE_DP3:
883 case BRW_OPCODE_DP4:
884 case BRW_OPCODE_DPH:
885 case BRW_OPCODE_F16TO32:
886 case BRW_OPCODE_F32TO16:
887 case BRW_OPCODE_LINE:
888 case BRW_OPCODE_LRP:
889 case BRW_OPCODE_MAC:
890 case BRW_OPCODE_MAD:
891 case BRW_OPCODE_MATH:
892 case BRW_OPCODE_MOV:
893 case BRW_OPCODE_MUL:
894 case SHADER_OPCODE_MULH:
895 case BRW_OPCODE_PLN:
896 case BRW_OPCODE_RNDD:
897 case BRW_OPCODE_RNDE:
898 case BRW_OPCODE_RNDU:
899 case BRW_OPCODE_RNDZ:
900 case BRW_OPCODE_SEL:
901 case BRW_OPCODE_SHL:
902 case BRW_OPCODE_SHR:
903 case FS_OPCODE_LINTERP:
904 case SHADER_OPCODE_COS:
905 case SHADER_OPCODE_EXP2:
906 case SHADER_OPCODE_LOG2:
907 case SHADER_OPCODE_POW:
908 case SHADER_OPCODE_RCP:
909 case SHADER_OPCODE_RSQ:
910 case SHADER_OPCODE_SIN:
911 case SHADER_OPCODE_SQRT:
912 return true;
913 default:
914 return false;
915 }
916 }
917
918 bool
919 backend_instruction::can_do_cmod() const
920 {
921 switch (opcode) {
922 case BRW_OPCODE_ADD:
923 case BRW_OPCODE_ADDC:
924 case BRW_OPCODE_AND:
925 case BRW_OPCODE_ASR:
926 case BRW_OPCODE_AVG:
927 case BRW_OPCODE_CMP:
928 case BRW_OPCODE_CMPN:
929 case BRW_OPCODE_DP2:
930 case BRW_OPCODE_DP3:
931 case BRW_OPCODE_DP4:
932 case BRW_OPCODE_DPH:
933 case BRW_OPCODE_F16TO32:
934 case BRW_OPCODE_F32TO16:
935 case BRW_OPCODE_FRC:
936 case BRW_OPCODE_LINE:
937 case BRW_OPCODE_LRP:
938 case BRW_OPCODE_LZD:
939 case BRW_OPCODE_MAC:
940 case BRW_OPCODE_MACH:
941 case BRW_OPCODE_MAD:
942 case BRW_OPCODE_MOV:
943 case BRW_OPCODE_MUL:
944 case BRW_OPCODE_NOT:
945 case BRW_OPCODE_OR:
946 case BRW_OPCODE_PLN:
947 case BRW_OPCODE_RNDD:
948 case BRW_OPCODE_RNDE:
949 case BRW_OPCODE_RNDU:
950 case BRW_OPCODE_RNDZ:
951 case BRW_OPCODE_SAD2:
952 case BRW_OPCODE_SADA2:
953 case BRW_OPCODE_SHL:
954 case BRW_OPCODE_SHR:
955 case BRW_OPCODE_SUBB:
956 case BRW_OPCODE_XOR:
957 case FS_OPCODE_CINTERP:
958 case FS_OPCODE_LINTERP:
959 return true;
960 default:
961 return false;
962 }
963 }
964
965 bool
966 backend_instruction::reads_accumulator_implicitly() const
967 {
968 switch (opcode) {
969 case BRW_OPCODE_MAC:
970 case BRW_OPCODE_MACH:
971 case BRW_OPCODE_SADA2:
972 return true;
973 default:
974 return false;
975 }
976 }
977
978 bool
979 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
980 {
981 return writes_accumulator ||
982 (devinfo->gen < 6 &&
983 ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
984 (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
985 opcode != FS_OPCODE_CINTERP)));
986 }
987
988 bool
989 backend_instruction::has_side_effects() const
990 {
991 switch (opcode) {
992 case SHADER_OPCODE_UNTYPED_ATOMIC:
993 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
994 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
995 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
996 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
997 case SHADER_OPCODE_TYPED_ATOMIC:
998 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
999 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1000 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1001 case SHADER_OPCODE_MEMORY_FENCE:
1002 case SHADER_OPCODE_URB_WRITE_SIMD8:
1003 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1004 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1005 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1006 case FS_OPCODE_FB_WRITE:
1007 case SHADER_OPCODE_BARRIER:
1008 case TCS_OPCODE_URB_WRITE:
1009 case TCS_OPCODE_RELEASE_INPUT:
1010 return true;
1011 default:
1012 return false;
1013 }
1014 }
1015
1016 bool
1017 backend_instruction::is_volatile() const
1018 {
1019 switch (opcode) {
1020 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1021 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1022 case SHADER_OPCODE_TYPED_SURFACE_READ:
1023 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1024 case SHADER_OPCODE_URB_READ_SIMD8:
1025 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1026 case VEC4_OPCODE_URB_READ:
1027 return true;
1028 default:
1029 return false;
1030 }
1031 }
1032
1033 #ifndef NDEBUG
1034 static bool
1035 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1036 {
1037 bool found = false;
1038 foreach_inst_in_block (backend_instruction, i, block) {
1039 if (inst == i) {
1040 found = true;
1041 }
1042 }
1043 return found;
1044 }
1045 #endif
1046
1047 static void
1048 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1049 {
1050 for (bblock_t *block_iter = start_block->next();
1051 block_iter;
1052 block_iter = block_iter->next()) {
1053 block_iter->start_ip += ip_adjustment;
1054 block_iter->end_ip += ip_adjustment;
1055 }
1056 }
1057
1058 void
1059 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1060 {
1061 assert(this != inst);
1062
1063 if (!this->is_head_sentinel())
1064 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1065
1066 block->end_ip++;
1067
1068 adjust_later_block_ips(block, 1);
1069
1070 exec_node::insert_after(inst);
1071 }
1072
1073 void
1074 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1075 {
1076 assert(this != inst);
1077
1078 if (!this->is_tail_sentinel())
1079 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1080
1081 block->end_ip++;
1082
1083 adjust_later_block_ips(block, 1);
1084
1085 exec_node::insert_before(inst);
1086 }
1087
1088 void
1089 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1090 {
1091 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1092
1093 unsigned num_inst = list->length();
1094
1095 block->end_ip += num_inst;
1096
1097 adjust_later_block_ips(block, num_inst);
1098
1099 exec_node::insert_before(list);
1100 }
1101
1102 void
1103 backend_instruction::remove(bblock_t *block)
1104 {
1105 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1106
1107 adjust_later_block_ips(block, -1);
1108
1109 if (block->start_ip == block->end_ip) {
1110 block->cfg->remove_block(block);
1111 } else {
1112 block->end_ip--;
1113 }
1114
1115 exec_node::remove();
1116 }
1117
1118 void
1119 backend_shader::dump_instructions()
1120 {
1121 dump_instructions(NULL);
1122 }
1123
1124 void
1125 backend_shader::dump_instructions(const char *name)
1126 {
1127 FILE *file = stderr;
1128 if (name && geteuid() != 0) {
1129 file = fopen(name, "w");
1130 if (!file)
1131 file = stderr;
1132 }
1133
1134 if (cfg) {
1135 int ip = 0;
1136 foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1137 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1138 fprintf(file, "%4d: ", ip++);
1139 dump_instruction(inst, file);
1140 }
1141 } else {
1142 int ip = 0;
1143 foreach_in_list(backend_instruction, inst, &instructions) {
1144 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1145 fprintf(file, "%4d: ", ip++);
1146 dump_instruction(inst, file);
1147 }
1148 }
1149
1150 if (file != stderr) {
1151 fclose(file);
1152 }
1153 }
1154
1155 void
1156 backend_shader::calculate_cfg()
1157 {
1158 if (this->cfg)
1159 return;
1160 cfg = new(mem_ctx) cfg_t(&this->instructions);
1161 }
1162
1163 /**
1164 * Sets up the starting offsets for the groups of binding table entries
1165 * commong to all pipeline stages.
1166 *
1167 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1168 * unused but also make sure that addition of small offsets to them will
1169 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1170 */
1171 void
1172 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1173 const struct brw_device_info *devinfo,
1174 const struct gl_shader_program *shader_prog,
1175 const struct gl_program *prog,
1176 struct brw_stage_prog_data *stage_prog_data,
1177 uint32_t next_binding_table_offset)
1178 {
1179 const struct gl_shader *shader = NULL;
1180 int num_textures = _mesa_fls(prog->SamplersUsed);
1181
1182 if (shader_prog)
1183 shader = shader_prog->_LinkedShaders[stage];
1184
1185 stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1186 next_binding_table_offset += num_textures;
1187
1188 if (shader) {
1189 assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1190 stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1191 next_binding_table_offset += shader->NumUniformBlocks;
1192
1193 assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1194 stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1195 next_binding_table_offset += shader->NumShaderStorageBlocks;
1196 } else {
1197 stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1198 stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1199 }
1200
1201 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1202 stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1203 next_binding_table_offset++;
1204 } else {
1205 stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1206 }
1207
1208 if (prog->UsesGather) {
1209 if (devinfo->gen >= 8) {
1210 stage_prog_data->binding_table.gather_texture_start =
1211 stage_prog_data->binding_table.texture_start;
1212 } else {
1213 stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1214 next_binding_table_offset += num_textures;
1215 }
1216 } else {
1217 stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1218 }
1219
1220 if (shader && shader->NumAtomicBuffers) {
1221 stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1222 next_binding_table_offset += shader->NumAtomicBuffers;
1223 } else {
1224 stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1225 }
1226
1227 if (shader && shader->NumImages) {
1228 stage_prog_data->binding_table.image_start = next_binding_table_offset;
1229 next_binding_table_offset += shader->NumImages;
1230 } else {
1231 stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1232 }
1233
1234 /* This may or may not be used depending on how the compile goes. */
1235 stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1236 next_binding_table_offset++;
1237
1238 assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1239
1240 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1241 }
1242
1243 static void
1244 setup_vec4_uniform_value(const gl_constant_value **params,
1245 const gl_constant_value *values,
1246 unsigned n)
1247 {
1248 static const gl_constant_value zero = { 0 };
1249
1250 for (unsigned i = 0; i < n; ++i)
1251 params[i] = &values[i];
1252
1253 for (unsigned i = n; i < 4; ++i)
1254 params[i] = &zero;
1255 }
1256
1257 void
1258 brw_setup_image_uniform_values(gl_shader_stage stage,
1259 struct brw_stage_prog_data *stage_prog_data,
1260 unsigned param_start_index,
1261 const gl_uniform_storage *storage)
1262 {
1263 const gl_constant_value **param =
1264 &stage_prog_data->param[param_start_index];
1265
1266 for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1267 const unsigned image_idx = storage->opaque[stage].index + i;
1268 const brw_image_param *image_param =
1269 &stage_prog_data->image_param[image_idx];
1270
1271 /* Upload the brw_image_param structure. The order is expected to match
1272 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1273 */
1274 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1275 (const gl_constant_value *)&image_param->surface_idx, 1);
1276 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1277 (const gl_constant_value *)image_param->offset, 2);
1278 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1279 (const gl_constant_value *)image_param->size, 3);
1280 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1281 (const gl_constant_value *)image_param->stride, 4);
1282 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1283 (const gl_constant_value *)image_param->tiling, 3);
1284 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1285 (const gl_constant_value *)image_param->swizzling, 2);
1286 param += BRW_IMAGE_PARAM_SIZE;
1287
1288 brw_mark_surface_used(
1289 stage_prog_data,
1290 stage_prog_data->binding_table.image_start + image_idx);
1291 }
1292 }
1293
1294 /**
1295 * Decide which set of clip planes should be used when clipping via
1296 * gl_Position or gl_ClipVertex.
1297 */
1298 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1299 {
1300 if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1301 /* There is currently a GLSL vertex shader, so clip according to GLSL
1302 * rules, which means compare gl_ClipVertex (or gl_Position, if
1303 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1304 * that were stored in EyeUserPlane at the time the clip planes were
1305 * specified.
1306 */
1307 return ctx->Transform.EyeUserPlane;
1308 } else {
1309 /* Either we are using fixed function or an ARB vertex program. In
1310 * either case the clip planes are going to be compared against
1311 * gl_Position (which is in clip coordinates) so we have to clip using
1312 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1313 * core.
1314 */
1315 return ctx->Transform._ClipUserPlane;
1316 }
1317 }
1318
1319 extern "C" const unsigned *
1320 brw_compile_tes(const struct brw_compiler *compiler,
1321 void *log_data,
1322 void *mem_ctx,
1323 const struct brw_tes_prog_key *key,
1324 struct brw_tes_prog_data *prog_data,
1325 const nir_shader *src_shader,
1326 struct gl_shader_program *shader_prog,
1327 int shader_time_index,
1328 unsigned *final_assembly_size,
1329 char **error_str)
1330 {
1331 const struct brw_device_info *devinfo = compiler->devinfo;
1332 struct gl_shader *shader =
1333 shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1334 const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1335
1336 nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1337 nir->info.inputs_read = key->inputs_read;
1338 nir->info.patch_inputs_read = key->patch_inputs_read;
1339
1340 struct brw_vue_map input_vue_map;
1341 brw_compute_tess_vue_map(&input_vue_map,
1342 nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1343 nir->info.patch_inputs_read);
1344
1345 nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1346 brw_nir_lower_tes_inputs(nir, &input_vue_map);
1347 brw_nir_lower_vue_outputs(nir, is_scalar);
1348 nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1349
1350 brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1351 nir->info.outputs_written,
1352 nir->info.separate_shader);
1353
1354 unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1355
1356 assert(output_size_bytes >= 1);
1357 if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1358 if (error_str)
1359 *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1360 return NULL;
1361 }
1362
1363 /* URB entry sizes are stored as a multiple of 64 bytes. */
1364 prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1365
1366 bool need_patch_header = nir->info.system_values_read &
1367 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1368 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1369
1370 /* The TES will pull most inputs using URB read messages.
1371 *
1372 * However, we push the patch header for TessLevel factors when required,
1373 * as it's a tiny amount of extra data.
1374 */
1375 prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1376
1377 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1378 fprintf(stderr, "TES Input ");
1379 brw_print_vue_map(stderr, &input_vue_map);
1380 fprintf(stderr, "TES Output ");
1381 brw_print_vue_map(stderr, &prog_data->base.vue_map);
1382 }
1383
1384 if (is_scalar) {
1385 fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1386 &prog_data->base.base, shader->Program, nir, 8,
1387 shader_time_index, &input_vue_map);
1388 if (!v.run_tes()) {
1389 if (error_str)
1390 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1391 return NULL;
1392 }
1393
1394 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1395 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1396
1397 fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1398 &prog_data->base.base, v.promoted_constants, false,
1399 MESA_SHADER_TESS_EVAL);
1400 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1401 g.enable_debug(ralloc_asprintf(mem_ctx,
1402 "%s tessellation evaluation shader %s",
1403 nir->info.label ? nir->info.label
1404 : "unnamed",
1405 nir->info.name));
1406 }
1407
1408 g.generate_code(v.cfg, 8);
1409
1410 return g.get_assembly(final_assembly_size);
1411 } else {
1412 brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1413 nir, mem_ctx, shader_time_index);
1414 if (!v.run()) {
1415 if (error_str)
1416 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1417 return NULL;
1418 }
1419
1420 if (unlikely(INTEL_DEBUG & DEBUG_TES))
1421 v.dump_instructions();
1422
1423 return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1424 &prog_data->base, v.cfg,
1425 final_assembly_size);
1426 }
1427 }