src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 static bool
  76 is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80    case MESA_SHADER_COMPUTE:
  81       return true;
  82    case MESA_SHADER_VERTEX:
  83       return compiler->scalar_vs;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 struct brw_compiler *
  90 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  91 {
  92    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  93
  94    compiler->devinfo = devinfo;
  95    compiler->shader_debug_log = shader_debug_log_mesa;
  96    compiler->shader_perf_log = shader_perf_log_mesa;
  97
  98    brw_fs_alloc_reg_sets(compiler);
  99    brw_vec4_alloc_reg_set(compiler);
 100
 101    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
 102       compiler->scalar_vs = true;
 103
 104    nir_shader_compiler_options *nir_options =
 105       rzalloc(compiler, nir_shader_compiler_options);
 106    nir_options->native_integers = true;
 107    /* In order to help allow for better CSE at the NIR level we tell NIR
 108     * to split all ffma instructions during opt_algebraic and we then
 109     * re-combine them as a later step.
 110     */
 111    nir_options->lower_ffma = true;
 112    nir_options->lower_sub = true;
 113    nir_options->lower_fdiv = true;
 114
 115    /* In the vec4 backend, our dpN instruction replicates its result to all
 116     * the components of a vec4.  We would like NIR to give us replicated fdot
 117     * instructions because it can optimize better for us.
 118     *
 119     * For the FS backend, it should be lowered away by the scalarizing pass so
 120     * we should never see fdot anyway.
 121     */
 122    nir_options->fdot_replicates = true;
 123
 124    /* We want the GLSL compiler to emit code that uses condition codes */
 125    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 126       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 127       compiler->glsl_compiler_options[i].MaxIfDepth =
 128          devinfo->gen < 6 ? 16 : UINT_MAX;
 129
 130       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 131       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 132       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 133       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 134       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 135       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 136
 137       bool is_scalar = is_scalar_shader_stage(compiler, i);
 138
 139       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 140       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 141       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 142
 143       /* !ARB_gpu_shader5 */
 144       if (devinfo->gen < 7)
 145          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 146
 147       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 148    }
 149
 150    return compiler;
 151 }
 152
 153 struct gl_shader *
 154 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 155 {
 156    struct brw_shader *shader;
 157
 158    shader = rzalloc(NULL, struct brw_shader);
 159    if (shader) {
 160       shader->base.Type = type;
 161       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 162       shader->base.Name = name;
 163       _mesa_init_shader(ctx, &shader->base);
 164    }
 165
 166    return &shader->base;
 167 }
 168
 169 /**
 170  * Performs a compile of the shader stages even when we don't know
 171  * what non-orthogonal state will be set, in the hope that it reflects
 172  * the eventual NOS used, and thus allows us to produce link failures.
 173  */
 174 static bool
 175 brw_shader_precompile(struct gl_context *ctx,
 176                       struct gl_shader_program *sh_prog)
 177 {
 178    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 179    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 180    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 181    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 182
 183    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 184       return false;
 185
 186    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 187       return false;
 188
 189    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 190       return false;
 191
 192    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 193       return false;
 194
 195    return true;
 196 }
 197
 198 static void
 199 brw_lower_packing_builtins(struct brw_context *brw,
 200                            gl_shader_stage shader_type,
 201                            exec_list *ir)
 202 {
 203    int ops = LOWER_PACK_SNORM_2x16
 204            | LOWER_UNPACK_SNORM_2x16
 205            | LOWER_PACK_UNORM_2x16
 206            | LOWER_UNPACK_UNORM_2x16;
 207
 208    if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
 209       ops |= LOWER_UNPACK_UNORM_4x8
 210            | LOWER_UNPACK_SNORM_4x8
 211            | LOWER_PACK_UNORM_4x8
 212            | LOWER_PACK_SNORM_4x8;
 213    }
 214
 215    if (brw->gen >= 7) {
 216       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 217        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 218        * lowering is needed. For SOA code, the Half2x16 ops must be
 219        * scalarized.
 220        */
 221       if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
 222          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 223              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 224       }
 225    } else {
 226       ops |= LOWER_PACK_HALF_2x16
 227           |  LOWER_UNPACK_HALF_2x16;
 228    }
 229
 230    lower_packing_builtins(ir, ops);
 231 }
 232
 233 static void
 234 process_glsl_ir(gl_shader_stage stage,
 235                 struct brw_context *brw,
 236                 struct gl_shader_program *shader_prog,
 237                 struct gl_shader *shader)
 238 {
 239    struct gl_context *ctx = &brw->ctx;
 240    const struct gl_shader_compiler_options *options =
 241       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 242
 243    /* Temporary memory context for any new IR. */
 244    void *mem_ctx = ralloc_context(NULL);
 245
 246    ralloc_adopt(mem_ctx, shader->ir);
 247
 248    /* lower_packing_builtins() inserts arithmetic instructions, so it
 249     * must precede lower_instructions().
 250     */
 251    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 252    do_mat_op_to_vec(shader->ir);
 253    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 254    lower_instructions(shader->ir,
 255                       MOD_TO_FLOOR |
 256                       DIV_TO_MUL_RCP |
 257                       SUB_TO_ADD_NEG |
 258                       EXP_TO_EXP2 |
 259                       LOG_TO_LOG2 |
 260                       bitfield_insert |
 261                       LDEXP_TO_ARITH |
 262                       CARRY_TO_ARITH |
 263                       BORROW_TO_ARITH);
 264
 265    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 266     * if-statements need to be flattened.
 267     */
 268    if (brw->gen < 6)
 269       lower_if_to_cond_assign(shader->ir, 16);
 270
 271    do_lower_texture_projection(shader->ir);
 272    brw_lower_texture_gradients(brw, shader->ir);
 273    do_vec_index_to_cond_assign(shader->ir);
 274    lower_vector_insert(shader->ir, true);
 275    lower_offset_arrays(shader->ir);
 276    brw_do_lower_unnormalized_offset(shader->ir);
 277    lower_noise(shader->ir);
 278    lower_quadop_vector(shader->ir, false);
 279
 280    bool lowered_variable_indexing =
 281       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 282                                           shader->ir,
 283                                           options->EmitNoIndirectInput,
 284                                           options->EmitNoIndirectOutput,
 285                                           options->EmitNoIndirectTemp,
 286                                           options->EmitNoIndirectUniform);
 287
 288    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 289       perf_debug("Unsupported form of variable indexing in %s; falling "
 290                  "back to very inefficient code generation\n",
 291                  _mesa_shader_stage_to_abbrev(shader->Stage));
 292    }
 293
 294    lower_ubo_reference(shader, shader->ir);
 295
 296    bool progress;
 297    do {
 298       progress = false;
 299
 300       if (is_scalar_shader_stage(brw->intelScreen->compiler, shader->Stage)) {
 301          brw_do_channel_expressions(shader->ir);
 302          brw_do_vector_splitting(shader->ir);
 303       }
 304
 305       progress = do_lower_jumps(shader->ir, true, true,
 306                                 true, /* main return */
 307                                 false, /* continue */
 308                                 false /* loops */
 309                                 ) || progress;
 310
 311       progress = do_common_optimization(shader->ir, true, true,
 312                                         options, ctx->Const.NativeIntegers) || progress;
 313    } while (progress);
 314
 315    validate_ir_tree(shader->ir);
 316
 317    /* Now that we've finished altering the linked IR, reparent any live IR back
 318     * to the permanent memory context, and free the temporary one (discarding any
 319     * junk we optimized away).
 320     */
 321    reparent_ir(shader->ir, shader->ir);
 322    ralloc_free(mem_ctx);
 323
 324    if (ctx->_Shader->Flags & GLSL_DUMP) {
 325       fprintf(stderr, "\n");
 326       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 327               _mesa_shader_stage_to_string(shader->Stage),
 328               shader_prog->Name);
 329       _mesa_print_ir(stderr, shader->ir, NULL);
 330       fprintf(stderr, "\n");
 331    }
 332 }
 333
 334 GLboolean
 335 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 336 {
 337    struct brw_context *brw = brw_context(ctx);
 338    const struct brw_compiler *compiler = brw->intelScreen->compiler;
 339    unsigned int stage;
 340
 341    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 342       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 343       if (!shader)
 344          continue;
 345
 346       struct gl_program *prog =
 347          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 348                                 shader->Name);
 349       if (!prog)
 350         return false;
 351       prog->Parameters = _mesa_new_parameter_list();
 352
 353       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 354
 355       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 356
 357       /* Make a pass over the IR to add state references for any built-in
 358        * uniforms that are used.  This has to be done now (during linking).
 359        * Code generation doesn't happen until the first time this shader is
 360        * used for rendering.  Waiting until then to generate the parameters is
 361        * too late.  At that point, the values for the built-in uniforms won't
 362        * get sent to the shader.
 363        */
 364       foreach_in_list(ir_instruction, node, shader->ir) {
 365          ir_variable *var = node->as_variable();
 366
 367          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 368              || (strncmp(var->name, "gl_", 3) != 0))
 369             continue;
 370
 371          const ir_state_slot *const slots = var->get_state_slots();
 372          assert(slots != NULL);
 373
 374          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 375             _mesa_add_state_reference(prog->Parameters,
 376                                       (gl_state_index *) slots[i].tokens);
 377          }
 378       }
 379
 380       do_set_program_inouts(shader->ir, prog, shader->Stage);
 381
 382       prog->SamplersUsed = shader->active_samplers;
 383       prog->ShadowSamplers = shader->shadow_samplers;
 384       _mesa_update_shader_textures_used(shProg, prog);
 385
 386       _mesa_reference_program(ctx, &shader->Program, prog);
 387
 388       brw_add_texrect_params(prog);
 389
 390       prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
 391                                  is_scalar_shader_stage(compiler, stage));
 392
 393       _mesa_reference_program(ctx, &prog, NULL);
 394    }
 395
 396    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 397       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 398          const struct gl_shader *sh = shProg->Shaders[i];
 399          if (!sh)
 400             continue;
 401
 402          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 403                  _mesa_shader_stage_to_string(sh->Stage),
 404                  i, shProg->Name);
 405          fprintf(stderr, "%s", sh->Source);
 406          fprintf(stderr, "\n");
 407       }
 408    }
 409
 410    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 411       return false;
 412
 413    return true;
 414 }
 415
 416
 417 enum brw_reg_type
 418 brw_type_for_base_type(const struct glsl_type *type)
 419 {
 420    switch (type->base_type) {
 421    case GLSL_TYPE_FLOAT:
 422       return BRW_REGISTER_TYPE_F;
 423    case GLSL_TYPE_INT:
 424    case GLSL_TYPE_BOOL:
 425    case GLSL_TYPE_SUBROUTINE:
 426       return BRW_REGISTER_TYPE_D;
 427    case GLSL_TYPE_UINT:
 428       return BRW_REGISTER_TYPE_UD;
 429    case GLSL_TYPE_ARRAY:
 430       return brw_type_for_base_type(type->fields.array);
 431    case GLSL_TYPE_STRUCT:
 432    case GLSL_TYPE_SAMPLER:
 433    case GLSL_TYPE_ATOMIC_UINT:
 434       /* These should be overridden with the type of the member when
 435        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 436        * way to trip up if we don't.
 437        */
 438       return BRW_REGISTER_TYPE_UD;
 439    case GLSL_TYPE_IMAGE:
 440       return BRW_REGISTER_TYPE_UD;
 441    case GLSL_TYPE_VOID:
 442    case GLSL_TYPE_ERROR:
 443    case GLSL_TYPE_INTERFACE:
 444    case GLSL_TYPE_DOUBLE:
 445    case GLSL_TYPE_FUNCTION:
 446       unreachable("not reached");
 447    }
 448
 449    return BRW_REGISTER_TYPE_F;
 450 }
 451
 452 enum brw_conditional_mod
 453 brw_conditional_for_comparison(unsigned int op)
 454 {
 455    switch (op) {
 456    case ir_binop_less:
 457       return BRW_CONDITIONAL_L;
 458    case ir_binop_greater:
 459       return BRW_CONDITIONAL_G;
 460    case ir_binop_lequal:
 461       return BRW_CONDITIONAL_LE;
 462    case ir_binop_gequal:
 463       return BRW_CONDITIONAL_GE;
 464    case ir_binop_equal:
 465    case ir_binop_all_equal: /* same as equal for scalars */
 466       return BRW_CONDITIONAL_Z;
 467    case ir_binop_nequal:
 468    case ir_binop_any_nequal: /* same as nequal for scalars */
 469       return BRW_CONDITIONAL_NZ;
 470    default:
 471       unreachable("not reached: bad operation for comparison");
 472    }
 473 }
 474
 475 uint32_t
 476 brw_math_function(enum opcode op)
 477 {
 478    switch (op) {
 479    case SHADER_OPCODE_RCP:
 480       return BRW_MATH_FUNCTION_INV;
 481    case SHADER_OPCODE_RSQ:
 482       return BRW_MATH_FUNCTION_RSQ;
 483    case SHADER_OPCODE_SQRT:
 484       return BRW_MATH_FUNCTION_SQRT;
 485    case SHADER_OPCODE_EXP2:
 486       return BRW_MATH_FUNCTION_EXP;
 487    case SHADER_OPCODE_LOG2:
 488       return BRW_MATH_FUNCTION_LOG;
 489    case SHADER_OPCODE_POW:
 490       return BRW_MATH_FUNCTION_POW;
 491    case SHADER_OPCODE_SIN:
 492       return BRW_MATH_FUNCTION_SIN;
 493    case SHADER_OPCODE_COS:
 494       return BRW_MATH_FUNCTION_COS;
 495    case SHADER_OPCODE_INT_QUOTIENT:
 496       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 497    case SHADER_OPCODE_INT_REMAINDER:
 498       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 499    default:
 500       unreachable("not reached: unknown math function");
 501    }
 502 }
 503
 504 uint32_t
 505 brw_texture_offset(int *offsets, unsigned num_components)
 506 {
 507    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 508
 509    /* Combine all three offsets into a single unsigned dword:
 510     *
 511     *    bits 11:8 - U Offset (X component)
 512     *    bits  7:4 - V Offset (Y component)
 513     *    bits  3:0 - R Offset (Z component)
 514     */
 515    unsigned offset_bits = 0;
 516    for (unsigned i = 0; i < num_components; i++) {
 517       const unsigned shift = 4 * (2 - i);
 518       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 519    }
 520    return offset_bits;
 521 }
 522
 523 const char *
 524 brw_instruction_name(enum opcode op)
 525 {
 526    switch (op) {
 527    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 528       assert(opcode_descs[op].name);
 529       return opcode_descs[op].name;
 530    case FS_OPCODE_FB_WRITE:
 531       return "fb_write";
 532    case FS_OPCODE_FB_WRITE_LOGICAL:
 533       return "fb_write_logical";
 534    case FS_OPCODE_BLORP_FB_WRITE:
 535       return "blorp_fb_write";
 536    case FS_OPCODE_REP_FB_WRITE:
 537       return "rep_fb_write";
 538
 539    case SHADER_OPCODE_RCP:
 540       return "rcp";
 541    case SHADER_OPCODE_RSQ:
 542       return "rsq";
 543    case SHADER_OPCODE_SQRT:
 544       return "sqrt";
 545    case SHADER_OPCODE_EXP2:
 546       return "exp2";
 547    case SHADER_OPCODE_LOG2:
 548       return "log2";
 549    case SHADER_OPCODE_POW:
 550       return "pow";
 551    case SHADER_OPCODE_INT_QUOTIENT:
 552       return "int_quot";
 553    case SHADER_OPCODE_INT_REMAINDER:
 554       return "int_rem";
 555    case SHADER_OPCODE_SIN:
 556       return "sin";
 557    case SHADER_OPCODE_COS:
 558       return "cos";
 559
 560    case SHADER_OPCODE_TEX:
 561       return "tex";
 562    case SHADER_OPCODE_TEX_LOGICAL:
 563       return "tex_logical";
 564    case SHADER_OPCODE_TXD:
 565       return "txd";
 566    case SHADER_OPCODE_TXD_LOGICAL:
 567       return "txd_logical";
 568    case SHADER_OPCODE_TXF:
 569       return "txf";
 570    case SHADER_OPCODE_TXF_LOGICAL:
 571       return "txf_logical";
 572    case SHADER_OPCODE_TXL:
 573       return "txl";
 574    case SHADER_OPCODE_TXL_LOGICAL:
 575       return "txl_logical";
 576    case SHADER_OPCODE_TXS:
 577       return "txs";
 578    case SHADER_OPCODE_TXS_LOGICAL:
 579       return "txs_logical";
 580    case FS_OPCODE_TXB:
 581       return "txb";
 582    case FS_OPCODE_TXB_LOGICAL:
 583       return "txb_logical";
 584    case SHADER_OPCODE_TXF_CMS:
 585       return "txf_cms";
 586    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 587       return "txf_cms_logical";
 588    case SHADER_OPCODE_TXF_UMS:
 589       return "txf_ums";
 590    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 591       return "txf_ums_logical";
 592    case SHADER_OPCODE_TXF_MCS:
 593       return "txf_mcs";
 594    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 595       return "txf_mcs_logical";
 596    case SHADER_OPCODE_LOD:
 597       return "lod";
 598    case SHADER_OPCODE_LOD_LOGICAL:
 599       return "lod_logical";
 600    case SHADER_OPCODE_TG4:
 601       return "tg4";
 602    case SHADER_OPCODE_TG4_LOGICAL:
 603       return "tg4_logical";
 604    case SHADER_OPCODE_TG4_OFFSET:
 605       return "tg4_offset";
 606    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 607       return "tg4_offset_logical";
 608    case SHADER_OPCODE_SAMPLEINFO:
 609       return "sampleinfo";
 610
 611    case SHADER_OPCODE_SHADER_TIME_ADD:
 612       return "shader_time_add";
 613
 614    case SHADER_OPCODE_UNTYPED_ATOMIC:
 615       return "untyped_atomic";
 616    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 617       return "untyped_atomic_logical";
 618    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 619       return "untyped_surface_read";
 620    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 621       return "untyped_surface_read_logical";
 622    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 623       return "untyped_surface_write";
 624    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 625       return "untyped_surface_write_logical";
 626    case SHADER_OPCODE_TYPED_ATOMIC:
 627       return "typed_atomic";
 628    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 629       return "typed_atomic_logical";
 630    case SHADER_OPCODE_TYPED_SURFACE_READ:
 631       return "typed_surface_read";
 632    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 633       return "typed_surface_read_logical";
 634    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 635       return "typed_surface_write";
 636    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 637       return "typed_surface_write_logical";
 638    case SHADER_OPCODE_MEMORY_FENCE:
 639       return "memory_fence";
 640
 641    case SHADER_OPCODE_LOAD_PAYLOAD:
 642       return "load_payload";
 643
 644    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 645       return "gen4_scratch_read";
 646    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 647       return "gen4_scratch_write";
 648    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 649       return "gen7_scratch_read";
 650    case SHADER_OPCODE_URB_WRITE_SIMD8:
 651       return "gen8_urb_write_simd8";
 652
 653    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 654       return "find_live_channel";
 655    case SHADER_OPCODE_BROADCAST:
 656       return "broadcast";
 657
 658    case VEC4_OPCODE_MOV_BYTES:
 659       return "mov_bytes";
 660    case VEC4_OPCODE_PACK_BYTES:
 661       return "pack_bytes";
 662    case VEC4_OPCODE_UNPACK_UNIFORM:
 663       return "unpack_uniform";
 664
 665    case FS_OPCODE_DDX_COARSE:
 666       return "ddx_coarse";
 667    case FS_OPCODE_DDX_FINE:
 668       return "ddx_fine";
 669    case FS_OPCODE_DDY_COARSE:
 670       return "ddy_coarse";
 671    case FS_OPCODE_DDY_FINE:
 672       return "ddy_fine";
 673
 674    case FS_OPCODE_CINTERP:
 675       return "cinterp";
 676    case FS_OPCODE_LINTERP:
 677       return "linterp";
 678
 679    case FS_OPCODE_PIXEL_X:
 680       return "pixel_x";
 681    case FS_OPCODE_PIXEL_Y:
 682       return "pixel_y";
 683
 684    case FS_OPCODE_GET_BUFFER_SIZE:
 685       return "fs_get_buffer_size";
 686
 687    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 688       return "uniform_pull_const";
 689    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 690       return "uniform_pull_const_gen7";
 691    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 692       return "varying_pull_const";
 693    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 694       return "varying_pull_const_gen7";
 695
 696    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 697       return "mov_dispatch_to_flags";
 698    case FS_OPCODE_DISCARD_JUMP:
 699       return "discard_jump";
 700
 701    case FS_OPCODE_SET_SAMPLE_ID:
 702       return "set_sample_id";
 703    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 704       return "set_simd4x2_offset";
 705
 706    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 707       return "pack_half_2x16_split";
 708    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 709       return "unpack_half_2x16_split_x";
 710    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 711       return "unpack_half_2x16_split_y";
 712
 713    case FS_OPCODE_PLACEHOLDER_HALT:
 714       return "placeholder_halt";
 715
 716    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 717       return "interp_centroid";
 718    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 719       return "interp_sample";
 720    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 721       return "interp_shared_offset";
 722    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 723       return "interp_per_slot_offset";
 724
 725    case VS_OPCODE_URB_WRITE:
 726       return "vs_urb_write";
 727    case VS_OPCODE_PULL_CONSTANT_LOAD:
 728       return "pull_constant_load";
 729    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 730       return "pull_constant_load_gen7";
 731
 732    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 733       return "set_simd4x2_header_gen9";
 734
 735    case VS_OPCODE_GET_BUFFER_SIZE:
 736       return "vs_get_buffer_size";
 737
 738    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 739       return "unpack_flags_simd4x2";
 740
 741    case GS_OPCODE_URB_WRITE:
 742       return "gs_urb_write";
 743    case GS_OPCODE_URB_WRITE_ALLOCATE:
 744       return "gs_urb_write_allocate";
 745    case GS_OPCODE_THREAD_END:
 746       return "gs_thread_end";
 747    case GS_OPCODE_SET_WRITE_OFFSET:
 748       return "set_write_offset";
 749    case GS_OPCODE_SET_VERTEX_COUNT:
 750       return "set_vertex_count";
 751    case GS_OPCODE_SET_DWORD_2:
 752       return "set_dword_2";
 753    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 754       return "prepare_channel_masks";
 755    case GS_OPCODE_SET_CHANNEL_MASKS:
 756       return "set_channel_masks";
 757    case GS_OPCODE_GET_INSTANCE_ID:
 758       return "get_instance_id";
 759    case GS_OPCODE_FF_SYNC:
 760       return "ff_sync";
 761    case GS_OPCODE_SET_PRIMITIVE_ID:
 762       return "set_primitive_id";
 763    case GS_OPCODE_SVB_WRITE:
 764       return "gs_svb_write";
 765    case GS_OPCODE_SVB_SET_DST_INDEX:
 766       return "gs_svb_set_dst_index";
 767    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 768       return "gs_ff_sync_set_primitives";
 769    case CS_OPCODE_CS_TERMINATE:
 770       return "cs_terminate";
 771    case SHADER_OPCODE_BARRIER:
 772       return "barrier";
 773    case SHADER_OPCODE_MULH:
 774       return "mulh";
 775    }
 776
 777    unreachable("not reached");
 778 }
 779
 780 bool
 781 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 782 {
 783    union {
 784       unsigned ud;
 785       int d;
 786       float f;
 787    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 788
 789    switch (type) {
 790    case BRW_REGISTER_TYPE_UD:
 791    case BRW_REGISTER_TYPE_D:
 792    case BRW_REGISTER_TYPE_UQ:
 793    case BRW_REGISTER_TYPE_Q:
 794       /* Nothing to do. */
 795       return false;
 796    case BRW_REGISTER_TYPE_UW:
 797       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 798       break;
 799    case BRW_REGISTER_TYPE_W:
 800       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 801       break;
 802    case BRW_REGISTER_TYPE_F:
 803       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 804       break;
 805    case BRW_REGISTER_TYPE_UB:
 806    case BRW_REGISTER_TYPE_B:
 807       unreachable("no UB/B immediates");
 808    case BRW_REGISTER_TYPE_V:
 809    case BRW_REGISTER_TYPE_UV:
 810    case BRW_REGISTER_TYPE_VF:
 811       unreachable("unimplemented: saturate vector immediate");
 812    case BRW_REGISTER_TYPE_DF:
 813    case BRW_REGISTER_TYPE_HF:
 814       unreachable("unimplemented: saturate DF/HF immediate");
 815    }
 816
 817    if (imm.ud != sat_imm.ud) {
 818       reg->dw1.ud = sat_imm.ud;
 819       return true;
 820    }
 821    return false;
 822 }
 823
 824 bool
 825 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 826 {
 827    switch (type) {
 828    case BRW_REGISTER_TYPE_D:
 829    case BRW_REGISTER_TYPE_UD:
 830       reg->dw1.d = -reg->dw1.d;
 831       return true;
 832    case BRW_REGISTER_TYPE_W:
 833    case BRW_REGISTER_TYPE_UW:
 834       reg->dw1.d = -(int16_t)reg->dw1.ud;
 835       return true;
 836    case BRW_REGISTER_TYPE_F:
 837       reg->dw1.f = -reg->dw1.f;
 838       return true;
 839    case BRW_REGISTER_TYPE_VF:
 840       reg->dw1.ud ^= 0x80808080;
 841       return true;
 842    case BRW_REGISTER_TYPE_UB:
 843    case BRW_REGISTER_TYPE_B:
 844       unreachable("no UB/B immediates");
 845    case BRW_REGISTER_TYPE_UV:
 846    case BRW_REGISTER_TYPE_V:
 847       assert(!"unimplemented: negate UV/V immediate");
 848    case BRW_REGISTER_TYPE_UQ:
 849    case BRW_REGISTER_TYPE_Q:
 850       assert(!"unimplemented: negate UQ/Q immediate");
 851    case BRW_REGISTER_TYPE_DF:
 852    case BRW_REGISTER_TYPE_HF:
 853       assert(!"unimplemented: negate DF/HF immediate");
 854    }
 855
 856    return false;
 857 }
 858
 859 bool
 860 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 861 {
 862    switch (type) {
 863    case BRW_REGISTER_TYPE_D:
 864       reg->dw1.d = abs(reg->dw1.d);
 865       return true;
 866    case BRW_REGISTER_TYPE_W:
 867       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 868       return true;
 869    case BRW_REGISTER_TYPE_F:
 870       reg->dw1.f = fabsf(reg->dw1.f);
 871       return true;
 872    case BRW_REGISTER_TYPE_VF:
 873       reg->dw1.ud &= ~0x80808080;
 874       return true;
 875    case BRW_REGISTER_TYPE_UB:
 876    case BRW_REGISTER_TYPE_B:
 877       unreachable("no UB/B immediates");
 878    case BRW_REGISTER_TYPE_UQ:
 879    case BRW_REGISTER_TYPE_UD:
 880    case BRW_REGISTER_TYPE_UW:
 881    case BRW_REGISTER_TYPE_UV:
 882       /* Presumably the absolute value modifier on an unsigned source is a
 883        * nop, but it would be nice to confirm.
 884        */
 885       assert(!"unimplemented: abs unsigned immediate");
 886    case BRW_REGISTER_TYPE_V:
 887       assert(!"unimplemented: abs V immediate");
 888    case BRW_REGISTER_TYPE_Q:
 889       assert(!"unimplemented: abs Q immediate");
 890    case BRW_REGISTER_TYPE_DF:
 891    case BRW_REGISTER_TYPE_HF:
 892       assert(!"unimplemented: abs DF/HF immediate");
 893    }
 894
 895    return false;
 896 }
 897
 898 backend_shader::backend_shader(const struct brw_compiler *compiler,
 899                                void *log_data,
 900                                void *mem_ctx,
 901                                nir_shader *shader,
 902                                struct brw_stage_prog_data *stage_prog_data)
 903    : compiler(compiler),
 904      log_data(log_data),
 905      devinfo(compiler->devinfo),
 906      nir(shader),
 907      stage_prog_data(stage_prog_data),
 908      mem_ctx(mem_ctx),
 909      cfg(NULL),
 910      stage(shader->stage)
 911 {
 912    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 913    stage_name = _mesa_shader_stage_to_string(stage);
 914    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 915 }
 916
 917 bool
 918 backend_reg::is_zero() const
 919 {
 920    if (file != IMM)
 921       return false;
 922
 923    return fixed_hw_reg.dw1.d == 0;
 924 }
 925
 926 bool
 927 backend_reg::is_one() const
 928 {
 929    if (file != IMM)
 930       return false;
 931
 932    return type == BRW_REGISTER_TYPE_F
 933           ? fixed_hw_reg.dw1.f == 1.0
 934           : fixed_hw_reg.dw1.d == 1;
 935 }
 936
 937 bool
 938 backend_reg::is_negative_one() const
 939 {
 940    if (file != IMM)
 941       return false;
 942
 943    switch (type) {
 944    case BRW_REGISTER_TYPE_F:
 945       return fixed_hw_reg.dw1.f == -1.0;
 946    case BRW_REGISTER_TYPE_D:
 947       return fixed_hw_reg.dw1.d == -1;
 948    default:
 949       return false;
 950    }
 951 }
 952
 953 bool
 954 backend_reg::is_null() const
 955 {
 956    return file == HW_REG &&
 957           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 958           fixed_hw_reg.nr == BRW_ARF_NULL;
 959 }
 960
 961
 962 bool
 963 backend_reg::is_accumulator() const
 964 {
 965    return file == HW_REG &&
 966           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 967           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 968 }
 969
 970 bool
 971 backend_reg::in_range(const backend_reg &r, unsigned n) const
 972 {
 973    return (file == r.file &&
 974            reg == r.reg &&
 975            reg_offset >= r.reg_offset &&
 976            reg_offset < r.reg_offset + n);
 977 }
 978
 979 bool
 980 backend_instruction::is_commutative() const
 981 {
 982    switch (opcode) {
 983    case BRW_OPCODE_AND:
 984    case BRW_OPCODE_OR:
 985    case BRW_OPCODE_XOR:
 986    case BRW_OPCODE_ADD:
 987    case BRW_OPCODE_MUL:
 988    case SHADER_OPCODE_MULH:
 989       return true;
 990    case BRW_OPCODE_SEL:
 991       /* MIN and MAX are commutative. */
 992       if (conditional_mod == BRW_CONDITIONAL_GE ||
 993           conditional_mod == BRW_CONDITIONAL_L) {
 994          return true;
 995       }
 996       /* fallthrough */
 997    default:
 998       return false;
 999    }
1000 }
1001
1002 bool
1003 backend_instruction::is_3src() const
1004 {
1005    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
1006 }
1007
1008 bool
1009 backend_instruction::is_tex() const
1010 {
1011    return (opcode == SHADER_OPCODE_TEX ||
1012            opcode == FS_OPCODE_TXB ||
1013            opcode == SHADER_OPCODE_TXD ||
1014            opcode == SHADER_OPCODE_TXF ||
1015            opcode == SHADER_OPCODE_TXF_CMS ||
1016            opcode == SHADER_OPCODE_TXF_UMS ||
1017            opcode == SHADER_OPCODE_TXF_MCS ||
1018            opcode == SHADER_OPCODE_TXL ||
1019            opcode == SHADER_OPCODE_TXS ||
1020            opcode == SHADER_OPCODE_LOD ||
1021            opcode == SHADER_OPCODE_TG4 ||
1022            opcode == SHADER_OPCODE_TG4_OFFSET);
1023 }
1024
1025 bool
1026 backend_instruction::is_math() const
1027 {
1028    return (opcode == SHADER_OPCODE_RCP ||
1029            opcode == SHADER_OPCODE_RSQ ||
1030            opcode == SHADER_OPCODE_SQRT ||
1031            opcode == SHADER_OPCODE_EXP2 ||
1032            opcode == SHADER_OPCODE_LOG2 ||
1033            opcode == SHADER_OPCODE_SIN ||
1034            opcode == SHADER_OPCODE_COS ||
1035            opcode == SHADER_OPCODE_INT_QUOTIENT ||
1036            opcode == SHADER_OPCODE_INT_REMAINDER ||
1037            opcode == SHADER_OPCODE_POW);
1038 }
1039
1040 bool
1041 backend_instruction::is_control_flow() const
1042 {
1043    switch (opcode) {
1044    case BRW_OPCODE_DO:
1045    case BRW_OPCODE_WHILE:
1046    case BRW_OPCODE_IF:
1047    case BRW_OPCODE_ELSE:
1048    case BRW_OPCODE_ENDIF:
1049    case BRW_OPCODE_BREAK:
1050    case BRW_OPCODE_CONTINUE:
1051       return true;
1052    default:
1053       return false;
1054    }
1055 }
1056
1057 bool
1058 backend_instruction::can_do_source_mods() const
1059 {
1060    switch (opcode) {
1061    case BRW_OPCODE_ADDC:
1062    case BRW_OPCODE_BFE:
1063    case BRW_OPCODE_BFI1:
1064    case BRW_OPCODE_BFI2:
1065    case BRW_OPCODE_BFREV:
1066    case BRW_OPCODE_CBIT:
1067    case BRW_OPCODE_FBH:
1068    case BRW_OPCODE_FBL:
1069    case BRW_OPCODE_SUBB:
1070       return false;
1071    default:
1072       return true;
1073    }
1074 }
1075
1076 bool
1077 backend_instruction::can_do_saturate() const
1078 {
1079    switch (opcode) {
1080    case BRW_OPCODE_ADD:
1081    case BRW_OPCODE_ASR:
1082    case BRW_OPCODE_AVG:
1083    case BRW_OPCODE_DP2:
1084    case BRW_OPCODE_DP3:
1085    case BRW_OPCODE_DP4:
1086    case BRW_OPCODE_DPH:
1087    case BRW_OPCODE_F16TO32:
1088    case BRW_OPCODE_F32TO16:
1089    case BRW_OPCODE_LINE:
1090    case BRW_OPCODE_LRP:
1091    case BRW_OPCODE_MAC:
1092    case BRW_OPCODE_MAD:
1093    case BRW_OPCODE_MATH:
1094    case BRW_OPCODE_MOV:
1095    case BRW_OPCODE_MUL:
1096    case SHADER_OPCODE_MULH:
1097    case BRW_OPCODE_PLN:
1098    case BRW_OPCODE_RNDD:
1099    case BRW_OPCODE_RNDE:
1100    case BRW_OPCODE_RNDU:
1101    case BRW_OPCODE_RNDZ:
1102    case BRW_OPCODE_SEL:
1103    case BRW_OPCODE_SHL:
1104    case BRW_OPCODE_SHR:
1105    case FS_OPCODE_LINTERP:
1106    case SHADER_OPCODE_COS:
1107    case SHADER_OPCODE_EXP2:
1108    case SHADER_OPCODE_LOG2:
1109    case SHADER_OPCODE_POW:
1110    case SHADER_OPCODE_RCP:
1111    case SHADER_OPCODE_RSQ:
1112    case SHADER_OPCODE_SIN:
1113    case SHADER_OPCODE_SQRT:
1114       return true;
1115    default:
1116       return false;
1117    }
1118 }
1119
1120 bool
1121 backend_instruction::can_do_cmod() const
1122 {
1123    switch (opcode) {
1124    case BRW_OPCODE_ADD:
1125    case BRW_OPCODE_ADDC:
1126    case BRW_OPCODE_AND:
1127    case BRW_OPCODE_ASR:
1128    case BRW_OPCODE_AVG:
1129    case BRW_OPCODE_CMP:
1130    case BRW_OPCODE_CMPN:
1131    case BRW_OPCODE_DP2:
1132    case BRW_OPCODE_DP3:
1133    case BRW_OPCODE_DP4:
1134    case BRW_OPCODE_DPH:
1135    case BRW_OPCODE_F16TO32:
1136    case BRW_OPCODE_F32TO16:
1137    case BRW_OPCODE_FRC:
1138    case BRW_OPCODE_LINE:
1139    case BRW_OPCODE_LRP:
1140    case BRW_OPCODE_LZD:
1141    case BRW_OPCODE_MAC:
1142    case BRW_OPCODE_MACH:
1143    case BRW_OPCODE_MAD:
1144    case BRW_OPCODE_MOV:
1145    case BRW_OPCODE_MUL:
1146    case BRW_OPCODE_NOT:
1147    case BRW_OPCODE_OR:
1148    case BRW_OPCODE_PLN:
1149    case BRW_OPCODE_RNDD:
1150    case BRW_OPCODE_RNDE:
1151    case BRW_OPCODE_RNDU:
1152    case BRW_OPCODE_RNDZ:
1153    case BRW_OPCODE_SAD2:
1154    case BRW_OPCODE_SADA2:
1155    case BRW_OPCODE_SHL:
1156    case BRW_OPCODE_SHR:
1157    case BRW_OPCODE_SUBB:
1158    case BRW_OPCODE_XOR:
1159    case FS_OPCODE_CINTERP:
1160    case FS_OPCODE_LINTERP:
1161       return true;
1162    default:
1163       return false;
1164    }
1165 }
1166
1167 bool
1168 backend_instruction::reads_accumulator_implicitly() const
1169 {
1170    switch (opcode) {
1171    case BRW_OPCODE_MAC:
1172    case BRW_OPCODE_MACH:
1173    case BRW_OPCODE_SADA2:
1174       return true;
1175    default:
1176       return false;
1177    }
1178 }
1179
1180 bool
1181 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1182 {
1183    return writes_accumulator ||
1184           (devinfo->gen < 6 &&
1185            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1186             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1187              opcode != FS_OPCODE_CINTERP)));
1188 }
1189
1190 bool
1191 backend_instruction::has_side_effects() const
1192 {
1193    switch (opcode) {
1194    case SHADER_OPCODE_UNTYPED_ATOMIC:
1195    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1196    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1197    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1198    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1199    case SHADER_OPCODE_TYPED_ATOMIC:
1200    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1201    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1202    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1203    case SHADER_OPCODE_MEMORY_FENCE:
1204    case SHADER_OPCODE_URB_WRITE_SIMD8:
1205    case FS_OPCODE_FB_WRITE:
1206    case SHADER_OPCODE_BARRIER:
1207       return true;
1208    default:
1209       return false;
1210    }
1211 }
1212
1213 #ifndef NDEBUG
1214 static bool
1215 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1216 {
1217    bool found = false;
1218    foreach_inst_in_block (backend_instruction, i, block) {
1219       if (inst == i) {
1220          found = true;
1221       }
1222    }
1223    return found;
1224 }
1225 #endif
1226
1227 static void
1228 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1229 {
1230    for (bblock_t *block_iter = start_block->next();
1231         !block_iter->link.is_tail_sentinel();
1232         block_iter = block_iter->next()) {
1233       block_iter->start_ip += ip_adjustment;
1234       block_iter->end_ip += ip_adjustment;
1235    }
1236 }
1237
1238 void
1239 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1240 {
1241    if (!this->is_head_sentinel())
1242       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1243
1244    block->end_ip++;
1245
1246    adjust_later_block_ips(block, 1);
1247
1248    exec_node::insert_after(inst);
1249 }
1250
1251 void
1252 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1253 {
1254    if (!this->is_tail_sentinel())
1255       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1256
1257    block->end_ip++;
1258
1259    adjust_later_block_ips(block, 1);
1260
1261    exec_node::insert_before(inst);
1262 }
1263
1264 void
1265 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1266 {
1267    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1268
1269    unsigned num_inst = list->length();
1270
1271    block->end_ip += num_inst;
1272
1273    adjust_later_block_ips(block, num_inst);
1274
1275    exec_node::insert_before(list);
1276 }
1277
1278 void
1279 backend_instruction::remove(bblock_t *block)
1280 {
1281    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1282
1283    adjust_later_block_ips(block, -1);
1284
1285    if (block->start_ip == block->end_ip) {
1286       block->cfg->remove_block(block);
1287    } else {
1288       block->end_ip--;
1289    }
1290
1291    exec_node::remove();
1292 }
1293
1294 void
1295 backend_shader::dump_instructions()
1296 {
1297    dump_instructions(NULL);
1298 }
1299
1300 void
1301 backend_shader::dump_instructions(const char *name)
1302 {
1303    FILE *file = stderr;
1304    if (name && geteuid() != 0) {
1305       file = fopen(name, "w");
1306       if (!file)
1307          file = stderr;
1308    }
1309
1310    if (cfg) {
1311       int ip = 0;
1312       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1313          fprintf(file, "%4d: ", ip++);
1314          dump_instruction(inst, file);
1315       }
1316    } else {
1317       int ip = 0;
1318       foreach_in_list(backend_instruction, inst, &instructions) {
1319          fprintf(file, "%4d: ", ip++);
1320          dump_instruction(inst, file);
1321       }
1322    }
1323
1324    if (file != stderr) {
1325       fclose(file);
1326    }
1327 }
1328
1329 void
1330 backend_shader::calculate_cfg()
1331 {
1332    if (this->cfg)
1333       return;
1334    cfg = new(mem_ctx) cfg_t(&this->instructions);
1335 }
1336
1337 void
1338 backend_shader::invalidate_cfg()
1339 {
1340    ralloc_free(this->cfg);
1341    this->cfg = NULL;
1342 }
1343
1344 /**
1345  * Sets up the starting offsets for the groups of binding table entries
1346  * commong to all pipeline stages.
1347  *
1348  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1349  * unused but also make sure that addition of small offsets to them will
1350  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1351  */
1352 void
1353 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1354                                         const struct brw_device_info *devinfo,
1355                                         const struct gl_shader_program *shader_prog,
1356                                         const struct gl_program *prog,
1357                                         struct brw_stage_prog_data *stage_prog_data,
1358                                         uint32_t next_binding_table_offset)
1359 {
1360    const struct gl_shader *shader = NULL;
1361    int num_textures = _mesa_fls(prog->SamplersUsed);
1362
1363    if (shader_prog)
1364       shader = shader_prog->_LinkedShaders[stage];
1365
1366    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1367    next_binding_table_offset += num_textures;
1368
1369    if (shader) {
1370       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1371       next_binding_table_offset += shader->NumUniformBlocks;
1372    } else {
1373       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1374    }
1375
1376    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1377       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1378       next_binding_table_offset++;
1379    } else {
1380       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1381    }
1382
1383    if (prog->UsesGather) {
1384       if (devinfo->gen >= 8) {
1385          stage_prog_data->binding_table.gather_texture_start =
1386             stage_prog_data->binding_table.texture_start;
1387       } else {
1388          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1389          next_binding_table_offset += num_textures;
1390       }
1391    } else {
1392       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1393    }
1394
1395    if (shader_prog && shader_prog->NumAtomicBuffers) {
1396       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1397       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1398    } else {
1399       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1400    }
1401
1402    if (shader && shader->NumImages) {
1403       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1404       next_binding_table_offset += shader->NumImages;
1405    } else {
1406       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1407    }
1408
1409    /* This may or may not be used depending on how the compile goes. */
1410    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1411    next_binding_table_offset++;
1412
1413    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1414
1415    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1416 }
1417
1418 static void
1419 setup_vec4_uniform_value(const gl_constant_value **params,
1420                          const gl_constant_value *values,
1421                          unsigned n)
1422 {
1423    static const gl_constant_value zero = { 0 };
1424
1425    for (unsigned i = 0; i < n; ++i)
1426       params[i] = &values[i];
1427
1428    for (unsigned i = n; i < 4; ++i)
1429       params[i] = &zero;
1430 }
1431
1432 void
1433 brw_setup_image_uniform_values(gl_shader_stage stage,
1434                                struct brw_stage_prog_data *stage_prog_data,
1435                                unsigned param_start_index,
1436                                const gl_uniform_storage *storage)
1437 {
1438    const gl_constant_value **param =
1439       &stage_prog_data->param[param_start_index];
1440
1441    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1442       const unsigned image_idx = storage->image[stage].index + i;
1443       const brw_image_param *image_param =
1444          &stage_prog_data->image_param[image_idx];
1445
1446       /* Upload the brw_image_param structure.  The order is expected to match
1447        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1448        */
1449       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1450          (const gl_constant_value *)&image_param->surface_idx, 1);
1451       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1452          (const gl_constant_value *)image_param->offset, 2);
1453       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1454          (const gl_constant_value *)image_param->size, 3);
1455       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1456          (const gl_constant_value *)image_param->stride, 4);
1457       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1458          (const gl_constant_value *)image_param->tiling, 3);
1459       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1460          (const gl_constant_value *)image_param->swizzling, 2);
1461       param += BRW_IMAGE_PARAM_SIZE;
1462
1463       brw_mark_surface_used(
1464          stage_prog_data,
1465          stage_prog_data->binding_table.image_start + image_idx);
1466    }
1467 }