2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/macros.h"
25 #include "brw_context.h"
31 #include "glsl/ir_optimization.h"
32 #include "glsl/glsl_parser_extras.h"
33 #include "main/shaderapi.h"
36 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
38 struct brw_context
*brw
= (struct brw_context
*)data
;
43 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
44 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
45 MESA_DEBUG_TYPE_OTHER
,
46 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
51 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
53 struct brw_context
*brw
= (struct brw_context
*)data
;
58 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
60 va_copy(args_copy
, args
);
61 vfprintf(stderr
, fmt
, args_copy
);
65 if (brw
->perf_debug
) {
67 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
68 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
69 MESA_DEBUG_TYPE_PERFORMANCE
,
70 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
76 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
78 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
80 compiler
->devinfo
= devinfo
;
81 compiler
->shader_debug_log
= shader_debug_log_mesa
;
82 compiler
->shader_perf_log
= shader_perf_log_mesa
;
84 brw_fs_alloc_reg_sets(compiler
);
85 brw_vec4_alloc_reg_set(compiler
);
87 if (devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
))
88 compiler
->scalar_vs
= true;
90 nir_shader_compiler_options
*nir_options
=
91 rzalloc(compiler
, nir_shader_compiler_options
);
92 nir_options
->native_integers
= true;
93 /* In order to help allow for better CSE at the NIR level we tell NIR
94 * to split all ffma instructions during opt_algebraic and we then
95 * re-combine them as a later step.
97 nir_options
->lower_ffma
= true;
98 nir_options
->lower_sub
= true;
100 /* We want the GLSL compiler to emit code that uses condition codes */
101 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
102 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
103 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
104 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
106 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
107 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
108 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
109 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
110 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
=
111 (i
== MESA_SHADER_FRAGMENT
);
112 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
=
113 (i
== MESA_SHADER_FRAGMENT
);
114 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
115 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
117 /* !ARB_gpu_shader5 */
118 if (devinfo
->gen
< 7)
119 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
122 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].OptimizeForAOS
= true;
123 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].OptimizeForAOS
= true;
125 if (compiler
->scalar_vs
) {
126 /* If we're using the scalar backend for vertex shaders, we need to
127 * configure these accordingly.
129 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].EmitNoIndirectOutput
= true;
130 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].EmitNoIndirectTemp
= true;
131 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].OptimizeForAOS
= false;
133 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].NirOptions
= nir_options
;
136 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
= nir_options
;
137 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
].NirOptions
= nir_options
;
143 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
145 struct brw_shader
*shader
;
147 shader
= rzalloc(NULL
, struct brw_shader
);
149 shader
->base
.Type
= type
;
150 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
151 shader
->base
.Name
= name
;
152 _mesa_init_shader(ctx
, &shader
->base
);
155 return &shader
->base
;
159 * Performs a compile of the shader stages even when we don't know
160 * what non-orthogonal state will be set, in the hope that it reflects
161 * the eventual NOS used, and thus allows us to produce link failures.
164 brw_shader_precompile(struct gl_context
*ctx
,
165 struct gl_shader_program
*sh_prog
)
167 struct gl_shader
*vs
= sh_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
168 struct gl_shader
*gs
= sh_prog
->_LinkedShaders
[MESA_SHADER_GEOMETRY
];
169 struct gl_shader
*fs
= sh_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
170 struct gl_shader
*cs
= sh_prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
];
172 if (fs
&& !brw_fs_precompile(ctx
, sh_prog
, fs
->Program
))
175 if (gs
&& !brw_gs_precompile(ctx
, sh_prog
, gs
->Program
))
178 if (vs
&& !brw_vs_precompile(ctx
, sh_prog
, vs
->Program
))
181 if (cs
&& !brw_cs_precompile(ctx
, sh_prog
, cs
->Program
))
188 is_scalar_shader_stage(struct brw_context
*brw
, int stage
)
191 case MESA_SHADER_FRAGMENT
:
193 case MESA_SHADER_VERTEX
:
194 return brw
->intelScreen
->compiler
->scalar_vs
;
201 brw_lower_packing_builtins(struct brw_context
*brw
,
202 gl_shader_stage shader_type
,
205 int ops
= LOWER_PACK_SNORM_2x16
206 | LOWER_UNPACK_SNORM_2x16
207 | LOWER_PACK_UNORM_2x16
208 | LOWER_UNPACK_UNORM_2x16
;
210 if (is_scalar_shader_stage(brw
, shader_type
)) {
211 ops
|= LOWER_UNPACK_UNORM_4x8
212 | LOWER_UNPACK_SNORM_4x8
213 | LOWER_PACK_UNORM_4x8
214 | LOWER_PACK_SNORM_4x8
;
218 /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
219 * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
220 * lowering is needed. For SOA code, the Half2x16 ops must be
223 if (is_scalar_shader_stage(brw
, shader_type
)) {
224 ops
|= LOWER_PACK_HALF_2x16_TO_SPLIT
225 | LOWER_UNPACK_HALF_2x16_TO_SPLIT
;
228 ops
|= LOWER_PACK_HALF_2x16
229 | LOWER_UNPACK_HALF_2x16
;
232 lower_packing_builtins(ir
, ops
);
236 process_glsl_ir(gl_shader_stage stage
,
237 struct brw_context
*brw
,
238 struct gl_shader_program
*shader_prog
,
239 struct gl_shader
*shader
)
241 struct gl_context
*ctx
= &brw
->ctx
;
242 const struct gl_shader_compiler_options
*options
=
243 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
245 /* Temporary memory context for any new IR. */
246 void *mem_ctx
= ralloc_context(NULL
);
248 ralloc_adopt(mem_ctx
, shader
->ir
);
250 /* lower_packing_builtins() inserts arithmetic instructions, so it
251 * must precede lower_instructions().
253 brw_lower_packing_builtins(brw
, shader
->Stage
, shader
->ir
);
254 do_mat_op_to_vec(shader
->ir
);
255 const int bitfield_insert
= brw
->gen
>= 7 ? BITFIELD_INSERT_TO_BFM_BFI
: 0;
256 lower_instructions(shader
->ir
,
267 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
268 * if-statements need to be flattened.
271 lower_if_to_cond_assign(shader
->ir
, 16);
273 do_lower_texture_projection(shader
->ir
);
274 brw_lower_texture_gradients(brw
, shader
->ir
);
275 do_vec_index_to_cond_assign(shader
->ir
);
276 lower_vector_insert(shader
->ir
, true);
277 if (options
->NirOptions
== NULL
)
278 brw_do_cubemap_normalize(shader
->ir
);
279 lower_offset_arrays(shader
->ir
);
280 brw_do_lower_unnormalized_offset(shader
->ir
);
281 lower_noise(shader
->ir
);
282 lower_quadop_vector(shader
->ir
, false);
284 bool lowered_variable_indexing
=
285 lower_variable_index_to_cond_assign((gl_shader_stage
)stage
,
287 options
->EmitNoIndirectInput
,
288 options
->EmitNoIndirectOutput
,
289 options
->EmitNoIndirectTemp
,
290 options
->EmitNoIndirectUniform
);
292 if (unlikely(brw
->perf_debug
&& lowered_variable_indexing
)) {
293 perf_debug("Unsupported form of variable indexing in %s; falling "
294 "back to very inefficient code generation\n",
295 _mesa_shader_stage_to_abbrev(shader
->Stage
));
298 lower_ubo_reference(shader
, shader
->ir
);
304 if (is_scalar_shader_stage(brw
, shader
->Stage
)) {
305 brw_do_channel_expressions(shader
->ir
);
306 brw_do_vector_splitting(shader
->ir
);
309 progress
= do_lower_jumps(shader
->ir
, true, true,
310 true, /* main return */
311 false, /* continue */
315 progress
= do_common_optimization(shader
->ir
, true, true,
316 options
, ctx
->Const
.NativeIntegers
) || progress
;
319 if (options
->NirOptions
!= NULL
)
320 lower_output_reads(stage
, shader
->ir
);
322 validate_ir_tree(shader
->ir
);
324 /* Now that we've finished altering the linked IR, reparent any live IR back
325 * to the permanent memory context, and free the temporary one (discarding any
326 * junk we optimized away).
328 reparent_ir(shader
->ir
, shader
->ir
);
329 ralloc_free(mem_ctx
);
331 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
332 fprintf(stderr
, "\n");
333 fprintf(stderr
, "GLSL IR for linked %s program %d:\n",
334 _mesa_shader_stage_to_string(shader
->Stage
),
336 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
337 fprintf(stderr
, "\n");
342 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*shProg
)
344 struct brw_context
*brw
= brw_context(ctx
);
347 for (stage
= 0; stage
< ARRAY_SIZE(shProg
->_LinkedShaders
); stage
++) {
348 struct gl_shader
*shader
= shProg
->_LinkedShaders
[stage
];
349 const struct gl_shader_compiler_options
*options
=
350 &ctx
->Const
.ShaderCompilerOptions
[stage
];
355 struct gl_program
*prog
=
356 ctx
->Driver
.NewProgram(ctx
, _mesa_shader_stage_to_program(stage
),
360 prog
->Parameters
= _mesa_new_parameter_list();
362 _mesa_copy_linked_program_data((gl_shader_stage
) stage
, shProg
, prog
);
364 process_glsl_ir((gl_shader_stage
) stage
, brw
, shProg
, shader
);
366 /* Make a pass over the IR to add state references for any built-in
367 * uniforms that are used. This has to be done now (during linking).
368 * Code generation doesn't happen until the first time this shader is
369 * used for rendering. Waiting until then to generate the parameters is
370 * too late. At that point, the values for the built-in uniforms won't
371 * get sent to the shader.
373 foreach_in_list(ir_instruction
, node
, shader
->ir
) {
374 ir_variable
*var
= node
->as_variable();
376 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
377 || (strncmp(var
->name
, "gl_", 3) != 0))
380 const ir_state_slot
*const slots
= var
->get_state_slots();
381 assert(slots
!= NULL
);
383 for (unsigned int i
= 0; i
< var
->get_num_state_slots(); i
++) {
384 _mesa_add_state_reference(prog
->Parameters
,
385 (gl_state_index
*) slots
[i
].tokens
);
389 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
391 prog
->SamplersUsed
= shader
->active_samplers
;
392 prog
->ShadowSamplers
= shader
->shadow_samplers
;
393 _mesa_update_shader_textures_used(shProg
, prog
);
395 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
397 brw_add_texrect_params(prog
);
399 if (options
->NirOptions
)
400 prog
->nir
= brw_create_nir(brw
, shProg
, prog
, (gl_shader_stage
) stage
);
402 _mesa_reference_program(ctx
, &prog
, NULL
);
405 if ((ctx
->_Shader
->Flags
& GLSL_DUMP
) && shProg
->Name
!= 0) {
406 for (unsigned i
= 0; i
< shProg
->NumShaders
; i
++) {
407 const struct gl_shader
*sh
= shProg
->Shaders
[i
];
411 fprintf(stderr
, "GLSL %s shader %d source for linked program %d:\n",
412 _mesa_shader_stage_to_string(sh
->Stage
),
414 fprintf(stderr
, "%s", sh
->Source
);
415 fprintf(stderr
, "\n");
419 if (brw
->precompile
&& !brw_shader_precompile(ctx
, shProg
))
427 brw_type_for_base_type(const struct glsl_type
*type
)
429 switch (type
->base_type
) {
430 case GLSL_TYPE_FLOAT
:
431 return BRW_REGISTER_TYPE_F
;
434 case GLSL_TYPE_SUBROUTINE
:
435 return BRW_REGISTER_TYPE_D
;
437 return BRW_REGISTER_TYPE_UD
;
438 case GLSL_TYPE_ARRAY
:
439 return brw_type_for_base_type(type
->fields
.array
);
440 case GLSL_TYPE_STRUCT
:
441 case GLSL_TYPE_SAMPLER
:
442 case GLSL_TYPE_ATOMIC_UINT
:
443 /* These should be overridden with the type of the member when
444 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
445 * way to trip up if we don't.
447 return BRW_REGISTER_TYPE_UD
;
448 case GLSL_TYPE_IMAGE
:
449 return BRW_REGISTER_TYPE_UD
;
451 case GLSL_TYPE_ERROR
:
452 case GLSL_TYPE_INTERFACE
:
453 case GLSL_TYPE_DOUBLE
:
454 unreachable("not reached");
457 return BRW_REGISTER_TYPE_F
;
460 enum brw_conditional_mod
461 brw_conditional_for_comparison(unsigned int op
)
465 return BRW_CONDITIONAL_L
;
466 case ir_binop_greater
:
467 return BRW_CONDITIONAL_G
;
468 case ir_binop_lequal
:
469 return BRW_CONDITIONAL_LE
;
470 case ir_binop_gequal
:
471 return BRW_CONDITIONAL_GE
;
473 case ir_binop_all_equal
: /* same as equal for scalars */
474 return BRW_CONDITIONAL_Z
;
475 case ir_binop_nequal
:
476 case ir_binop_any_nequal
: /* same as nequal for scalars */
477 return BRW_CONDITIONAL_NZ
;
479 unreachable("not reached: bad operation for comparison");
484 brw_math_function(enum opcode op
)
487 case SHADER_OPCODE_RCP
:
488 return BRW_MATH_FUNCTION_INV
;
489 case SHADER_OPCODE_RSQ
:
490 return BRW_MATH_FUNCTION_RSQ
;
491 case SHADER_OPCODE_SQRT
:
492 return BRW_MATH_FUNCTION_SQRT
;
493 case SHADER_OPCODE_EXP2
:
494 return BRW_MATH_FUNCTION_EXP
;
495 case SHADER_OPCODE_LOG2
:
496 return BRW_MATH_FUNCTION_LOG
;
497 case SHADER_OPCODE_POW
:
498 return BRW_MATH_FUNCTION_POW
;
499 case SHADER_OPCODE_SIN
:
500 return BRW_MATH_FUNCTION_SIN
;
501 case SHADER_OPCODE_COS
:
502 return BRW_MATH_FUNCTION_COS
;
503 case SHADER_OPCODE_INT_QUOTIENT
:
504 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
505 case SHADER_OPCODE_INT_REMAINDER
:
506 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
508 unreachable("not reached: unknown math function");
513 brw_texture_offset(int *offsets
, unsigned num_components
)
515 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
517 /* Combine all three offsets into a single unsigned dword:
519 * bits 11:8 - U Offset (X component)
520 * bits 7:4 - V Offset (Y component)
521 * bits 3:0 - R Offset (Z component)
523 unsigned offset_bits
= 0;
524 for (unsigned i
= 0; i
< num_components
; i
++) {
525 const unsigned shift
= 4 * (2 - i
);
526 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
532 brw_instruction_name(enum opcode op
)
535 case BRW_OPCODE_MOV
... BRW_OPCODE_NOP
:
536 assert(opcode_descs
[op
].name
);
537 return opcode_descs
[op
].name
;
538 case FS_OPCODE_FB_WRITE
:
540 case FS_OPCODE_FB_WRITE_LOGICAL
:
541 return "fb_write_logical";
542 case FS_OPCODE_BLORP_FB_WRITE
:
543 return "blorp_fb_write";
544 case FS_OPCODE_REP_FB_WRITE
:
545 return "rep_fb_write";
547 case SHADER_OPCODE_RCP
:
549 case SHADER_OPCODE_RSQ
:
551 case SHADER_OPCODE_SQRT
:
553 case SHADER_OPCODE_EXP2
:
555 case SHADER_OPCODE_LOG2
:
557 case SHADER_OPCODE_POW
:
559 case SHADER_OPCODE_INT_QUOTIENT
:
561 case SHADER_OPCODE_INT_REMAINDER
:
563 case SHADER_OPCODE_SIN
:
565 case SHADER_OPCODE_COS
:
568 case SHADER_OPCODE_TEX
:
570 case SHADER_OPCODE_TEX_LOGICAL
:
571 return "tex_logical";
572 case SHADER_OPCODE_TXD
:
574 case SHADER_OPCODE_TXD_LOGICAL
:
575 return "txd_logical";
576 case SHADER_OPCODE_TXF
:
578 case SHADER_OPCODE_TXF_LOGICAL
:
579 return "txf_logical";
580 case SHADER_OPCODE_TXL
:
582 case SHADER_OPCODE_TXL_LOGICAL
:
583 return "txl_logical";
584 case SHADER_OPCODE_TXS
:
586 case SHADER_OPCODE_TXS_LOGICAL
:
587 return "txs_logical";
590 case FS_OPCODE_TXB_LOGICAL
:
591 return "txb_logical";
592 case SHADER_OPCODE_TXF_CMS
:
594 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
595 return "txf_cms_logical";
596 case SHADER_OPCODE_TXF_UMS
:
598 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
599 return "txf_ums_logical";
600 case SHADER_OPCODE_TXF_MCS
:
602 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
603 return "txf_mcs_logical";
604 case SHADER_OPCODE_LOD
:
606 case SHADER_OPCODE_LOD_LOGICAL
:
607 return "lod_logical";
608 case SHADER_OPCODE_TG4
:
610 case SHADER_OPCODE_TG4_LOGICAL
:
611 return "tg4_logical";
612 case SHADER_OPCODE_TG4_OFFSET
:
614 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
615 return "tg4_offset_logical";
617 case SHADER_OPCODE_SHADER_TIME_ADD
:
618 return "shader_time_add";
620 case SHADER_OPCODE_UNTYPED_ATOMIC
:
621 return "untyped_atomic";
622 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
623 return "untyped_surface_read";
624 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
625 return "untyped_surface_write";
626 case SHADER_OPCODE_TYPED_ATOMIC
:
627 return "typed_atomic";
628 case SHADER_OPCODE_TYPED_SURFACE_READ
:
629 return "typed_surface_read";
630 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
631 return "typed_surface_write";
632 case SHADER_OPCODE_MEMORY_FENCE
:
633 return "memory_fence";
635 case SHADER_OPCODE_LOAD_PAYLOAD
:
636 return "load_payload";
638 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
639 return "gen4_scratch_read";
640 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
641 return "gen4_scratch_write";
642 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
643 return "gen7_scratch_read";
644 case SHADER_OPCODE_URB_WRITE_SIMD8
:
645 return "gen8_urb_write_simd8";
647 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
648 return "find_live_channel";
649 case SHADER_OPCODE_BROADCAST
:
652 case VEC4_OPCODE_MOV_BYTES
:
654 case VEC4_OPCODE_PACK_BYTES
:
656 case VEC4_OPCODE_UNPACK_UNIFORM
:
657 return "unpack_uniform";
659 case FS_OPCODE_DDX_COARSE
:
661 case FS_OPCODE_DDX_FINE
:
663 case FS_OPCODE_DDY_COARSE
:
665 case FS_OPCODE_DDY_FINE
:
668 case FS_OPCODE_CINTERP
:
670 case FS_OPCODE_LINTERP
:
673 case FS_OPCODE_PIXEL_X
:
675 case FS_OPCODE_PIXEL_Y
:
678 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
679 return "uniform_pull_const";
680 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
681 return "uniform_pull_const_gen7";
682 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
683 return "varying_pull_const";
684 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
685 return "varying_pull_const_gen7";
687 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
688 return "mov_dispatch_to_flags";
689 case FS_OPCODE_DISCARD_JUMP
:
690 return "discard_jump";
692 case FS_OPCODE_SET_SAMPLE_ID
:
693 return "set_sample_id";
694 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
695 return "set_simd4x2_offset";
697 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
698 return "pack_half_2x16_split";
699 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
700 return "unpack_half_2x16_split_x";
701 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
702 return "unpack_half_2x16_split_y";
704 case FS_OPCODE_PLACEHOLDER_HALT
:
705 return "placeholder_halt";
707 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
708 return "interp_centroid";
709 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
710 return "interp_sample";
711 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
712 return "interp_shared_offset";
713 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
714 return "interp_per_slot_offset";
716 case VS_OPCODE_URB_WRITE
:
717 return "vs_urb_write";
718 case VS_OPCODE_PULL_CONSTANT_LOAD
:
719 return "pull_constant_load";
720 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
721 return "pull_constant_load_gen7";
723 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
724 return "set_simd4x2_header_gen9";
726 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
727 return "unpack_flags_simd4x2";
729 case GS_OPCODE_URB_WRITE
:
730 return "gs_urb_write";
731 case GS_OPCODE_URB_WRITE_ALLOCATE
:
732 return "gs_urb_write_allocate";
733 case GS_OPCODE_THREAD_END
:
734 return "gs_thread_end";
735 case GS_OPCODE_SET_WRITE_OFFSET
:
736 return "set_write_offset";
737 case GS_OPCODE_SET_VERTEX_COUNT
:
738 return "set_vertex_count";
739 case GS_OPCODE_SET_DWORD_2
:
740 return "set_dword_2";
741 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
742 return "prepare_channel_masks";
743 case GS_OPCODE_SET_CHANNEL_MASKS
:
744 return "set_channel_masks";
745 case GS_OPCODE_GET_INSTANCE_ID
:
746 return "get_instance_id";
747 case GS_OPCODE_FF_SYNC
:
749 case GS_OPCODE_SET_PRIMITIVE_ID
:
750 return "set_primitive_id";
751 case GS_OPCODE_SVB_WRITE
:
752 return "gs_svb_write";
753 case GS_OPCODE_SVB_SET_DST_INDEX
:
754 return "gs_svb_set_dst_index";
755 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
756 return "gs_ff_sync_set_primitives";
757 case CS_OPCODE_CS_TERMINATE
:
758 return "cs_terminate";
759 case SHADER_OPCODE_BARRIER
:
763 unreachable("not reached");
767 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
773 } imm
= { reg
->dw1
.ud
}, sat_imm
= { 0 };
776 case BRW_REGISTER_TYPE_UD
:
777 case BRW_REGISTER_TYPE_D
:
778 case BRW_REGISTER_TYPE_UQ
:
779 case BRW_REGISTER_TYPE_Q
:
782 case BRW_REGISTER_TYPE_UW
:
783 sat_imm
.ud
= CLAMP(imm
.ud
, 0, USHRT_MAX
);
785 case BRW_REGISTER_TYPE_W
:
786 sat_imm
.d
= CLAMP(imm
.d
, SHRT_MIN
, SHRT_MAX
);
788 case BRW_REGISTER_TYPE_F
:
789 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
791 case BRW_REGISTER_TYPE_UB
:
792 case BRW_REGISTER_TYPE_B
:
793 unreachable("no UB/B immediates");
794 case BRW_REGISTER_TYPE_V
:
795 case BRW_REGISTER_TYPE_UV
:
796 case BRW_REGISTER_TYPE_VF
:
797 unreachable("unimplemented: saturate vector immediate");
798 case BRW_REGISTER_TYPE_DF
:
799 case BRW_REGISTER_TYPE_HF
:
800 unreachable("unimplemented: saturate DF/HF immediate");
803 if (imm
.ud
!= sat_imm
.ud
) {
804 reg
->dw1
.ud
= sat_imm
.ud
;
811 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
814 case BRW_REGISTER_TYPE_D
:
815 case BRW_REGISTER_TYPE_UD
:
816 reg
->dw1
.d
= -reg
->dw1
.d
;
818 case BRW_REGISTER_TYPE_W
:
819 case BRW_REGISTER_TYPE_UW
:
820 reg
->dw1
.d
= -(int16_t)reg
->dw1
.ud
;
822 case BRW_REGISTER_TYPE_F
:
823 reg
->dw1
.f
= -reg
->dw1
.f
;
825 case BRW_REGISTER_TYPE_VF
:
826 reg
->dw1
.ud
^= 0x80808080;
828 case BRW_REGISTER_TYPE_UB
:
829 case BRW_REGISTER_TYPE_B
:
830 unreachable("no UB/B immediates");
831 case BRW_REGISTER_TYPE_UV
:
832 case BRW_REGISTER_TYPE_V
:
833 assert(!"unimplemented: negate UV/V immediate");
834 case BRW_REGISTER_TYPE_UQ
:
835 case BRW_REGISTER_TYPE_Q
:
836 assert(!"unimplemented: negate UQ/Q immediate");
837 case BRW_REGISTER_TYPE_DF
:
838 case BRW_REGISTER_TYPE_HF
:
839 assert(!"unimplemented: negate DF/HF immediate");
846 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
849 case BRW_REGISTER_TYPE_D
:
850 reg
->dw1
.d
= abs(reg
->dw1
.d
);
852 case BRW_REGISTER_TYPE_W
:
853 reg
->dw1
.d
= abs((int16_t)reg
->dw1
.ud
);
855 case BRW_REGISTER_TYPE_F
:
856 reg
->dw1
.f
= fabsf(reg
->dw1
.f
);
858 case BRW_REGISTER_TYPE_VF
:
859 reg
->dw1
.ud
&= ~0x80808080;
861 case BRW_REGISTER_TYPE_UB
:
862 case BRW_REGISTER_TYPE_B
:
863 unreachable("no UB/B immediates");
864 case BRW_REGISTER_TYPE_UQ
:
865 case BRW_REGISTER_TYPE_UD
:
866 case BRW_REGISTER_TYPE_UW
:
867 case BRW_REGISTER_TYPE_UV
:
868 /* Presumably the absolute value modifier on an unsigned source is a
869 * nop, but it would be nice to confirm.
871 assert(!"unimplemented: abs unsigned immediate");
872 case BRW_REGISTER_TYPE_V
:
873 assert(!"unimplemented: abs V immediate");
874 case BRW_REGISTER_TYPE_Q
:
875 assert(!"unimplemented: abs Q immediate");
876 case BRW_REGISTER_TYPE_DF
:
877 case BRW_REGISTER_TYPE_HF
:
878 assert(!"unimplemented: abs DF/HF immediate");
884 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
887 struct gl_shader_program
*shader_prog
,
888 struct gl_program
*prog
,
889 struct brw_stage_prog_data
*stage_prog_data
,
890 gl_shader_stage stage
)
891 : compiler(compiler
),
893 devinfo(compiler
->devinfo
),
895 (struct brw_shader
*)shader_prog
->_LinkedShaders
[stage
] : NULL
),
896 shader_prog(shader_prog
),
898 stage_prog_data(stage_prog_data
),
903 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
904 stage_name
= _mesa_shader_stage_to_string(stage
);
905 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
909 backend_reg::is_zero() const
914 return fixed_hw_reg
.dw1
.d
== 0;
918 backend_reg::is_one() const
923 return type
== BRW_REGISTER_TYPE_F
924 ? fixed_hw_reg
.dw1
.f
== 1.0
925 : fixed_hw_reg
.dw1
.d
== 1;
929 backend_reg::is_negative_one() const
935 case BRW_REGISTER_TYPE_F
:
936 return fixed_hw_reg
.dw1
.f
== -1.0;
937 case BRW_REGISTER_TYPE_D
:
938 return fixed_hw_reg
.dw1
.d
== -1;
945 backend_reg::is_null() const
947 return file
== HW_REG
&&
948 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
949 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
954 backend_reg::is_accumulator() const
956 return file
== HW_REG
&&
957 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
958 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
962 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
964 return (file
== r
.file
&&
966 reg_offset
>= r
.reg_offset
&&
967 reg_offset
< r
.reg_offset
+ n
);
971 backend_instruction::is_commutative() const
981 /* MIN and MAX are commutative. */
982 if (conditional_mod
== BRW_CONDITIONAL_GE
||
983 conditional_mod
== BRW_CONDITIONAL_L
) {
993 backend_instruction::is_3src() const
995 return opcode
< ARRAY_SIZE(opcode_descs
) && opcode_descs
[opcode
].nsrc
== 3;
999 backend_instruction::is_tex() const
1001 return (opcode
== SHADER_OPCODE_TEX
||
1002 opcode
== FS_OPCODE_TXB
||
1003 opcode
== SHADER_OPCODE_TXD
||
1004 opcode
== SHADER_OPCODE_TXF
||
1005 opcode
== SHADER_OPCODE_TXF_CMS
||
1006 opcode
== SHADER_OPCODE_TXF_UMS
||
1007 opcode
== SHADER_OPCODE_TXF_MCS
||
1008 opcode
== SHADER_OPCODE_TXL
||
1009 opcode
== SHADER_OPCODE_TXS
||
1010 opcode
== SHADER_OPCODE_LOD
||
1011 opcode
== SHADER_OPCODE_TG4
||
1012 opcode
== SHADER_OPCODE_TG4_OFFSET
);
1016 backend_instruction::is_math() const
1018 return (opcode
== SHADER_OPCODE_RCP
||
1019 opcode
== SHADER_OPCODE_RSQ
||
1020 opcode
== SHADER_OPCODE_SQRT
||
1021 opcode
== SHADER_OPCODE_EXP2
||
1022 opcode
== SHADER_OPCODE_LOG2
||
1023 opcode
== SHADER_OPCODE_SIN
||
1024 opcode
== SHADER_OPCODE_COS
||
1025 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
1026 opcode
== SHADER_OPCODE_INT_REMAINDER
||
1027 opcode
== SHADER_OPCODE_POW
);
1031 backend_instruction::is_control_flow() const
1035 case BRW_OPCODE_WHILE
:
1037 case BRW_OPCODE_ELSE
:
1038 case BRW_OPCODE_ENDIF
:
1039 case BRW_OPCODE_BREAK
:
1040 case BRW_OPCODE_CONTINUE
:
1048 backend_instruction::can_do_source_mods() const
1051 case BRW_OPCODE_ADDC
:
1052 case BRW_OPCODE_BFE
:
1053 case BRW_OPCODE_BFI1
:
1054 case BRW_OPCODE_BFI2
:
1055 case BRW_OPCODE_BFREV
:
1056 case BRW_OPCODE_CBIT
:
1057 case BRW_OPCODE_FBH
:
1058 case BRW_OPCODE_FBL
:
1059 case BRW_OPCODE_SUBB
:
1067 backend_instruction::can_do_saturate() const
1070 case BRW_OPCODE_ADD
:
1071 case BRW_OPCODE_ASR
:
1072 case BRW_OPCODE_AVG
:
1073 case BRW_OPCODE_DP2
:
1074 case BRW_OPCODE_DP3
:
1075 case BRW_OPCODE_DP4
:
1076 case BRW_OPCODE_DPH
:
1077 case BRW_OPCODE_F16TO32
:
1078 case BRW_OPCODE_F32TO16
:
1079 case BRW_OPCODE_LINE
:
1080 case BRW_OPCODE_LRP
:
1081 case BRW_OPCODE_MAC
:
1082 case BRW_OPCODE_MAD
:
1083 case BRW_OPCODE_MATH
:
1084 case BRW_OPCODE_MOV
:
1085 case BRW_OPCODE_MUL
:
1086 case BRW_OPCODE_PLN
:
1087 case BRW_OPCODE_RNDD
:
1088 case BRW_OPCODE_RNDE
:
1089 case BRW_OPCODE_RNDU
:
1090 case BRW_OPCODE_RNDZ
:
1091 case BRW_OPCODE_SEL
:
1092 case BRW_OPCODE_SHL
:
1093 case BRW_OPCODE_SHR
:
1094 case FS_OPCODE_LINTERP
:
1095 case SHADER_OPCODE_COS
:
1096 case SHADER_OPCODE_EXP2
:
1097 case SHADER_OPCODE_LOG2
:
1098 case SHADER_OPCODE_POW
:
1099 case SHADER_OPCODE_RCP
:
1100 case SHADER_OPCODE_RSQ
:
1101 case SHADER_OPCODE_SIN
:
1102 case SHADER_OPCODE_SQRT
:
1110 backend_instruction::can_do_cmod() const
1113 case BRW_OPCODE_ADD
:
1114 case BRW_OPCODE_ADDC
:
1115 case BRW_OPCODE_AND
:
1116 case BRW_OPCODE_ASR
:
1117 case BRW_OPCODE_AVG
:
1118 case BRW_OPCODE_CMP
:
1119 case BRW_OPCODE_CMPN
:
1120 case BRW_OPCODE_DP2
:
1121 case BRW_OPCODE_DP3
:
1122 case BRW_OPCODE_DP4
:
1123 case BRW_OPCODE_DPH
:
1124 case BRW_OPCODE_F16TO32
:
1125 case BRW_OPCODE_F32TO16
:
1126 case BRW_OPCODE_FRC
:
1127 case BRW_OPCODE_LINE
:
1128 case BRW_OPCODE_LRP
:
1129 case BRW_OPCODE_LZD
:
1130 case BRW_OPCODE_MAC
:
1131 case BRW_OPCODE_MACH
:
1132 case BRW_OPCODE_MAD
:
1133 case BRW_OPCODE_MOV
:
1134 case BRW_OPCODE_MUL
:
1135 case BRW_OPCODE_NOT
:
1137 case BRW_OPCODE_PLN
:
1138 case BRW_OPCODE_RNDD
:
1139 case BRW_OPCODE_RNDE
:
1140 case BRW_OPCODE_RNDU
:
1141 case BRW_OPCODE_RNDZ
:
1142 case BRW_OPCODE_SAD2
:
1143 case BRW_OPCODE_SADA2
:
1144 case BRW_OPCODE_SHL
:
1145 case BRW_OPCODE_SHR
:
1146 case BRW_OPCODE_SUBB
:
1147 case BRW_OPCODE_XOR
:
1148 case FS_OPCODE_CINTERP
:
1149 case FS_OPCODE_LINTERP
:
1157 backend_instruction::reads_accumulator_implicitly() const
1160 case BRW_OPCODE_MAC
:
1161 case BRW_OPCODE_MACH
:
1162 case BRW_OPCODE_SADA2
:
1170 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
1172 return writes_accumulator
||
1173 (devinfo
->gen
< 6 &&
1174 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
1175 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
1176 opcode
!= FS_OPCODE_CINTERP
)));
1180 backend_instruction::has_side_effects() const
1183 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1184 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1185 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1186 case SHADER_OPCODE_TYPED_ATOMIC
:
1187 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1188 case SHADER_OPCODE_MEMORY_FENCE
:
1189 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1190 case FS_OPCODE_FB_WRITE
:
1191 case SHADER_OPCODE_BARRIER
:
1200 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1203 foreach_inst_in_block (backend_instruction
, i
, block
) {
1213 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1215 for (bblock_t
*block_iter
= start_block
->next();
1216 !block_iter
->link
.is_tail_sentinel();
1217 block_iter
= block_iter
->next()) {
1218 block_iter
->start_ip
+= ip_adjustment
;
1219 block_iter
->end_ip
+= ip_adjustment
;
1224 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1226 if (!this->is_head_sentinel())
1227 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1231 adjust_later_block_ips(block
, 1);
1233 exec_node::insert_after(inst
);
1237 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1239 if (!this->is_tail_sentinel())
1240 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1244 adjust_later_block_ips(block
, 1);
1246 exec_node::insert_before(inst
);
1250 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1252 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1254 unsigned num_inst
= list
->length();
1256 block
->end_ip
+= num_inst
;
1258 adjust_later_block_ips(block
, num_inst
);
1260 exec_node::insert_before(list
);
1264 backend_instruction::remove(bblock_t
*block
)
1266 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1268 adjust_later_block_ips(block
, -1);
1270 if (block
->start_ip
== block
->end_ip
) {
1271 block
->cfg
->remove_block(block
);
1276 exec_node::remove();
1280 backend_shader::dump_instructions()
1282 dump_instructions(NULL
);
1286 backend_shader::dump_instructions(const char *name
)
1288 FILE *file
= stderr
;
1289 if (name
&& geteuid() != 0) {
1290 file
= fopen(name
, "w");
1297 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1298 fprintf(file
, "%4d: ", ip
++);
1299 dump_instruction(inst
, file
);
1303 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1304 fprintf(file
, "%4d: ", ip
++);
1305 dump_instruction(inst
, file
);
1309 if (file
!= stderr
) {
1315 backend_shader::calculate_cfg()
1319 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1323 backend_shader::invalidate_cfg()
1325 ralloc_free(this->cfg
);
1330 * Sets up the starting offsets for the groups of binding table entries
1331 * commong to all pipeline stages.
1333 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1334 * unused but also make sure that addition of small offsets to them will
1335 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1338 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset
)
1340 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1342 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1343 next_binding_table_offset
+= num_textures
;
1346 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1347 next_binding_table_offset
+= shader
->base
.NumUniformBlocks
;
1349 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1352 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1353 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1354 next_binding_table_offset
++;
1356 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1359 if (prog
->UsesGather
) {
1360 if (devinfo
->gen
>= 8) {
1361 stage_prog_data
->binding_table
.gather_texture_start
=
1362 stage_prog_data
->binding_table
.texture_start
;
1364 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1365 next_binding_table_offset
+= num_textures
;
1368 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1371 if (shader_prog
&& shader_prog
->NumAtomicBuffers
) {
1372 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1373 next_binding_table_offset
+= shader_prog
->NumAtomicBuffers
;
1375 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1378 if (shader
&& shader
->base
.NumImages
) {
1379 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1380 next_binding_table_offset
+= shader
->base
.NumImages
;
1382 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1385 /* This may or may not be used depending on how the compile goes. */
1386 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1387 next_binding_table_offset
++;
1389 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1391 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */