src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 static bool
  76 is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80    case MESA_SHADER_COMPUTE:
  81       return true;
  82    case MESA_SHADER_VERTEX:
  83       return compiler->scalar_vs;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 struct brw_compiler *
  90 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  91 {
  92    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  93
  94    compiler->devinfo = devinfo;
  95    compiler->shader_debug_log = shader_debug_log_mesa;
  96    compiler->shader_perf_log = shader_perf_log_mesa;
  97
  98    brw_fs_alloc_reg_sets(compiler);
  99    brw_vec4_alloc_reg_set(compiler);
 100
 101    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
 102       compiler->scalar_vs = true;
 103
 104    nir_shader_compiler_options *nir_options =
 105       rzalloc(compiler, nir_shader_compiler_options);
 106    nir_options->native_integers = true;
 107    /* In order to help allow for better CSE at the NIR level we tell NIR
 108     * to split all ffma instructions during opt_algebraic and we then
 109     * re-combine them as a later step.
 110     */
 111    nir_options->lower_ffma = true;
 112    nir_options->lower_sub = true;
 113    /* In the vec4 backend, our dpN instruction replicates its result to all
 114     * the components of a vec4.  We would like NIR to give us replicated fdot
 115     * instructions because it can optimize better for us.
 116     *
 117     * For the FS backend, it should be lowered away by the scalarizing pass so
 118     * we should never see fdot anyway.
 119     */
 120    nir_options->fdot_replicates = true;
 121
 122    /* We want the GLSL compiler to emit code that uses condition codes */
 123    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 124       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 125       compiler->glsl_compiler_options[i].MaxIfDepth =
 126          devinfo->gen < 6 ? 16 : UINT_MAX;
 127
 128       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 129       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 130       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 132       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 133       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 134
 135       bool is_scalar = is_scalar_shader_stage(compiler, i);
 136
 137       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 138       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 139       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 140
 141       /* !ARB_gpu_shader5 */
 142       if (devinfo->gen < 7)
 143          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 144
 145       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 146    }
 147
 148    return compiler;
 149 }
 150
 151 struct gl_shader *
 152 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 153 {
 154    struct brw_shader *shader;
 155
 156    shader = rzalloc(NULL, struct brw_shader);
 157    if (shader) {
 158       shader->base.Type = type;
 159       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 160       shader->base.Name = name;
 161       _mesa_init_shader(ctx, &shader->base);
 162    }
 163
 164    return &shader->base;
 165 }
 166
 167 /**
 168  * Performs a compile of the shader stages even when we don't know
 169  * what non-orthogonal state will be set, in the hope that it reflects
 170  * the eventual NOS used, and thus allows us to produce link failures.
 171  */
 172 static bool
 173 brw_shader_precompile(struct gl_context *ctx,
 174                       struct gl_shader_program *sh_prog)
 175 {
 176    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 177    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 178    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 179    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 180
 181    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 182       return false;
 183
 184    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 185       return false;
 186
 187    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 188       return false;
 189
 190    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 191       return false;
 192
 193    return true;
 194 }
 195
 196 static void
 197 brw_lower_packing_builtins(struct brw_context *brw,
 198                            gl_shader_stage shader_type,
 199                            exec_list *ir)
 200 {
 201    int ops = LOWER_PACK_SNORM_2x16
 202            | LOWER_UNPACK_SNORM_2x16
 203            | LOWER_PACK_UNORM_2x16
 204            | LOWER_UNPACK_UNORM_2x16;
 205
 206    if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
 207       ops |= LOWER_UNPACK_UNORM_4x8
 208            | LOWER_UNPACK_SNORM_4x8
 209            | LOWER_PACK_UNORM_4x8
 210            | LOWER_PACK_SNORM_4x8;
 211    }
 212
 213    if (brw->gen >= 7) {
 214       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 215        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 216        * lowering is needed. For SOA code, the Half2x16 ops must be
 217        * scalarized.
 218        */
 219       if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
 220          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 221              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 222       }
 223    } else {
 224       ops |= LOWER_PACK_HALF_2x16
 225           |  LOWER_UNPACK_HALF_2x16;
 226    }
 227
 228    lower_packing_builtins(ir, ops);
 229 }
 230
 231 static void
 232 process_glsl_ir(gl_shader_stage stage,
 233                 struct brw_context *brw,
 234                 struct gl_shader_program *shader_prog,
 235                 struct gl_shader *shader)
 236 {
 237    struct gl_context *ctx = &brw->ctx;
 238    const struct gl_shader_compiler_options *options =
 239       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 240
 241    /* Temporary memory context for any new IR. */
 242    void *mem_ctx = ralloc_context(NULL);
 243
 244    ralloc_adopt(mem_ctx, shader->ir);
 245
 246    /* lower_packing_builtins() inserts arithmetic instructions, so it
 247     * must precede lower_instructions().
 248     */
 249    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 250    do_mat_op_to_vec(shader->ir);
 251    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 252    lower_instructions(shader->ir,
 253                       MOD_TO_FLOOR |
 254                       DIV_TO_MUL_RCP |
 255                       SUB_TO_ADD_NEG |
 256                       EXP_TO_EXP2 |
 257                       LOG_TO_LOG2 |
 258                       bitfield_insert |
 259                       LDEXP_TO_ARITH |
 260                       CARRY_TO_ARITH |
 261                       BORROW_TO_ARITH);
 262
 263    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 264     * if-statements need to be flattened.
 265     */
 266    if (brw->gen < 6)
 267       lower_if_to_cond_assign(shader->ir, 16);
 268
 269    do_lower_texture_projection(shader->ir);
 270    brw_lower_texture_gradients(brw, shader->ir);
 271    do_vec_index_to_cond_assign(shader->ir);
 272    lower_vector_insert(shader->ir, true);
 273    lower_offset_arrays(shader->ir);
 274    brw_do_lower_unnormalized_offset(shader->ir);
 275    lower_noise(shader->ir);
 276    lower_quadop_vector(shader->ir, false);
 277
 278    bool lowered_variable_indexing =
 279       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 280                                           shader->ir,
 281                                           options->EmitNoIndirectInput,
 282                                           options->EmitNoIndirectOutput,
 283                                           options->EmitNoIndirectTemp,
 284                                           options->EmitNoIndirectUniform);
 285
 286    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 287       perf_debug("Unsupported form of variable indexing in %s; falling "
 288                  "back to very inefficient code generation\n",
 289                  _mesa_shader_stage_to_abbrev(shader->Stage));
 290    }
 291
 292    lower_ubo_reference(shader, shader->ir);
 293
 294    bool progress;
 295    do {
 296       progress = false;
 297
 298       if (is_scalar_shader_stage(brw->intelScreen->compiler, shader->Stage)) {
 299          brw_do_channel_expressions(shader->ir);
 300          brw_do_vector_splitting(shader->ir);
 301       }
 302
 303       progress = do_lower_jumps(shader->ir, true, true,
 304                                 true, /* main return */
 305                                 false, /* continue */
 306                                 false /* loops */
 307                                 ) || progress;
 308
 309       progress = do_common_optimization(shader->ir, true, true,
 310                                         options, ctx->Const.NativeIntegers) || progress;
 311    } while (progress);
 312
 313    validate_ir_tree(shader->ir);
 314
 315    /* Now that we've finished altering the linked IR, reparent any live IR back
 316     * to the permanent memory context, and free the temporary one (discarding any
 317     * junk we optimized away).
 318     */
 319    reparent_ir(shader->ir, shader->ir);
 320    ralloc_free(mem_ctx);
 321
 322    if (ctx->_Shader->Flags & GLSL_DUMP) {
 323       fprintf(stderr, "\n");
 324       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 325               _mesa_shader_stage_to_string(shader->Stage),
 326               shader_prog->Name);
 327       _mesa_print_ir(stderr, shader->ir, NULL);
 328       fprintf(stderr, "\n");
 329    }
 330 }
 331
 332 GLboolean
 333 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 334 {
 335    struct brw_context *brw = brw_context(ctx);
 336    const struct brw_compiler *compiler = brw->intelScreen->compiler;
 337    unsigned int stage;
 338
 339    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 340       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 341       if (!shader)
 342          continue;
 343
 344       struct gl_program *prog =
 345          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 346                                 shader->Name);
 347       if (!prog)
 348         return false;
 349       prog->Parameters = _mesa_new_parameter_list();
 350
 351       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 352
 353       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 354
 355       /* Make a pass over the IR to add state references for any built-in
 356        * uniforms that are used.  This has to be done now (during linking).
 357        * Code generation doesn't happen until the first time this shader is
 358        * used for rendering.  Waiting until then to generate the parameters is
 359        * too late.  At that point, the values for the built-in uniforms won't
 360        * get sent to the shader.
 361        */
 362       foreach_in_list(ir_instruction, node, shader->ir) {
 363          ir_variable *var = node->as_variable();
 364
 365          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 366              || (strncmp(var->name, "gl_", 3) != 0))
 367             continue;
 368
 369          const ir_state_slot *const slots = var->get_state_slots();
 370          assert(slots != NULL);
 371
 372          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 373             _mesa_add_state_reference(prog->Parameters,
 374                                       (gl_state_index *) slots[i].tokens);
 375          }
 376       }
 377
 378       do_set_program_inouts(shader->ir, prog, shader->Stage);
 379
 380       prog->SamplersUsed = shader->active_samplers;
 381       prog->ShadowSamplers = shader->shadow_samplers;
 382       _mesa_update_shader_textures_used(shProg, prog);
 383
 384       _mesa_reference_program(ctx, &shader->Program, prog);
 385
 386       brw_add_texrect_params(prog);
 387
 388       prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
 389                                  is_scalar_shader_stage(compiler, stage));
 390
 391       _mesa_reference_program(ctx, &prog, NULL);
 392    }
 393
 394    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 395       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 396          const struct gl_shader *sh = shProg->Shaders[i];
 397          if (!sh)
 398             continue;
 399
 400          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 401                  _mesa_shader_stage_to_string(sh->Stage),
 402                  i, shProg->Name);
 403          fprintf(stderr, "%s", sh->Source);
 404          fprintf(stderr, "\n");
 405       }
 406    }
 407
 408    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 409       return false;
 410
 411    return true;
 412 }
 413
 414
 415 enum brw_reg_type
 416 brw_type_for_base_type(const struct glsl_type *type)
 417 {
 418    switch (type->base_type) {
 419    case GLSL_TYPE_FLOAT:
 420       return BRW_REGISTER_TYPE_F;
 421    case GLSL_TYPE_INT:
 422    case GLSL_TYPE_BOOL:
 423    case GLSL_TYPE_SUBROUTINE:
 424       return BRW_REGISTER_TYPE_D;
 425    case GLSL_TYPE_UINT:
 426       return BRW_REGISTER_TYPE_UD;
 427    case GLSL_TYPE_ARRAY:
 428       return brw_type_for_base_type(type->fields.array);
 429    case GLSL_TYPE_STRUCT:
 430    case GLSL_TYPE_SAMPLER:
 431    case GLSL_TYPE_ATOMIC_UINT:
 432       /* These should be overridden with the type of the member when
 433        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 434        * way to trip up if we don't.
 435        */
 436       return BRW_REGISTER_TYPE_UD;
 437    case GLSL_TYPE_IMAGE:
 438       return BRW_REGISTER_TYPE_UD;
 439    case GLSL_TYPE_VOID:
 440    case GLSL_TYPE_ERROR:
 441    case GLSL_TYPE_INTERFACE:
 442    case GLSL_TYPE_DOUBLE:
 443       unreachable("not reached");
 444    }
 445
 446    return BRW_REGISTER_TYPE_F;
 447 }
 448
 449 enum brw_conditional_mod
 450 brw_conditional_for_comparison(unsigned int op)
 451 {
 452    switch (op) {
 453    case ir_binop_less:
 454       return BRW_CONDITIONAL_L;
 455    case ir_binop_greater:
 456       return BRW_CONDITIONAL_G;
 457    case ir_binop_lequal:
 458       return BRW_CONDITIONAL_LE;
 459    case ir_binop_gequal:
 460       return BRW_CONDITIONAL_GE;
 461    case ir_binop_equal:
 462    case ir_binop_all_equal: /* same as equal for scalars */
 463       return BRW_CONDITIONAL_Z;
 464    case ir_binop_nequal:
 465    case ir_binop_any_nequal: /* same as nequal for scalars */
 466       return BRW_CONDITIONAL_NZ;
 467    default:
 468       unreachable("not reached: bad operation for comparison");
 469    }
 470 }
 471
 472 uint32_t
 473 brw_math_function(enum opcode op)
 474 {
 475    switch (op) {
 476    case SHADER_OPCODE_RCP:
 477       return BRW_MATH_FUNCTION_INV;
 478    case SHADER_OPCODE_RSQ:
 479       return BRW_MATH_FUNCTION_RSQ;
 480    case SHADER_OPCODE_SQRT:
 481       return BRW_MATH_FUNCTION_SQRT;
 482    case SHADER_OPCODE_EXP2:
 483       return BRW_MATH_FUNCTION_EXP;
 484    case SHADER_OPCODE_LOG2:
 485       return BRW_MATH_FUNCTION_LOG;
 486    case SHADER_OPCODE_POW:
 487       return BRW_MATH_FUNCTION_POW;
 488    case SHADER_OPCODE_SIN:
 489       return BRW_MATH_FUNCTION_SIN;
 490    case SHADER_OPCODE_COS:
 491       return BRW_MATH_FUNCTION_COS;
 492    case SHADER_OPCODE_INT_QUOTIENT:
 493       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 494    case SHADER_OPCODE_INT_REMAINDER:
 495       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 496    default:
 497       unreachable("not reached: unknown math function");
 498    }
 499 }
 500
 501 uint32_t
 502 brw_texture_offset(int *offsets, unsigned num_components)
 503 {
 504    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 505
 506    /* Combine all three offsets into a single unsigned dword:
 507     *
 508     *    bits 11:8 - U Offset (X component)
 509     *    bits  7:4 - V Offset (Y component)
 510     *    bits  3:0 - R Offset (Z component)
 511     */
 512    unsigned offset_bits = 0;
 513    for (unsigned i = 0; i < num_components; i++) {
 514       const unsigned shift = 4 * (2 - i);
 515       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 516    }
 517    return offset_bits;
 518 }
 519
 520 const char *
 521 brw_instruction_name(enum opcode op)
 522 {
 523    switch (op) {
 524    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 525       assert(opcode_descs[op].name);
 526       return opcode_descs[op].name;
 527    case FS_OPCODE_FB_WRITE:
 528       return "fb_write";
 529    case FS_OPCODE_FB_WRITE_LOGICAL:
 530       return "fb_write_logical";
 531    case FS_OPCODE_BLORP_FB_WRITE:
 532       return "blorp_fb_write";
 533    case FS_OPCODE_REP_FB_WRITE:
 534       return "rep_fb_write";
 535
 536    case SHADER_OPCODE_RCP:
 537       return "rcp";
 538    case SHADER_OPCODE_RSQ:
 539       return "rsq";
 540    case SHADER_OPCODE_SQRT:
 541       return "sqrt";
 542    case SHADER_OPCODE_EXP2:
 543       return "exp2";
 544    case SHADER_OPCODE_LOG2:
 545       return "log2";
 546    case SHADER_OPCODE_POW:
 547       return "pow";
 548    case SHADER_OPCODE_INT_QUOTIENT:
 549       return "int_quot";
 550    case SHADER_OPCODE_INT_REMAINDER:
 551       return "int_rem";
 552    case SHADER_OPCODE_SIN:
 553       return "sin";
 554    case SHADER_OPCODE_COS:
 555       return "cos";
 556
 557    case SHADER_OPCODE_TEX:
 558       return "tex";
 559    case SHADER_OPCODE_TEX_LOGICAL:
 560       return "tex_logical";
 561    case SHADER_OPCODE_TXD:
 562       return "txd";
 563    case SHADER_OPCODE_TXD_LOGICAL:
 564       return "txd_logical";
 565    case SHADER_OPCODE_TXF:
 566       return "txf";
 567    case SHADER_OPCODE_TXF_LOGICAL:
 568       return "txf_logical";
 569    case SHADER_OPCODE_TXL:
 570       return "txl";
 571    case SHADER_OPCODE_TXL_LOGICAL:
 572       return "txl_logical";
 573    case SHADER_OPCODE_TXS:
 574       return "txs";
 575    case SHADER_OPCODE_TXS_LOGICAL:
 576       return "txs_logical";
 577    case FS_OPCODE_TXB:
 578       return "txb";
 579    case FS_OPCODE_TXB_LOGICAL:
 580       return "txb_logical";
 581    case SHADER_OPCODE_TXF_CMS:
 582       return "txf_cms";
 583    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 584       return "txf_cms_logical";
 585    case SHADER_OPCODE_TXF_UMS:
 586       return "txf_ums";
 587    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 588       return "txf_ums_logical";
 589    case SHADER_OPCODE_TXF_MCS:
 590       return "txf_mcs";
 591    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 592       return "txf_mcs_logical";
 593    case SHADER_OPCODE_LOD:
 594       return "lod";
 595    case SHADER_OPCODE_LOD_LOGICAL:
 596       return "lod_logical";
 597    case SHADER_OPCODE_TG4:
 598       return "tg4";
 599    case SHADER_OPCODE_TG4_LOGICAL:
 600       return "tg4_logical";
 601    case SHADER_OPCODE_TG4_OFFSET:
 602       return "tg4_offset";
 603    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 604       return "tg4_offset_logical";
 605    case SHADER_OPCODE_SAMPLEINFO:
 606       return "sampleinfo";
 607
 608    case SHADER_OPCODE_SHADER_TIME_ADD:
 609       return "shader_time_add";
 610
 611    case SHADER_OPCODE_UNTYPED_ATOMIC:
 612       return "untyped_atomic";
 613    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 614       return "untyped_atomic_logical";
 615    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 616       return "untyped_surface_read";
 617    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 618       return "untyped_surface_read_logical";
 619    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 620       return "untyped_surface_write";
 621    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 622       return "untyped_surface_write_logical";
 623    case SHADER_OPCODE_TYPED_ATOMIC:
 624       return "typed_atomic";
 625    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 626       return "typed_atomic_logical";
 627    case SHADER_OPCODE_TYPED_SURFACE_READ:
 628       return "typed_surface_read";
 629    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 630       return "typed_surface_read_logical";
 631    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 632       return "typed_surface_write";
 633    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 634       return "typed_surface_write_logical";
 635    case SHADER_OPCODE_MEMORY_FENCE:
 636       return "memory_fence";
 637
 638    case SHADER_OPCODE_LOAD_PAYLOAD:
 639       return "load_payload";
 640
 641    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 642       return "gen4_scratch_read";
 643    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 644       return "gen4_scratch_write";
 645    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 646       return "gen7_scratch_read";
 647    case SHADER_OPCODE_URB_WRITE_SIMD8:
 648       return "gen8_urb_write_simd8";
 649
 650    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 651       return "find_live_channel";
 652    case SHADER_OPCODE_BROADCAST:
 653       return "broadcast";
 654
 655    case VEC4_OPCODE_MOV_BYTES:
 656       return "mov_bytes";
 657    case VEC4_OPCODE_PACK_BYTES:
 658       return "pack_bytes";
 659    case VEC4_OPCODE_UNPACK_UNIFORM:
 660       return "unpack_uniform";
 661
 662    case FS_OPCODE_DDX_COARSE:
 663       return "ddx_coarse";
 664    case FS_OPCODE_DDX_FINE:
 665       return "ddx_fine";
 666    case FS_OPCODE_DDY_COARSE:
 667       return "ddy_coarse";
 668    case FS_OPCODE_DDY_FINE:
 669       return "ddy_fine";
 670
 671    case FS_OPCODE_CINTERP:
 672       return "cinterp";
 673    case FS_OPCODE_LINTERP:
 674       return "linterp";
 675
 676    case FS_OPCODE_PIXEL_X:
 677       return "pixel_x";
 678    case FS_OPCODE_PIXEL_Y:
 679       return "pixel_y";
 680
 681    case FS_OPCODE_GET_BUFFER_SIZE:
 682       return "fs_get_buffer_size";
 683
 684    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 685       return "uniform_pull_const";
 686    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 687       return "uniform_pull_const_gen7";
 688    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 689       return "varying_pull_const";
 690    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 691       return "varying_pull_const_gen7";
 692
 693    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 694       return "mov_dispatch_to_flags";
 695    case FS_OPCODE_DISCARD_JUMP:
 696       return "discard_jump";
 697
 698    case FS_OPCODE_SET_SAMPLE_ID:
 699       return "set_sample_id";
 700    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 701       return "set_simd4x2_offset";
 702
 703    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 704       return "pack_half_2x16_split";
 705    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 706       return "unpack_half_2x16_split_x";
 707    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 708       return "unpack_half_2x16_split_y";
 709
 710    case FS_OPCODE_PLACEHOLDER_HALT:
 711       return "placeholder_halt";
 712
 713    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 714       return "interp_centroid";
 715    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 716       return "interp_sample";
 717    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 718       return "interp_shared_offset";
 719    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 720       return "interp_per_slot_offset";
 721
 722    case VS_OPCODE_URB_WRITE:
 723       return "vs_urb_write";
 724    case VS_OPCODE_PULL_CONSTANT_LOAD:
 725       return "pull_constant_load";
 726    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 727       return "pull_constant_load_gen7";
 728
 729    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 730       return "set_simd4x2_header_gen9";
 731
 732    case VS_OPCODE_GET_BUFFER_SIZE:
 733       return "vs_get_buffer_size";
 734
 735    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 736       return "unpack_flags_simd4x2";
 737
 738    case GS_OPCODE_URB_WRITE:
 739       return "gs_urb_write";
 740    case GS_OPCODE_URB_WRITE_ALLOCATE:
 741       return "gs_urb_write_allocate";
 742    case GS_OPCODE_THREAD_END:
 743       return "gs_thread_end";
 744    case GS_OPCODE_SET_WRITE_OFFSET:
 745       return "set_write_offset";
 746    case GS_OPCODE_SET_VERTEX_COUNT:
 747       return "set_vertex_count";
 748    case GS_OPCODE_SET_DWORD_2:
 749       return "set_dword_2";
 750    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 751       return "prepare_channel_masks";
 752    case GS_OPCODE_SET_CHANNEL_MASKS:
 753       return "set_channel_masks";
 754    case GS_OPCODE_GET_INSTANCE_ID:
 755       return "get_instance_id";
 756    case GS_OPCODE_FF_SYNC:
 757       return "ff_sync";
 758    case GS_OPCODE_SET_PRIMITIVE_ID:
 759       return "set_primitive_id";
 760    case GS_OPCODE_SVB_WRITE:
 761       return "gs_svb_write";
 762    case GS_OPCODE_SVB_SET_DST_INDEX:
 763       return "gs_svb_set_dst_index";
 764    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 765       return "gs_ff_sync_set_primitives";
 766    case CS_OPCODE_CS_TERMINATE:
 767       return "cs_terminate";
 768    case SHADER_OPCODE_BARRIER:
 769       return "barrier";
 770    case SHADER_OPCODE_MULH:
 771       return "mulh";
 772    }
 773
 774    unreachable("not reached");
 775 }
 776
 777 bool
 778 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 779 {
 780    union {
 781       unsigned ud;
 782       int d;
 783       float f;
 784    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 785
 786    switch (type) {
 787    case BRW_REGISTER_TYPE_UD:
 788    case BRW_REGISTER_TYPE_D:
 789    case BRW_REGISTER_TYPE_UQ:
 790    case BRW_REGISTER_TYPE_Q:
 791       /* Nothing to do. */
 792       return false;
 793    case BRW_REGISTER_TYPE_UW:
 794       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 795       break;
 796    case BRW_REGISTER_TYPE_W:
 797       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 798       break;
 799    case BRW_REGISTER_TYPE_F:
 800       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 801       break;
 802    case BRW_REGISTER_TYPE_UB:
 803    case BRW_REGISTER_TYPE_B:
 804       unreachable("no UB/B immediates");
 805    case BRW_REGISTER_TYPE_V:
 806    case BRW_REGISTER_TYPE_UV:
 807    case BRW_REGISTER_TYPE_VF:
 808       unreachable("unimplemented: saturate vector immediate");
 809    case BRW_REGISTER_TYPE_DF:
 810    case BRW_REGISTER_TYPE_HF:
 811       unreachable("unimplemented: saturate DF/HF immediate");
 812    }
 813
 814    if (imm.ud != sat_imm.ud) {
 815       reg->dw1.ud = sat_imm.ud;
 816       return true;
 817    }
 818    return false;
 819 }
 820
 821 bool
 822 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 823 {
 824    switch (type) {
 825    case BRW_REGISTER_TYPE_D:
 826    case BRW_REGISTER_TYPE_UD:
 827       reg->dw1.d = -reg->dw1.d;
 828       return true;
 829    case BRW_REGISTER_TYPE_W:
 830    case BRW_REGISTER_TYPE_UW:
 831       reg->dw1.d = -(int16_t)reg->dw1.ud;
 832       return true;
 833    case BRW_REGISTER_TYPE_F:
 834       reg->dw1.f = -reg->dw1.f;
 835       return true;
 836    case BRW_REGISTER_TYPE_VF:
 837       reg->dw1.ud ^= 0x80808080;
 838       return true;
 839    case BRW_REGISTER_TYPE_UB:
 840    case BRW_REGISTER_TYPE_B:
 841       unreachable("no UB/B immediates");
 842    case BRW_REGISTER_TYPE_UV:
 843    case BRW_REGISTER_TYPE_V:
 844       assert(!"unimplemented: negate UV/V immediate");
 845    case BRW_REGISTER_TYPE_UQ:
 846    case BRW_REGISTER_TYPE_Q:
 847       assert(!"unimplemented: negate UQ/Q immediate");
 848    case BRW_REGISTER_TYPE_DF:
 849    case BRW_REGISTER_TYPE_HF:
 850       assert(!"unimplemented: negate DF/HF immediate");
 851    }
 852
 853    return false;
 854 }
 855
 856 bool
 857 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 858 {
 859    switch (type) {
 860    case BRW_REGISTER_TYPE_D:
 861       reg->dw1.d = abs(reg->dw1.d);
 862       return true;
 863    case BRW_REGISTER_TYPE_W:
 864       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 865       return true;
 866    case BRW_REGISTER_TYPE_F:
 867       reg->dw1.f = fabsf(reg->dw1.f);
 868       return true;
 869    case BRW_REGISTER_TYPE_VF:
 870       reg->dw1.ud &= ~0x80808080;
 871       return true;
 872    case BRW_REGISTER_TYPE_UB:
 873    case BRW_REGISTER_TYPE_B:
 874       unreachable("no UB/B immediates");
 875    case BRW_REGISTER_TYPE_UQ:
 876    case BRW_REGISTER_TYPE_UD:
 877    case BRW_REGISTER_TYPE_UW:
 878    case BRW_REGISTER_TYPE_UV:
 879       /* Presumably the absolute value modifier on an unsigned source is a
 880        * nop, but it would be nice to confirm.
 881        */
 882       assert(!"unimplemented: abs unsigned immediate");
 883    case BRW_REGISTER_TYPE_V:
 884       assert(!"unimplemented: abs V immediate");
 885    case BRW_REGISTER_TYPE_Q:
 886       assert(!"unimplemented: abs Q immediate");
 887    case BRW_REGISTER_TYPE_DF:
 888    case BRW_REGISTER_TYPE_HF:
 889       assert(!"unimplemented: abs DF/HF immediate");
 890    }
 891
 892    return false;
 893 }
 894
 895 backend_shader::backend_shader(const struct brw_compiler *compiler,
 896                                void *log_data,
 897                                void *mem_ctx,
 898                                nir_shader *shader,
 899                                struct brw_stage_prog_data *stage_prog_data)
 900    : compiler(compiler),
 901      log_data(log_data),
 902      devinfo(compiler->devinfo),
 903      nir(shader),
 904      stage_prog_data(stage_prog_data),
 905      mem_ctx(mem_ctx),
 906      cfg(NULL),
 907      stage(shader->stage)
 908 {
 909    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 910    stage_name = _mesa_shader_stage_to_string(stage);
 911    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 912 }
 913
 914 bool
 915 backend_reg::is_zero() const
 916 {
 917    if (file != IMM)
 918       return false;
 919
 920    return fixed_hw_reg.dw1.d == 0;
 921 }
 922
 923 bool
 924 backend_reg::is_one() const
 925 {
 926    if (file != IMM)
 927       return false;
 928
 929    return type == BRW_REGISTER_TYPE_F
 930           ? fixed_hw_reg.dw1.f == 1.0
 931           : fixed_hw_reg.dw1.d == 1;
 932 }
 933
 934 bool
 935 backend_reg::is_negative_one() const
 936 {
 937    if (file != IMM)
 938       return false;
 939
 940    switch (type) {
 941    case BRW_REGISTER_TYPE_F:
 942       return fixed_hw_reg.dw1.f == -1.0;
 943    case BRW_REGISTER_TYPE_D:
 944       return fixed_hw_reg.dw1.d == -1;
 945    default:
 946       return false;
 947    }
 948 }
 949
 950 bool
 951 backend_reg::is_null() const
 952 {
 953    return file == HW_REG &&
 954           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 955           fixed_hw_reg.nr == BRW_ARF_NULL;
 956 }
 957
 958
 959 bool
 960 backend_reg::is_accumulator() const
 961 {
 962    return file == HW_REG &&
 963           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 964           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 965 }
 966
 967 bool
 968 backend_reg::in_range(const backend_reg &r, unsigned n) const
 969 {
 970    return (file == r.file &&
 971            reg == r.reg &&
 972            reg_offset >= r.reg_offset &&
 973            reg_offset < r.reg_offset + n);
 974 }
 975
 976 bool
 977 backend_instruction::is_commutative() const
 978 {
 979    switch (opcode) {
 980    case BRW_OPCODE_AND:
 981    case BRW_OPCODE_OR:
 982    case BRW_OPCODE_XOR:
 983    case BRW_OPCODE_ADD:
 984    case BRW_OPCODE_MUL:
 985    case SHADER_OPCODE_MULH:
 986       return true;
 987    case BRW_OPCODE_SEL:
 988       /* MIN and MAX are commutative. */
 989       if (conditional_mod == BRW_CONDITIONAL_GE ||
 990           conditional_mod == BRW_CONDITIONAL_L) {
 991          return true;
 992       }
 993       /* fallthrough */
 994    default:
 995       return false;
 996    }
 997 }
 998
 999 bool
1000 backend_instruction::is_3src() const
1001 {
1002    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
1003 }
1004
1005 bool
1006 backend_instruction::is_tex() const
1007 {
1008    return (opcode == SHADER_OPCODE_TEX ||
1009            opcode == FS_OPCODE_TXB ||
1010            opcode == SHADER_OPCODE_TXD ||
1011            opcode == SHADER_OPCODE_TXF ||
1012            opcode == SHADER_OPCODE_TXF_CMS ||
1013            opcode == SHADER_OPCODE_TXF_UMS ||
1014            opcode == SHADER_OPCODE_TXF_MCS ||
1015            opcode == SHADER_OPCODE_TXL ||
1016            opcode == SHADER_OPCODE_TXS ||
1017            opcode == SHADER_OPCODE_LOD ||
1018            opcode == SHADER_OPCODE_TG4 ||
1019            opcode == SHADER_OPCODE_TG4_OFFSET);
1020 }
1021
1022 bool
1023 backend_instruction::is_math() const
1024 {
1025    return (opcode == SHADER_OPCODE_RCP ||
1026            opcode == SHADER_OPCODE_RSQ ||
1027            opcode == SHADER_OPCODE_SQRT ||
1028            opcode == SHADER_OPCODE_EXP2 ||
1029            opcode == SHADER_OPCODE_LOG2 ||
1030            opcode == SHADER_OPCODE_SIN ||
1031            opcode == SHADER_OPCODE_COS ||
1032            opcode == SHADER_OPCODE_INT_QUOTIENT ||
1033            opcode == SHADER_OPCODE_INT_REMAINDER ||
1034            opcode == SHADER_OPCODE_POW);
1035 }
1036
1037 bool
1038 backend_instruction::is_control_flow() const
1039 {
1040    switch (opcode) {
1041    case BRW_OPCODE_DO:
1042    case BRW_OPCODE_WHILE:
1043    case BRW_OPCODE_IF:
1044    case BRW_OPCODE_ELSE:
1045    case BRW_OPCODE_ENDIF:
1046    case BRW_OPCODE_BREAK:
1047    case BRW_OPCODE_CONTINUE:
1048       return true;
1049    default:
1050       return false;
1051    }
1052 }
1053
1054 bool
1055 backend_instruction::can_do_source_mods() const
1056 {
1057    switch (opcode) {
1058    case BRW_OPCODE_ADDC:
1059    case BRW_OPCODE_BFE:
1060    case BRW_OPCODE_BFI1:
1061    case BRW_OPCODE_BFI2:
1062    case BRW_OPCODE_BFREV:
1063    case BRW_OPCODE_CBIT:
1064    case BRW_OPCODE_FBH:
1065    case BRW_OPCODE_FBL:
1066    case BRW_OPCODE_SUBB:
1067       return false;
1068    default:
1069       return true;
1070    }
1071 }
1072
1073 bool
1074 backend_instruction::can_do_saturate() const
1075 {
1076    switch (opcode) {
1077    case BRW_OPCODE_ADD:
1078    case BRW_OPCODE_ASR:
1079    case BRW_OPCODE_AVG:
1080    case BRW_OPCODE_DP2:
1081    case BRW_OPCODE_DP3:
1082    case BRW_OPCODE_DP4:
1083    case BRW_OPCODE_DPH:
1084    case BRW_OPCODE_F16TO32:
1085    case BRW_OPCODE_F32TO16:
1086    case BRW_OPCODE_LINE:
1087    case BRW_OPCODE_LRP:
1088    case BRW_OPCODE_MAC:
1089    case BRW_OPCODE_MAD:
1090    case BRW_OPCODE_MATH:
1091    case BRW_OPCODE_MOV:
1092    case BRW_OPCODE_MUL:
1093    case SHADER_OPCODE_MULH:
1094    case BRW_OPCODE_PLN:
1095    case BRW_OPCODE_RNDD:
1096    case BRW_OPCODE_RNDE:
1097    case BRW_OPCODE_RNDU:
1098    case BRW_OPCODE_RNDZ:
1099    case BRW_OPCODE_SEL:
1100    case BRW_OPCODE_SHL:
1101    case BRW_OPCODE_SHR:
1102    case FS_OPCODE_LINTERP:
1103    case SHADER_OPCODE_COS:
1104    case SHADER_OPCODE_EXP2:
1105    case SHADER_OPCODE_LOG2:
1106    case SHADER_OPCODE_POW:
1107    case SHADER_OPCODE_RCP:
1108    case SHADER_OPCODE_RSQ:
1109    case SHADER_OPCODE_SIN:
1110    case SHADER_OPCODE_SQRT:
1111       return true;
1112    default:
1113       return false;
1114    }
1115 }
1116
1117 bool
1118 backend_instruction::can_do_cmod() const
1119 {
1120    switch (opcode) {
1121    case BRW_OPCODE_ADD:
1122    case BRW_OPCODE_ADDC:
1123    case BRW_OPCODE_AND:
1124    case BRW_OPCODE_ASR:
1125    case BRW_OPCODE_AVG:
1126    case BRW_OPCODE_CMP:
1127    case BRW_OPCODE_CMPN:
1128    case BRW_OPCODE_DP2:
1129    case BRW_OPCODE_DP3:
1130    case BRW_OPCODE_DP4:
1131    case BRW_OPCODE_DPH:
1132    case BRW_OPCODE_F16TO32:
1133    case BRW_OPCODE_F32TO16:
1134    case BRW_OPCODE_FRC:
1135    case BRW_OPCODE_LINE:
1136    case BRW_OPCODE_LRP:
1137    case BRW_OPCODE_LZD:
1138    case BRW_OPCODE_MAC:
1139    case BRW_OPCODE_MACH:
1140    case BRW_OPCODE_MAD:
1141    case BRW_OPCODE_MOV:
1142    case BRW_OPCODE_MUL:
1143    case BRW_OPCODE_NOT:
1144    case BRW_OPCODE_OR:
1145    case BRW_OPCODE_PLN:
1146    case BRW_OPCODE_RNDD:
1147    case BRW_OPCODE_RNDE:
1148    case BRW_OPCODE_RNDU:
1149    case BRW_OPCODE_RNDZ:
1150    case BRW_OPCODE_SAD2:
1151    case BRW_OPCODE_SADA2:
1152    case BRW_OPCODE_SHL:
1153    case BRW_OPCODE_SHR:
1154    case BRW_OPCODE_SUBB:
1155    case BRW_OPCODE_XOR:
1156    case FS_OPCODE_CINTERP:
1157    case FS_OPCODE_LINTERP:
1158       return true;
1159    default:
1160       return false;
1161    }
1162 }
1163
1164 bool
1165 backend_instruction::reads_accumulator_implicitly() const
1166 {
1167    switch (opcode) {
1168    case BRW_OPCODE_MAC:
1169    case BRW_OPCODE_MACH:
1170    case BRW_OPCODE_SADA2:
1171       return true;
1172    default:
1173       return false;
1174    }
1175 }
1176
1177 bool
1178 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1179 {
1180    return writes_accumulator ||
1181           (devinfo->gen < 6 &&
1182            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1183             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1184              opcode != FS_OPCODE_CINTERP)));
1185 }
1186
1187 bool
1188 backend_instruction::has_side_effects() const
1189 {
1190    switch (opcode) {
1191    case SHADER_OPCODE_UNTYPED_ATOMIC:
1192    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1193    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1194    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1195    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1196    case SHADER_OPCODE_TYPED_ATOMIC:
1197    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1198    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1199    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1200    case SHADER_OPCODE_MEMORY_FENCE:
1201    case SHADER_OPCODE_URB_WRITE_SIMD8:
1202    case FS_OPCODE_FB_WRITE:
1203    case SHADER_OPCODE_BARRIER:
1204       return true;
1205    default:
1206       return false;
1207    }
1208 }
1209
1210 #ifndef NDEBUG
1211 static bool
1212 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1213 {
1214    bool found = false;
1215    foreach_inst_in_block (backend_instruction, i, block) {
1216       if (inst == i) {
1217          found = true;
1218       }
1219    }
1220    return found;
1221 }
1222 #endif
1223
1224 static void
1225 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1226 {
1227    for (bblock_t *block_iter = start_block->next();
1228         !block_iter->link.is_tail_sentinel();
1229         block_iter = block_iter->next()) {
1230       block_iter->start_ip += ip_adjustment;
1231       block_iter->end_ip += ip_adjustment;
1232    }
1233 }
1234
1235 void
1236 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1237 {
1238    if (!this->is_head_sentinel())
1239       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1240
1241    block->end_ip++;
1242
1243    adjust_later_block_ips(block, 1);
1244
1245    exec_node::insert_after(inst);
1246 }
1247
1248 void
1249 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1250 {
1251    if (!this->is_tail_sentinel())
1252       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1253
1254    block->end_ip++;
1255
1256    adjust_later_block_ips(block, 1);
1257
1258    exec_node::insert_before(inst);
1259 }
1260
1261 void
1262 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1263 {
1264    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1265
1266    unsigned num_inst = list->length();
1267
1268    block->end_ip += num_inst;
1269
1270    adjust_later_block_ips(block, num_inst);
1271
1272    exec_node::insert_before(list);
1273 }
1274
1275 void
1276 backend_instruction::remove(bblock_t *block)
1277 {
1278    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1279
1280    adjust_later_block_ips(block, -1);
1281
1282    if (block->start_ip == block->end_ip) {
1283       block->cfg->remove_block(block);
1284    } else {
1285       block->end_ip--;
1286    }
1287
1288    exec_node::remove();
1289 }
1290
1291 void
1292 backend_shader::dump_instructions()
1293 {
1294    dump_instructions(NULL);
1295 }
1296
1297 void
1298 backend_shader::dump_instructions(const char *name)
1299 {
1300    FILE *file = stderr;
1301    if (name && geteuid() != 0) {
1302       file = fopen(name, "w");
1303       if (!file)
1304          file = stderr;
1305    }
1306
1307    if (cfg) {
1308       int ip = 0;
1309       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1310          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1311             fprintf(file, "%4d: ", ip++);
1312          dump_instruction(inst, file);
1313       }
1314    } else {
1315       int ip = 0;
1316       foreach_in_list(backend_instruction, inst, &instructions) {
1317          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1318             fprintf(file, "%4d: ", ip++);
1319          dump_instruction(inst, file);
1320       }
1321    }
1322
1323    if (file != stderr) {
1324       fclose(file);
1325    }
1326 }
1327
1328 void
1329 backend_shader::calculate_cfg()
1330 {
1331    if (this->cfg)
1332       return;
1333    cfg = new(mem_ctx) cfg_t(&this->instructions);
1334 }
1335
1336 void
1337 backend_shader::invalidate_cfg()
1338 {
1339    ralloc_free(this->cfg);
1340    this->cfg = NULL;
1341 }
1342
1343 /**
1344  * Sets up the starting offsets for the groups of binding table entries
1345  * commong to all pipeline stages.
1346  *
1347  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1348  * unused but also make sure that addition of small offsets to them will
1349  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1350  */
1351 void
1352 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1353                                         const struct brw_device_info *devinfo,
1354                                         const struct gl_shader_program *shader_prog,
1355                                         const struct gl_program *prog,
1356                                         struct brw_stage_prog_data *stage_prog_data,
1357                                         uint32_t next_binding_table_offset)
1358 {
1359    const struct gl_shader *shader = NULL;
1360    int num_textures = _mesa_fls(prog->SamplersUsed);
1361
1362    if (shader_prog)
1363       shader = shader_prog->_LinkedShaders[stage];
1364
1365    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1366    next_binding_table_offset += num_textures;
1367
1368    if (shader) {
1369       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1370       next_binding_table_offset += shader->NumUniformBlocks;
1371    } else {
1372       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1373    }
1374
1375    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1376       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1377       next_binding_table_offset++;
1378    } else {
1379       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1380    }
1381
1382    if (prog->UsesGather) {
1383       if (devinfo->gen >= 8) {
1384          stage_prog_data->binding_table.gather_texture_start =
1385             stage_prog_data->binding_table.texture_start;
1386       } else {
1387          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1388          next_binding_table_offset += num_textures;
1389       }
1390    } else {
1391       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1392    }
1393
1394    if (shader_prog && shader_prog->NumAtomicBuffers) {
1395       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1396       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1397    } else {
1398       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1399    }
1400
1401    if (shader && shader->NumImages) {
1402       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1403       next_binding_table_offset += shader->NumImages;
1404    } else {
1405       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1406    }
1407
1408    /* This may or may not be used depending on how the compile goes. */
1409    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1410    next_binding_table_offset++;
1411
1412    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1413
1414    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1415 }
1416
1417 static void
1418 setup_vec4_uniform_value(const gl_constant_value **params,
1419                          const gl_constant_value *values,
1420                          unsigned n)
1421 {
1422    static const gl_constant_value zero = { 0 };
1423
1424    for (unsigned i = 0; i < n; ++i)
1425       params[i] = &values[i];
1426
1427    for (unsigned i = n; i < 4; ++i)
1428       params[i] = &zero;
1429 }
1430
1431 void
1432 brw_setup_image_uniform_values(gl_shader_stage stage,
1433                                struct brw_stage_prog_data *stage_prog_data,
1434                                unsigned param_start_index,
1435                                const gl_uniform_storage *storage)
1436 {
1437    const gl_constant_value **param =
1438       &stage_prog_data->param[param_start_index];
1439
1440    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1441       const unsigned image_idx = storage->opaque[stage].index + i;
1442       const brw_image_param *image_param =
1443          &stage_prog_data->image_param[image_idx];
1444
1445       /* Upload the brw_image_param structure.  The order is expected to match
1446        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1447        */
1448       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1449          (const gl_constant_value *)&image_param->surface_idx, 1);
1450       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1451          (const gl_constant_value *)image_param->offset, 2);
1452       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1453          (const gl_constant_value *)image_param->size, 3);
1454       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1455          (const gl_constant_value *)image_param->stride, 4);
1456       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1457          (const gl_constant_value *)image_param->tiling, 3);
1458       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1459          (const gl_constant_value *)image_param->swizzling, 2);
1460       param += BRW_IMAGE_PARAM_SIZE;
1461
1462       brw_mark_surface_used(
1463          stage_prog_data,
1464          stage_prog_data->binding_table.image_start + image_idx);
1465    }
1466 }