src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 struct brw_compiler *
  36 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  37 {
  38    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  39
  40    compiler->devinfo = devinfo;
  41
  42    brw_fs_alloc_reg_sets(compiler);
  43    brw_vec4_alloc_reg_set(compiler);
  44
  45    return compiler;
  46 }
  47
  48 struct gl_shader *
  49 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  50 {
  51    struct brw_shader *shader;
  52
  53    shader = rzalloc(NULL, struct brw_shader);
  54    if (shader) {
  55       shader->base.Type = type;
  56       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  57       shader->base.Name = name;
  58       _mesa_init_shader(ctx, &shader->base);
  59    }
  60
  61    return &shader->base;
  62 }
  63
  64 /**
  65  * Performs a compile of the shader stages even when we don't know
  66  * what non-orthogonal state will be set, in the hope that it reflects
  67  * the eventual NOS used, and thus allows us to produce link failures.
  68  */
  69 static bool
  70 brw_shader_precompile(struct gl_context *ctx,
  71                       struct gl_shader_program *sh_prog)
  72 {
  73    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  74    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  75    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  76    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
  77
  78    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  79       return false;
  80
  81    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  82       return false;
  83
  84    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  85       return false;
  86
  87    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
  88       return false;
  89
  90    return true;
  91 }
  92
  93 static inline bool
  94 is_scalar_shader_stage(struct brw_context *brw, int stage)
  95 {
  96    switch (stage) {
  97    case MESA_SHADER_FRAGMENT:
  98       return true;
  99    case MESA_SHADER_VERTEX:
 100       return brw->scalar_vs;
 101    default:
 102       return false;
 103    }
 104 }
 105
 106 static void
 107 brw_lower_packing_builtins(struct brw_context *brw,
 108                            gl_shader_stage shader_type,
 109                            exec_list *ir)
 110 {
 111    int ops = LOWER_PACK_SNORM_2x16
 112            | LOWER_UNPACK_SNORM_2x16
 113            | LOWER_PACK_UNORM_2x16
 114            | LOWER_UNPACK_UNORM_2x16;
 115
 116    if (is_scalar_shader_stage(brw, shader_type)) {
 117       ops |= LOWER_UNPACK_UNORM_4x8
 118            | LOWER_UNPACK_SNORM_4x8
 119            | LOWER_PACK_UNORM_4x8
 120            | LOWER_PACK_SNORM_4x8;
 121    }
 122
 123    if (brw->gen >= 7) {
 124       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 125        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 126        * lowering is needed. For SOA code, the Half2x16 ops must be
 127        * scalarized.
 128        */
 129       if (is_scalar_shader_stage(brw, shader_type)) {
 130          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 131              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 132       }
 133    } else {
 134       ops |= LOWER_PACK_HALF_2x16
 135           |  LOWER_UNPACK_HALF_2x16;
 136    }
 137
 138    lower_packing_builtins(ir, ops);
 139 }
 140
 141 static void
 142 process_glsl_ir(struct brw_context *brw,
 143                 struct gl_shader_program *shader_prog,
 144                 struct gl_shader *shader)
 145 {
 146    struct gl_context *ctx = &brw->ctx;
 147    const struct gl_shader_compiler_options *options =
 148       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 149
 150    /* Temporary memory context for any new IR. */
 151    void *mem_ctx = ralloc_context(NULL);
 152
 153    ralloc_adopt(mem_ctx, shader->ir);
 154
 155    /* lower_packing_builtins() inserts arithmetic instructions, so it
 156     * must precede lower_instructions().
 157     */
 158    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 159    do_mat_op_to_vec(shader->ir);
 160    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 161    lower_instructions(shader->ir,
 162                       MOD_TO_FLOOR |
 163                       DIV_TO_MUL_RCP |
 164                       SUB_TO_ADD_NEG |
 165                       EXP_TO_EXP2 |
 166                       LOG_TO_LOG2 |
 167                       bitfield_insert |
 168                       LDEXP_TO_ARITH);
 169
 170    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 171     * if-statements need to be flattened.
 172     */
 173    if (brw->gen < 6)
 174       lower_if_to_cond_assign(shader->ir, 16);
 175
 176    do_lower_texture_projection(shader->ir);
 177    brw_lower_texture_gradients(brw, shader->ir);
 178    do_vec_index_to_cond_assign(shader->ir);
 179    lower_vector_insert(shader->ir, true);
 180    if (options->NirOptions == NULL)
 181       brw_do_cubemap_normalize(shader->ir);
 182    lower_offset_arrays(shader->ir);
 183    brw_do_lower_unnormalized_offset(shader->ir);
 184    lower_noise(shader->ir);
 185    lower_quadop_vector(shader->ir, false);
 186
 187    bool lowered_variable_indexing =
 188       lower_variable_index_to_cond_assign(shader->ir,
 189                                           options->EmitNoIndirectInput,
 190                                           options->EmitNoIndirectOutput,
 191                                           options->EmitNoIndirectTemp,
 192                                           options->EmitNoIndirectUniform);
 193
 194    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 195       perf_debug("Unsupported form of variable indexing in FS; falling "
 196                  "back to very inefficient code generation\n");
 197    }
 198
 199    lower_ubo_reference(shader, shader->ir);
 200
 201    bool progress;
 202    do {
 203       progress = false;
 204
 205       if (is_scalar_shader_stage(brw, shader->Stage)) {
 206          brw_do_channel_expressions(shader->ir);
 207          brw_do_vector_splitting(shader->ir);
 208       }
 209
 210       progress = do_lower_jumps(shader->ir, true, true,
 211                                 true, /* main return */
 212                                 false, /* continue */
 213                                 false /* loops */
 214                                 ) || progress;
 215
 216       progress = do_common_optimization(shader->ir, true, true,
 217                                         options, ctx->Const.NativeIntegers) || progress;
 218    } while (progress);
 219
 220    if (options->NirOptions != NULL)
 221       lower_output_reads(shader->ir);
 222
 223    validate_ir_tree(shader->ir);
 224
 225    /* Now that we've finished altering the linked IR, reparent any live IR back
 226     * to the permanent memory context, and free the temporary one (discarding any
 227     * junk we optimized away).
 228     */
 229    reparent_ir(shader->ir, shader->ir);
 230    ralloc_free(mem_ctx);
 231
 232    if (ctx->_Shader->Flags & GLSL_DUMP) {
 233       fprintf(stderr, "\n");
 234       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 235               _mesa_shader_stage_to_string(shader->Stage),
 236               shader_prog->Name);
 237       _mesa_print_ir(stderr, shader->ir, NULL);
 238       fprintf(stderr, "\n");
 239    }
 240 }
 241
 242 GLboolean
 243 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 244 {
 245    struct brw_context *brw = brw_context(ctx);
 246    unsigned int stage;
 247
 248    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 249       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 250       const struct gl_shader_compiler_options *options =
 251          &ctx->Const.ShaderCompilerOptions[stage];
 252
 253       if (!shader)
 254          continue;
 255
 256       struct gl_program *prog =
 257          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 258                                 shader->Name);
 259       if (!prog)
 260         return false;
 261       prog->Parameters = _mesa_new_parameter_list();
 262
 263       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 264
 265       process_glsl_ir(brw, shProg, shader);
 266
 267       /* Make a pass over the IR to add state references for any built-in
 268        * uniforms that are used.  This has to be done now (during linking).
 269        * Code generation doesn't happen until the first time this shader is
 270        * used for rendering.  Waiting until then to generate the parameters is
 271        * too late.  At that point, the values for the built-in uniforms won't
 272        * get sent to the shader.
 273        */
 274       foreach_in_list(ir_instruction, node, shader->ir) {
 275          ir_variable *var = node->as_variable();
 276
 277          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 278              || (strncmp(var->name, "gl_", 3) != 0))
 279             continue;
 280
 281          const ir_state_slot *const slots = var->get_state_slots();
 282          assert(slots != NULL);
 283
 284          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 285             _mesa_add_state_reference(prog->Parameters,
 286                                       (gl_state_index *) slots[i].tokens);
 287          }
 288       }
 289
 290       do_set_program_inouts(shader->ir, prog, shader->Stage);
 291
 292       prog->SamplersUsed = shader->active_samplers;
 293       prog->ShadowSamplers = shader->shadow_samplers;
 294       _mesa_update_shader_textures_used(shProg, prog);
 295
 296       _mesa_reference_program(ctx, &shader->Program, prog);
 297
 298       brw_add_texrect_params(prog);
 299
 300       if (options->NirOptions)
 301          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 302
 303       _mesa_reference_program(ctx, &prog, NULL);
 304    }
 305
 306    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 307       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 308          const struct gl_shader *sh = shProg->Shaders[i];
 309          if (!sh)
 310             continue;
 311
 312          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 313                  _mesa_shader_stage_to_string(sh->Stage),
 314                  i, shProg->Name);
 315          fprintf(stderr, "%s", sh->Source);
 316          fprintf(stderr, "\n");
 317       }
 318    }
 319
 320    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 321       return false;
 322
 323    return true;
 324 }
 325
 326
 327 enum brw_reg_type
 328 brw_type_for_base_type(const struct glsl_type *type)
 329 {
 330    switch (type->base_type) {
 331    case GLSL_TYPE_FLOAT:
 332       return BRW_REGISTER_TYPE_F;
 333    case GLSL_TYPE_INT:
 334    case GLSL_TYPE_BOOL:
 335       return BRW_REGISTER_TYPE_D;
 336    case GLSL_TYPE_UINT:
 337       return BRW_REGISTER_TYPE_UD;
 338    case GLSL_TYPE_ARRAY:
 339       return brw_type_for_base_type(type->fields.array);
 340    case GLSL_TYPE_STRUCT:
 341    case GLSL_TYPE_SAMPLER:
 342    case GLSL_TYPE_ATOMIC_UINT:
 343       /* These should be overridden with the type of the member when
 344        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 345        * way to trip up if we don't.
 346        */
 347       return BRW_REGISTER_TYPE_UD;
 348    case GLSL_TYPE_IMAGE:
 349       return BRW_REGISTER_TYPE_UD;
 350    case GLSL_TYPE_VOID:
 351    case GLSL_TYPE_ERROR:
 352    case GLSL_TYPE_INTERFACE:
 353    case GLSL_TYPE_DOUBLE:
 354       unreachable("not reached");
 355    }
 356
 357    return BRW_REGISTER_TYPE_F;
 358 }
 359
 360 enum brw_conditional_mod
 361 brw_conditional_for_comparison(unsigned int op)
 362 {
 363    switch (op) {
 364    case ir_binop_less:
 365       return BRW_CONDITIONAL_L;
 366    case ir_binop_greater:
 367       return BRW_CONDITIONAL_G;
 368    case ir_binop_lequal:
 369       return BRW_CONDITIONAL_LE;
 370    case ir_binop_gequal:
 371       return BRW_CONDITIONAL_GE;
 372    case ir_binop_equal:
 373    case ir_binop_all_equal: /* same as equal for scalars */
 374       return BRW_CONDITIONAL_Z;
 375    case ir_binop_nequal:
 376    case ir_binop_any_nequal: /* same as nequal for scalars */
 377       return BRW_CONDITIONAL_NZ;
 378    default:
 379       unreachable("not reached: bad operation for comparison");
 380    }
 381 }
 382
 383 uint32_t
 384 brw_math_function(enum opcode op)
 385 {
 386    switch (op) {
 387    case SHADER_OPCODE_RCP:
 388       return BRW_MATH_FUNCTION_INV;
 389    case SHADER_OPCODE_RSQ:
 390       return BRW_MATH_FUNCTION_RSQ;
 391    case SHADER_OPCODE_SQRT:
 392       return BRW_MATH_FUNCTION_SQRT;
 393    case SHADER_OPCODE_EXP2:
 394       return BRW_MATH_FUNCTION_EXP;
 395    case SHADER_OPCODE_LOG2:
 396       return BRW_MATH_FUNCTION_LOG;
 397    case SHADER_OPCODE_POW:
 398       return BRW_MATH_FUNCTION_POW;
 399    case SHADER_OPCODE_SIN:
 400       return BRW_MATH_FUNCTION_SIN;
 401    case SHADER_OPCODE_COS:
 402       return BRW_MATH_FUNCTION_COS;
 403    case SHADER_OPCODE_INT_QUOTIENT:
 404       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 405    case SHADER_OPCODE_INT_REMAINDER:
 406       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 407    default:
 408       unreachable("not reached: unknown math function");
 409    }
 410 }
 411
 412 uint32_t
 413 brw_texture_offset(int *offsets, unsigned num_components)
 414 {
 415    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 416
 417    /* Combine all three offsets into a single unsigned dword:
 418     *
 419     *    bits 11:8 - U Offset (X component)
 420     *    bits  7:4 - V Offset (Y component)
 421     *    bits  3:0 - R Offset (Z component)
 422     */
 423    unsigned offset_bits = 0;
 424    for (unsigned i = 0; i < num_components; i++) {
 425       const unsigned shift = 4 * (2 - i);
 426       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 427    }
 428    return offset_bits;
 429 }
 430
 431 const char *
 432 brw_instruction_name(enum opcode op)
 433 {
 434    switch (op) {
 435    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 436       assert(opcode_descs[op].name);
 437       return opcode_descs[op].name;
 438    case FS_OPCODE_FB_WRITE:
 439       return "fb_write";
 440    case FS_OPCODE_BLORP_FB_WRITE:
 441       return "blorp_fb_write";
 442    case FS_OPCODE_REP_FB_WRITE:
 443       return "rep_fb_write";
 444
 445    case SHADER_OPCODE_RCP:
 446       return "rcp";
 447    case SHADER_OPCODE_RSQ:
 448       return "rsq";
 449    case SHADER_OPCODE_SQRT:
 450       return "sqrt";
 451    case SHADER_OPCODE_EXP2:
 452       return "exp2";
 453    case SHADER_OPCODE_LOG2:
 454       return "log2";
 455    case SHADER_OPCODE_POW:
 456       return "pow";
 457    case SHADER_OPCODE_INT_QUOTIENT:
 458       return "int_quot";
 459    case SHADER_OPCODE_INT_REMAINDER:
 460       return "int_rem";
 461    case SHADER_OPCODE_SIN:
 462       return "sin";
 463    case SHADER_OPCODE_COS:
 464       return "cos";
 465
 466    case SHADER_OPCODE_TEX:
 467       return "tex";
 468    case SHADER_OPCODE_TXD:
 469       return "txd";
 470    case SHADER_OPCODE_TXF:
 471       return "txf";
 472    case SHADER_OPCODE_TXL:
 473       return "txl";
 474    case SHADER_OPCODE_TXS:
 475       return "txs";
 476    case FS_OPCODE_TXB:
 477       return "txb";
 478    case SHADER_OPCODE_TXF_CMS:
 479       return "txf_cms";
 480    case SHADER_OPCODE_TXF_UMS:
 481       return "txf_ums";
 482    case SHADER_OPCODE_TXF_MCS:
 483       return "txf_mcs";
 484    case SHADER_OPCODE_LOD:
 485       return "lod";
 486    case SHADER_OPCODE_TG4:
 487       return "tg4";
 488    case SHADER_OPCODE_TG4_OFFSET:
 489       return "tg4_offset";
 490    case SHADER_OPCODE_SHADER_TIME_ADD:
 491       return "shader_time_add";
 492
 493    case SHADER_OPCODE_UNTYPED_ATOMIC:
 494       return "untyped_atomic";
 495    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 496       return "untyped_surface_read";
 497    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 498       return "untyped_surface_write";
 499    case SHADER_OPCODE_TYPED_ATOMIC:
 500       return "typed_atomic";
 501    case SHADER_OPCODE_TYPED_SURFACE_READ:
 502       return "typed_surface_read";
 503    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 504       return "typed_surface_write";
 505
 506    case SHADER_OPCODE_LOAD_PAYLOAD:
 507       return "load_payload";
 508
 509    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 510       return "gen4_scratch_read";
 511    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 512       return "gen4_scratch_write";
 513    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 514       return "gen7_scratch_read";
 515    case SHADER_OPCODE_URB_WRITE_SIMD8:
 516       return "gen8_urb_write_simd8";
 517
 518    case VEC4_OPCODE_MOV_BYTES:
 519       return "mov_bytes";
 520    case VEC4_OPCODE_PACK_BYTES:
 521       return "pack_bytes";
 522    case VEC4_OPCODE_UNPACK_UNIFORM:
 523       return "unpack_uniform";
 524
 525    case FS_OPCODE_DDX_COARSE:
 526       return "ddx_coarse";
 527    case FS_OPCODE_DDX_FINE:
 528       return "ddx_fine";
 529    case FS_OPCODE_DDY_COARSE:
 530       return "ddy_coarse";
 531    case FS_OPCODE_DDY_FINE:
 532       return "ddy_fine";
 533
 534    case FS_OPCODE_CINTERP:
 535       return "cinterp";
 536    case FS_OPCODE_LINTERP:
 537       return "linterp";
 538
 539    case FS_OPCODE_PIXEL_X:
 540       return "pixel_x";
 541    case FS_OPCODE_PIXEL_Y:
 542       return "pixel_y";
 543
 544    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 545       return "uniform_pull_const";
 546    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 547       return "uniform_pull_const_gen7";
 548    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 549       return "varying_pull_const";
 550    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 551       return "varying_pull_const_gen7";
 552
 553    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 554       return "mov_dispatch_to_flags";
 555    case FS_OPCODE_DISCARD_JUMP:
 556       return "discard_jump";
 557
 558    case FS_OPCODE_SET_OMASK:
 559       return "set_omask";
 560    case FS_OPCODE_SET_SAMPLE_ID:
 561       return "set_sample_id";
 562    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 563       return "set_simd4x2_offset";
 564
 565    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 566       return "pack_half_2x16_split";
 567    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 568       return "unpack_half_2x16_split_x";
 569    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 570       return "unpack_half_2x16_split_y";
 571
 572    case FS_OPCODE_PLACEHOLDER_HALT:
 573       return "placeholder_halt";
 574
 575    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 576       return "interp_centroid";
 577    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 578       return "interp_sample";
 579    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 580       return "interp_shared_offset";
 581    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 582       return "interp_per_slot_offset";
 583
 584    case VS_OPCODE_URB_WRITE:
 585       return "vs_urb_write";
 586    case VS_OPCODE_PULL_CONSTANT_LOAD:
 587       return "pull_constant_load";
 588    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 589       return "pull_constant_load_gen7";
 590
 591    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 592       return "set_simd4x2_header_gen9";
 593
 594    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 595       return "unpack_flags_simd4x2";
 596
 597    case GS_OPCODE_URB_WRITE:
 598       return "gs_urb_write";
 599    case GS_OPCODE_URB_WRITE_ALLOCATE:
 600       return "gs_urb_write_allocate";
 601    case GS_OPCODE_THREAD_END:
 602       return "gs_thread_end";
 603    case GS_OPCODE_SET_WRITE_OFFSET:
 604       return "set_write_offset";
 605    case GS_OPCODE_SET_VERTEX_COUNT:
 606       return "set_vertex_count";
 607    case GS_OPCODE_SET_DWORD_2:
 608       return "set_dword_2";
 609    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 610       return "prepare_channel_masks";
 611    case GS_OPCODE_SET_CHANNEL_MASKS:
 612       return "set_channel_masks";
 613    case GS_OPCODE_GET_INSTANCE_ID:
 614       return "get_instance_id";
 615    case GS_OPCODE_FF_SYNC:
 616       return "ff_sync";
 617    case GS_OPCODE_SET_PRIMITIVE_ID:
 618       return "set_primitive_id";
 619    case GS_OPCODE_SVB_WRITE:
 620       return "gs_svb_write";
 621    case GS_OPCODE_SVB_SET_DST_INDEX:
 622       return "gs_svb_set_dst_index";
 623    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 624       return "gs_ff_sync_set_primitives";
 625    case CS_OPCODE_CS_TERMINATE:
 626       return "cs_terminate";
 627    }
 628
 629    unreachable("not reached");
 630 }
 631
 632 bool
 633 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 634 {
 635    union {
 636       unsigned ud;
 637       int d;
 638       float f;
 639    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 640
 641    switch (type) {
 642    case BRW_REGISTER_TYPE_UD:
 643    case BRW_REGISTER_TYPE_D:
 644    case BRW_REGISTER_TYPE_UQ:
 645    case BRW_REGISTER_TYPE_Q:
 646       /* Nothing to do. */
 647       return false;
 648    case BRW_REGISTER_TYPE_UW:
 649       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 650       break;
 651    case BRW_REGISTER_TYPE_W:
 652       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 653       break;
 654    case BRW_REGISTER_TYPE_F:
 655       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 656       break;
 657    case BRW_REGISTER_TYPE_UB:
 658    case BRW_REGISTER_TYPE_B:
 659       unreachable("no UB/B immediates");
 660    case BRW_REGISTER_TYPE_V:
 661    case BRW_REGISTER_TYPE_UV:
 662    case BRW_REGISTER_TYPE_VF:
 663       unreachable("unimplemented: saturate vector immediate");
 664    case BRW_REGISTER_TYPE_DF:
 665    case BRW_REGISTER_TYPE_HF:
 666       unreachable("unimplemented: saturate DF/HF immediate");
 667    }
 668
 669    if (imm.ud != sat_imm.ud) {
 670       reg->dw1.ud = sat_imm.ud;
 671       return true;
 672    }
 673    return false;
 674 }
 675
 676 bool
 677 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 678 {
 679    switch (type) {
 680    case BRW_REGISTER_TYPE_D:
 681    case BRW_REGISTER_TYPE_UD:
 682       reg->dw1.d = -reg->dw1.d;
 683       return true;
 684    case BRW_REGISTER_TYPE_W:
 685    case BRW_REGISTER_TYPE_UW:
 686       reg->dw1.d = -(int16_t)reg->dw1.ud;
 687       return true;
 688    case BRW_REGISTER_TYPE_F:
 689       reg->dw1.f = -reg->dw1.f;
 690       return true;
 691    case BRW_REGISTER_TYPE_VF:
 692       reg->dw1.ud ^= 0x80808080;
 693       return true;
 694    case BRW_REGISTER_TYPE_UB:
 695    case BRW_REGISTER_TYPE_B:
 696       unreachable("no UB/B immediates");
 697    case BRW_REGISTER_TYPE_UV:
 698    case BRW_REGISTER_TYPE_V:
 699       assert(!"unimplemented: negate UV/V immediate");
 700    case BRW_REGISTER_TYPE_UQ:
 701    case BRW_REGISTER_TYPE_Q:
 702       assert(!"unimplemented: negate UQ/Q immediate");
 703    case BRW_REGISTER_TYPE_DF:
 704    case BRW_REGISTER_TYPE_HF:
 705       assert(!"unimplemented: negate DF/HF immediate");
 706    }
 707
 708    return false;
 709 }
 710
 711 bool
 712 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 713 {
 714    switch (type) {
 715    case BRW_REGISTER_TYPE_D:
 716       reg->dw1.d = abs(reg->dw1.d);
 717       return true;
 718    case BRW_REGISTER_TYPE_W:
 719       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 720       return true;
 721    case BRW_REGISTER_TYPE_F:
 722       reg->dw1.f = fabsf(reg->dw1.f);
 723       return true;
 724    case BRW_REGISTER_TYPE_VF:
 725       reg->dw1.ud &= ~0x80808080;
 726       return true;
 727    case BRW_REGISTER_TYPE_UB:
 728    case BRW_REGISTER_TYPE_B:
 729       unreachable("no UB/B immediates");
 730    case BRW_REGISTER_TYPE_UQ:
 731    case BRW_REGISTER_TYPE_UD:
 732    case BRW_REGISTER_TYPE_UW:
 733    case BRW_REGISTER_TYPE_UV:
 734       /* Presumably the absolute value modifier on an unsigned source is a
 735        * nop, but it would be nice to confirm.
 736        */
 737       assert(!"unimplemented: abs unsigned immediate");
 738    case BRW_REGISTER_TYPE_V:
 739       assert(!"unimplemented: abs V immediate");
 740    case BRW_REGISTER_TYPE_Q:
 741       assert(!"unimplemented: abs Q immediate");
 742    case BRW_REGISTER_TYPE_DF:
 743    case BRW_REGISTER_TYPE_HF:
 744       assert(!"unimplemented: abs DF/HF immediate");
 745    }
 746
 747    return false;
 748 }
 749
 750 backend_visitor::backend_visitor(struct brw_context *brw,
 751                                  struct gl_shader_program *shader_prog,
 752                                  struct gl_program *prog,
 753                                  struct brw_stage_prog_data *stage_prog_data,
 754                                  gl_shader_stage stage)
 755    : brw(brw),
 756      devinfo(brw->intelScreen->devinfo),
 757      ctx(&brw->ctx),
 758      shader(shader_prog ?
 759         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 760      shader_prog(shader_prog),
 761      prog(prog),
 762      stage_prog_data(stage_prog_data),
 763      cfg(NULL),
 764      stage(stage)
 765 {
 766    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 767    stage_name = _mesa_shader_stage_to_string(stage);
 768    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 769 }
 770
 771 bool
 772 backend_reg::is_zero() const
 773 {
 774    if (file != IMM)
 775       return false;
 776
 777    return fixed_hw_reg.dw1.d == 0;
 778 }
 779
 780 bool
 781 backend_reg::is_one() const
 782 {
 783    if (file != IMM)
 784       return false;
 785
 786    return type == BRW_REGISTER_TYPE_F
 787           ? fixed_hw_reg.dw1.f == 1.0
 788           : fixed_hw_reg.dw1.d == 1;
 789 }
 790
 791 bool
 792 backend_reg::is_negative_one() const
 793 {
 794    if (file != IMM)
 795       return false;
 796
 797    switch (type) {
 798    case BRW_REGISTER_TYPE_F:
 799       return fixed_hw_reg.dw1.f == -1.0;
 800    case BRW_REGISTER_TYPE_D:
 801       return fixed_hw_reg.dw1.d == -1;
 802    default:
 803       return false;
 804    }
 805 }
 806
 807 bool
 808 backend_reg::is_null() const
 809 {
 810    return file == HW_REG &&
 811           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 812           fixed_hw_reg.nr == BRW_ARF_NULL;
 813 }
 814
 815
 816 bool
 817 backend_reg::is_accumulator() const
 818 {
 819    return file == HW_REG &&
 820           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 821           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 822 }
 823
 824 bool
 825 backend_reg::in_range(const backend_reg &r, unsigned n) const
 826 {
 827    return (file == r.file &&
 828            reg == r.reg &&
 829            reg_offset >= r.reg_offset &&
 830            reg_offset < r.reg_offset + n);
 831 }
 832
 833 bool
 834 backend_instruction::is_commutative() const
 835 {
 836    switch (opcode) {
 837    case BRW_OPCODE_AND:
 838    case BRW_OPCODE_OR:
 839    case BRW_OPCODE_XOR:
 840    case BRW_OPCODE_ADD:
 841    case BRW_OPCODE_MUL:
 842       return true;
 843    case BRW_OPCODE_SEL:
 844       /* MIN and MAX are commutative. */
 845       if (conditional_mod == BRW_CONDITIONAL_GE ||
 846           conditional_mod == BRW_CONDITIONAL_L) {
 847          return true;
 848       }
 849       /* fallthrough */
 850    default:
 851       return false;
 852    }
 853 }
 854
 855 bool
 856 backend_instruction::is_3src() const
 857 {
 858    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 859 }
 860
 861 bool
 862 backend_instruction::is_tex() const
 863 {
 864    return (opcode == SHADER_OPCODE_TEX ||
 865            opcode == FS_OPCODE_TXB ||
 866            opcode == SHADER_OPCODE_TXD ||
 867            opcode == SHADER_OPCODE_TXF ||
 868            opcode == SHADER_OPCODE_TXF_CMS ||
 869            opcode == SHADER_OPCODE_TXF_UMS ||
 870            opcode == SHADER_OPCODE_TXF_MCS ||
 871            opcode == SHADER_OPCODE_TXL ||
 872            opcode == SHADER_OPCODE_TXS ||
 873            opcode == SHADER_OPCODE_LOD ||
 874            opcode == SHADER_OPCODE_TG4 ||
 875            opcode == SHADER_OPCODE_TG4_OFFSET);
 876 }
 877
 878 bool
 879 backend_instruction::is_math() const
 880 {
 881    return (opcode == SHADER_OPCODE_RCP ||
 882            opcode == SHADER_OPCODE_RSQ ||
 883            opcode == SHADER_OPCODE_SQRT ||
 884            opcode == SHADER_OPCODE_EXP2 ||
 885            opcode == SHADER_OPCODE_LOG2 ||
 886            opcode == SHADER_OPCODE_SIN ||
 887            opcode == SHADER_OPCODE_COS ||
 888            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 889            opcode == SHADER_OPCODE_INT_REMAINDER ||
 890            opcode == SHADER_OPCODE_POW);
 891 }
 892
 893 bool
 894 backend_instruction::is_control_flow() const
 895 {
 896    switch (opcode) {
 897    case BRW_OPCODE_DO:
 898    case BRW_OPCODE_WHILE:
 899    case BRW_OPCODE_IF:
 900    case BRW_OPCODE_ELSE:
 901    case BRW_OPCODE_ENDIF:
 902    case BRW_OPCODE_BREAK:
 903    case BRW_OPCODE_CONTINUE:
 904       return true;
 905    default:
 906       return false;
 907    }
 908 }
 909
 910 bool
 911 backend_instruction::can_do_source_mods() const
 912 {
 913    switch (opcode) {
 914    case BRW_OPCODE_ADDC:
 915    case BRW_OPCODE_BFE:
 916    case BRW_OPCODE_BFI1:
 917    case BRW_OPCODE_BFI2:
 918    case BRW_OPCODE_BFREV:
 919    case BRW_OPCODE_CBIT:
 920    case BRW_OPCODE_FBH:
 921    case BRW_OPCODE_FBL:
 922    case BRW_OPCODE_SUBB:
 923       return false;
 924    default:
 925       return true;
 926    }
 927 }
 928
 929 bool
 930 backend_instruction::can_do_saturate() const
 931 {
 932    switch (opcode) {
 933    case BRW_OPCODE_ADD:
 934    case BRW_OPCODE_ASR:
 935    case BRW_OPCODE_AVG:
 936    case BRW_OPCODE_DP2:
 937    case BRW_OPCODE_DP3:
 938    case BRW_OPCODE_DP4:
 939    case BRW_OPCODE_DPH:
 940    case BRW_OPCODE_F16TO32:
 941    case BRW_OPCODE_F32TO16:
 942    case BRW_OPCODE_LINE:
 943    case BRW_OPCODE_LRP:
 944    case BRW_OPCODE_MAC:
 945    case BRW_OPCODE_MACH:
 946    case BRW_OPCODE_MAD:
 947    case BRW_OPCODE_MATH:
 948    case BRW_OPCODE_MOV:
 949    case BRW_OPCODE_MUL:
 950    case BRW_OPCODE_PLN:
 951    case BRW_OPCODE_RNDD:
 952    case BRW_OPCODE_RNDE:
 953    case BRW_OPCODE_RNDU:
 954    case BRW_OPCODE_RNDZ:
 955    case BRW_OPCODE_SEL:
 956    case BRW_OPCODE_SHL:
 957    case BRW_OPCODE_SHR:
 958    case FS_OPCODE_LINTERP:
 959    case SHADER_OPCODE_COS:
 960    case SHADER_OPCODE_EXP2:
 961    case SHADER_OPCODE_LOG2:
 962    case SHADER_OPCODE_POW:
 963    case SHADER_OPCODE_RCP:
 964    case SHADER_OPCODE_RSQ:
 965    case SHADER_OPCODE_SIN:
 966    case SHADER_OPCODE_SQRT:
 967       return true;
 968    default:
 969       return false;
 970    }
 971 }
 972
 973 bool
 974 backend_instruction::can_do_cmod() const
 975 {
 976    switch (opcode) {
 977    case BRW_OPCODE_ADD:
 978    case BRW_OPCODE_ADDC:
 979    case BRW_OPCODE_AND:
 980    case BRW_OPCODE_ASR:
 981    case BRW_OPCODE_AVG:
 982    case BRW_OPCODE_CMP:
 983    case BRW_OPCODE_CMPN:
 984    case BRW_OPCODE_DP2:
 985    case BRW_OPCODE_DP3:
 986    case BRW_OPCODE_DP4:
 987    case BRW_OPCODE_DPH:
 988    case BRW_OPCODE_F16TO32:
 989    case BRW_OPCODE_F32TO16:
 990    case BRW_OPCODE_FRC:
 991    case BRW_OPCODE_LINE:
 992    case BRW_OPCODE_LRP:
 993    case BRW_OPCODE_LZD:
 994    case BRW_OPCODE_MAC:
 995    case BRW_OPCODE_MACH:
 996    case BRW_OPCODE_MAD:
 997    case BRW_OPCODE_MOV:
 998    case BRW_OPCODE_MUL:
 999    case BRW_OPCODE_NOT:
1000    case BRW_OPCODE_OR:
1001    case BRW_OPCODE_PLN:
1002    case BRW_OPCODE_RNDD:
1003    case BRW_OPCODE_RNDE:
1004    case BRW_OPCODE_RNDU:
1005    case BRW_OPCODE_RNDZ:
1006    case BRW_OPCODE_SAD2:
1007    case BRW_OPCODE_SADA2:
1008    case BRW_OPCODE_SHL:
1009    case BRW_OPCODE_SHR:
1010    case BRW_OPCODE_SUBB:
1011    case BRW_OPCODE_XOR:
1012    case FS_OPCODE_CINTERP:
1013    case FS_OPCODE_LINTERP:
1014       return true;
1015    default:
1016       return false;
1017    }
1018 }
1019
1020 bool
1021 backend_instruction::reads_accumulator_implicitly() const
1022 {
1023    switch (opcode) {
1024    case BRW_OPCODE_MAC:
1025    case BRW_OPCODE_MACH:
1026    case BRW_OPCODE_SADA2:
1027       return true;
1028    default:
1029       return false;
1030    }
1031 }
1032
1033 bool
1034 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1035 {
1036    return writes_accumulator ||
1037           (devinfo->gen < 6 &&
1038            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1039             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1040              opcode != FS_OPCODE_CINTERP)));
1041 }
1042
1043 bool
1044 backend_instruction::has_side_effects() const
1045 {
1046    switch (opcode) {
1047    case SHADER_OPCODE_UNTYPED_ATOMIC:
1048    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1049    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1050    case SHADER_OPCODE_TYPED_ATOMIC:
1051    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1052    case SHADER_OPCODE_URB_WRITE_SIMD8:
1053    case FS_OPCODE_FB_WRITE:
1054       return true;
1055    default:
1056       return false;
1057    }
1058 }
1059
1060 #ifndef NDEBUG
1061 static bool
1062 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1063 {
1064    bool found = false;
1065    foreach_inst_in_block (backend_instruction, i, block) {
1066       if (inst == i) {
1067          found = true;
1068       }
1069    }
1070    return found;
1071 }
1072 #endif
1073
1074 static void
1075 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1076 {
1077    for (bblock_t *block_iter = start_block->next();
1078         !block_iter->link.is_tail_sentinel();
1079         block_iter = block_iter->next()) {
1080       block_iter->start_ip += ip_adjustment;
1081       block_iter->end_ip += ip_adjustment;
1082    }
1083 }
1084
1085 void
1086 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1087 {
1088    if (!this->is_head_sentinel())
1089       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1090
1091    block->end_ip++;
1092
1093    adjust_later_block_ips(block, 1);
1094
1095    exec_node::insert_after(inst);
1096 }
1097
1098 void
1099 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1100 {
1101    if (!this->is_tail_sentinel())
1102       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1103
1104    block->end_ip++;
1105
1106    adjust_later_block_ips(block, 1);
1107
1108    exec_node::insert_before(inst);
1109 }
1110
1111 void
1112 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1113 {
1114    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1115
1116    unsigned num_inst = list->length();
1117
1118    block->end_ip += num_inst;
1119
1120    adjust_later_block_ips(block, num_inst);
1121
1122    exec_node::insert_before(list);
1123 }
1124
1125 void
1126 backend_instruction::remove(bblock_t *block)
1127 {
1128    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1129
1130    adjust_later_block_ips(block, -1);
1131
1132    if (block->start_ip == block->end_ip) {
1133       block->cfg->remove_block(block);
1134    } else {
1135       block->end_ip--;
1136    }
1137
1138    exec_node::remove();
1139 }
1140
1141 void
1142 backend_visitor::dump_instructions()
1143 {
1144    dump_instructions(NULL);
1145 }
1146
1147 void
1148 backend_visitor::dump_instructions(const char *name)
1149 {
1150    FILE *file = stderr;
1151    if (name && geteuid() != 0) {
1152       file = fopen(name, "w");
1153       if (!file)
1154          file = stderr;
1155    }
1156
1157    if (cfg) {
1158       int ip = 0;
1159       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1160          fprintf(file, "%4d: ", ip++);
1161          dump_instruction(inst, file);
1162       }
1163    } else {
1164       int ip = 0;
1165       foreach_in_list(backend_instruction, inst, &instructions) {
1166          fprintf(file, "%4d: ", ip++);
1167          dump_instruction(inst, file);
1168       }
1169    }
1170
1171    if (file != stderr) {
1172       fclose(file);
1173    }
1174 }
1175
1176 void
1177 backend_visitor::calculate_cfg()
1178 {
1179    if (this->cfg)
1180       return;
1181    cfg = new(mem_ctx) cfg_t(&this->instructions);
1182 }
1183
1184 void
1185 backend_visitor::invalidate_cfg()
1186 {
1187    ralloc_free(this->cfg);
1188    this->cfg = NULL;
1189 }
1190
1191 /**
1192  * Sets up the starting offsets for the groups of binding table entries
1193  * commong to all pipeline stages.
1194  *
1195  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1196  * unused but also make sure that addition of small offsets to them will
1197  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1198  */
1199 void
1200 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1201 {
1202    int num_textures = _mesa_fls(prog->SamplersUsed);
1203
1204    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1205    next_binding_table_offset += num_textures;
1206
1207    if (shader) {
1208       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1209       next_binding_table_offset += shader->base.NumUniformBlocks;
1210    } else {
1211       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1212    }
1213
1214    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1215       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1216       next_binding_table_offset++;
1217    } else {
1218       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1219    }
1220
1221    if (prog->UsesGather) {
1222       if (devinfo->gen >= 8) {
1223          stage_prog_data->binding_table.gather_texture_start =
1224             stage_prog_data->binding_table.texture_start;
1225       } else {
1226          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1227          next_binding_table_offset += num_textures;
1228       }
1229    } else {
1230       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1231    }
1232
1233    if (shader_prog && shader_prog->NumAtomicBuffers) {
1234       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1235       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1236    } else {
1237       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1238    }
1239
1240    if (shader && shader->base.NumImages) {
1241       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1242       next_binding_table_offset += shader->base.NumImages;
1243    } else {
1244       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1245    }
1246
1247    /* This may or may not be used depending on how the compile goes. */
1248    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1249    next_binding_table_offset++;
1250
1251    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1252
1253    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1254 }