src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "brw_context.h"
  27 }
  28 #include "brw_vs.h"
  29 #include "brw_gs.h"
  30 #include "brw_fs.h"
  31 #include "brw_cfg.h"
  32 #include "glsl/ir_optimization.h"
  33 #include "glsl/glsl_parser_extras.h"
  34 #include "main/shaderapi.h"
  35
  36 struct gl_shader *
  37 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  38 {
  39    struct brw_shader *shader;
  40
  41    shader = rzalloc(NULL, struct brw_shader);
  42    if (shader) {
  43       shader->base.Type = type;
  44       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  45       shader->base.Name = name;
  46       _mesa_init_shader(ctx, &shader->base);
  47    }
  48
  49    return &shader->base;
  50 }
  51
  52 /**
  53  * Performs a compile of the shader stages even when we don't know
  54  * what non-orthogonal state will be set, in the hope that it reflects
  55  * the eventual NOS used, and thus allows us to produce link failures.
  56  */
  57 static bool
  58 brw_shader_precompile(struct gl_context *ctx,
  59                       struct gl_shader_program *sh_prog)
  60 {
  61    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  62    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  63    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  64
  65    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  66       return false;
  67
  68    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  69       return false;
  70
  71    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  72       return false;
  73
  74    return true;
  75 }
  76
  77 static inline bool
  78 is_scalar_shader_stage(struct brw_context *brw, int stage)
  79 {
  80    switch (stage) {
  81    case MESA_SHADER_FRAGMENT:
  82       return true;
  83    case MESA_SHADER_VERTEX:
  84       return brw->scalar_vs;
  85    default:
  86       return false;
  87    }
  88 }
  89
  90 static void
  91 brw_lower_packing_builtins(struct brw_context *brw,
  92                            gl_shader_stage shader_type,
  93                            exec_list *ir)
  94 {
  95    int ops = LOWER_PACK_SNORM_2x16
  96            | LOWER_UNPACK_SNORM_2x16
  97            | LOWER_PACK_UNORM_2x16
  98            | LOWER_UNPACK_UNORM_2x16;
  99
 100    if (is_scalar_shader_stage(brw, shader_type)) {
 101       ops |= LOWER_UNPACK_UNORM_4x8
 102            | LOWER_UNPACK_SNORM_4x8
 103            | LOWER_PACK_UNORM_4x8
 104            | LOWER_PACK_SNORM_4x8;
 105    }
 106
 107    if (brw->gen >= 7) {
 108       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 109        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 110        * lowering is needed. For SOA code, the Half2x16 ops must be
 111        * scalarized.
 112        */
 113       if (is_scalar_shader_stage(brw, shader_type)) {
 114          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 115              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 116       }
 117    } else {
 118       ops |= LOWER_PACK_HALF_2x16
 119           |  LOWER_UNPACK_HALF_2x16;
 120    }
 121
 122    lower_packing_builtins(ir, ops);
 123 }
 124
 125 GLboolean
 126 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 127 {
 128    struct brw_context *brw = brw_context(ctx);
 129    unsigned int stage;
 130
 131    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 132       const struct gl_shader_compiler_options *options =
 133          &ctx->Const.ShaderCompilerOptions[stage];
 134       struct brw_shader *shader =
 135          (struct brw_shader *)shProg->_LinkedShaders[stage];
 136
 137       if (!shader)
 138          continue;
 139
 140       struct gl_program *prog =
 141          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 142                                 shader->base.Name);
 143       if (!prog)
 144         return false;
 145       prog->Parameters = _mesa_new_parameter_list();
 146
 147       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 148
 149       bool progress;
 150
 151       /* lower_packing_builtins() inserts arithmetic instructions, so it
 152        * must precede lower_instructions().
 153        */
 154       brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->base.ir);
 155       do_mat_op_to_vec(shader->base.ir);
 156       const int bitfield_insert = brw->gen >= 7
 157                                   ? BITFIELD_INSERT_TO_BFM_BFI
 158                                   : 0;
 159       lower_instructions(shader->base.ir,
 160                          MOD_TO_FLOOR |
 161                          DIV_TO_MUL_RCP |
 162                          SUB_TO_ADD_NEG |
 163                          EXP_TO_EXP2 |
 164                          LOG_TO_LOG2 |
 165                          bitfield_insert |
 166                          LDEXP_TO_ARITH);
 167
 168       /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 169        * if-statements need to be flattened.
 170        */
 171       if (brw->gen < 6)
 172          lower_if_to_cond_assign(shader->base.ir, 16);
 173
 174       do_lower_texture_projection(shader->base.ir);
 175       brw_lower_texture_gradients(brw, shader->base.ir);
 176       do_vec_index_to_cond_assign(shader->base.ir);
 177       lower_vector_insert(shader->base.ir, true);
 178       brw_do_cubemap_normalize(shader->base.ir);
 179       lower_offset_arrays(shader->base.ir);
 180       brw_do_lower_unnormalized_offset(shader->base.ir);
 181       lower_noise(shader->base.ir);
 182       lower_quadop_vector(shader->base.ir, false);
 183
 184       bool lowered_variable_indexing =
 185          lower_variable_index_to_cond_assign(shader->base.ir,
 186                                              options->EmitNoIndirectInput,
 187                                              options->EmitNoIndirectOutput,
 188                                              options->EmitNoIndirectTemp,
 189                                              options->EmitNoIndirectUniform);
 190
 191       if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 192          perf_debug("Unsupported form of variable indexing in FS; falling "
 193                     "back to very inefficient code generation\n");
 194       }
 195
 196       lower_ubo_reference(&shader->base, shader->base.ir);
 197
 198       do {
 199          progress = false;
 200
 201          if (is_scalar_shader_stage(brw, stage)) {
 202             brw_do_channel_expressions(shader->base.ir);
 203             brw_do_vector_splitting(shader->base.ir);
 204          }
 205
 206          progress = do_lower_jumps(shader->base.ir, true, true,
 207                                    true, /* main return */
 208                                    false, /* continue */
 209                                    false /* loops */
 210                                    ) || progress;
 211
 212          progress = do_common_optimization(shader->base.ir, true, true,
 213                                            options, ctx->Const.NativeIntegers)
 214            || progress;
 215       } while (progress);
 216
 217       /* Make a pass over the IR to add state references for any built-in
 218        * uniforms that are used.  This has to be done now (during linking).
 219        * Code generation doesn't happen until the first time this shader is
 220        * used for rendering.  Waiting until then to generate the parameters is
 221        * too late.  At that point, the values for the built-in uniforms won't
 222        * get sent to the shader.
 223        */
 224       foreach_in_list(ir_instruction, node, shader->base.ir) {
 225          ir_variable *var = node->as_variable();
 226
 227          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 228              || (strncmp(var->name, "gl_", 3) != 0))
 229             continue;
 230
 231          const ir_state_slot *const slots = var->get_state_slots();
 232          assert(slots != NULL);
 233
 234          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 235             _mesa_add_state_reference(prog->Parameters,
 236                                       (gl_state_index *) slots[i].tokens);
 237          }
 238       }
 239
 240       validate_ir_tree(shader->base.ir);
 241
 242       do_set_program_inouts(shader->base.ir, prog, shader->base.Stage);
 243
 244       prog->SamplersUsed = shader->base.active_samplers;
 245       prog->ShadowSamplers = shader->base.shadow_samplers;
 246       _mesa_update_shader_textures_used(shProg, prog);
 247
 248       _mesa_reference_program(ctx, &shader->base.Program, prog);
 249
 250       brw_add_texrect_params(prog);
 251
 252       _mesa_reference_program(ctx, &prog, NULL);
 253
 254       if (ctx->_Shader->Flags & GLSL_DUMP) {
 255          fprintf(stderr, "\n");
 256          fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 257                  _mesa_shader_stage_to_string(shader->base.Stage),
 258                  shProg->Name);
 259          _mesa_print_ir(stderr, shader->base.ir, NULL);
 260          fprintf(stderr, "\n");
 261       }
 262    }
 263
 264    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 265       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 266          const struct gl_shader *sh = shProg->Shaders[i];
 267          if (!sh)
 268             continue;
 269
 270          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 271                  _mesa_shader_stage_to_string(sh->Stage),
 272                  i, shProg->Name);
 273          fprintf(stderr, "%s", sh->Source);
 274          fprintf(stderr, "\n");
 275       }
 276    }
 277
 278    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 279       return false;
 280
 281    return true;
 282 }
 283
 284
 285 enum brw_reg_type
 286 brw_type_for_base_type(const struct glsl_type *type)
 287 {
 288    switch (type->base_type) {
 289    case GLSL_TYPE_FLOAT:
 290       return BRW_REGISTER_TYPE_F;
 291    case GLSL_TYPE_INT:
 292    case GLSL_TYPE_BOOL:
 293       return BRW_REGISTER_TYPE_D;
 294    case GLSL_TYPE_UINT:
 295       return BRW_REGISTER_TYPE_UD;
 296    case GLSL_TYPE_ARRAY:
 297       return brw_type_for_base_type(type->fields.array);
 298    case GLSL_TYPE_STRUCT:
 299    case GLSL_TYPE_SAMPLER:
 300    case GLSL_TYPE_ATOMIC_UINT:
 301       /* These should be overridden with the type of the member when
 302        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 303        * way to trip up if we don't.
 304        */
 305       return BRW_REGISTER_TYPE_UD;
 306    case GLSL_TYPE_IMAGE:
 307       return BRW_REGISTER_TYPE_UD;
 308    case GLSL_TYPE_VOID:
 309    case GLSL_TYPE_ERROR:
 310    case GLSL_TYPE_INTERFACE:
 311       unreachable("not reached");
 312    }
 313
 314    return BRW_REGISTER_TYPE_F;
 315 }
 316
 317 enum brw_conditional_mod
 318 brw_conditional_for_comparison(unsigned int op)
 319 {
 320    switch (op) {
 321    case ir_binop_less:
 322       return BRW_CONDITIONAL_L;
 323    case ir_binop_greater:
 324       return BRW_CONDITIONAL_G;
 325    case ir_binop_lequal:
 326       return BRW_CONDITIONAL_LE;
 327    case ir_binop_gequal:
 328       return BRW_CONDITIONAL_GE;
 329    case ir_binop_equal:
 330    case ir_binop_all_equal: /* same as equal for scalars */
 331       return BRW_CONDITIONAL_Z;
 332    case ir_binop_nequal:
 333    case ir_binop_any_nequal: /* same as nequal for scalars */
 334       return BRW_CONDITIONAL_NZ;
 335    default:
 336       unreachable("not reached: bad operation for comparison");
 337    }
 338 }
 339
 340 uint32_t
 341 brw_math_function(enum opcode op)
 342 {
 343    switch (op) {
 344    case SHADER_OPCODE_RCP:
 345       return BRW_MATH_FUNCTION_INV;
 346    case SHADER_OPCODE_RSQ:
 347       return BRW_MATH_FUNCTION_RSQ;
 348    case SHADER_OPCODE_SQRT:
 349       return BRW_MATH_FUNCTION_SQRT;
 350    case SHADER_OPCODE_EXP2:
 351       return BRW_MATH_FUNCTION_EXP;
 352    case SHADER_OPCODE_LOG2:
 353       return BRW_MATH_FUNCTION_LOG;
 354    case SHADER_OPCODE_POW:
 355       return BRW_MATH_FUNCTION_POW;
 356    case SHADER_OPCODE_SIN:
 357       return BRW_MATH_FUNCTION_SIN;
 358    case SHADER_OPCODE_COS:
 359       return BRW_MATH_FUNCTION_COS;
 360    case SHADER_OPCODE_INT_QUOTIENT:
 361       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 362    case SHADER_OPCODE_INT_REMAINDER:
 363       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 364    default:
 365       unreachable("not reached: unknown math function");
 366    }
 367 }
 368
 369 uint32_t
 370 brw_texture_offset(struct gl_context *ctx, int *offsets,
 371                    unsigned num_components)
 372 {
 373    /* If the driver does not support GL_ARB_gpu_shader5, the offset
 374     * must be constant.
 375     */
 376    assert(offsets != NULL || ctx->Extensions.ARB_gpu_shader5);
 377
 378    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 379
 380    /* Combine all three offsets into a single unsigned dword:
 381     *
 382     *    bits 11:8 - U Offset (X component)
 383     *    bits  7:4 - V Offset (Y component)
 384     *    bits  3:0 - R Offset (Z component)
 385     */
 386    unsigned offset_bits = 0;
 387    for (unsigned i = 0; i < num_components; i++) {
 388       const unsigned shift = 4 * (2 - i);
 389       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 390    }
 391    return offset_bits;
 392 }
 393
 394 const char *
 395 brw_instruction_name(enum opcode op)
 396 {
 397    switch (op) {
 398    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 399       assert(opcode_descs[op].name);
 400       return opcode_descs[op].name;
 401    case FS_OPCODE_FB_WRITE:
 402       return "fb_write";
 403    case FS_OPCODE_BLORP_FB_WRITE:
 404       return "blorp_fb_write";
 405    case FS_OPCODE_REP_FB_WRITE:
 406       return "rep_fb_write";
 407
 408    case SHADER_OPCODE_RCP:
 409       return "rcp";
 410    case SHADER_OPCODE_RSQ:
 411       return "rsq";
 412    case SHADER_OPCODE_SQRT:
 413       return "sqrt";
 414    case SHADER_OPCODE_EXP2:
 415       return "exp2";
 416    case SHADER_OPCODE_LOG2:
 417       return "log2";
 418    case SHADER_OPCODE_POW:
 419       return "pow";
 420    case SHADER_OPCODE_INT_QUOTIENT:
 421       return "int_quot";
 422    case SHADER_OPCODE_INT_REMAINDER:
 423       return "int_rem";
 424    case SHADER_OPCODE_SIN:
 425       return "sin";
 426    case SHADER_OPCODE_COS:
 427       return "cos";
 428
 429    case SHADER_OPCODE_TEX:
 430       return "tex";
 431    case SHADER_OPCODE_TXD:
 432       return "txd";
 433    case SHADER_OPCODE_TXF:
 434       return "txf";
 435    case SHADER_OPCODE_TXL:
 436       return "txl";
 437    case SHADER_OPCODE_TXS:
 438       return "txs";
 439    case FS_OPCODE_TXB:
 440       return "txb";
 441    case SHADER_OPCODE_TXF_CMS:
 442       return "txf_cms";
 443    case SHADER_OPCODE_TXF_UMS:
 444       return "txf_ums";
 445    case SHADER_OPCODE_TXF_MCS:
 446       return "txf_mcs";
 447    case SHADER_OPCODE_LOD:
 448       return "lod";
 449    case SHADER_OPCODE_TG4:
 450       return "tg4";
 451    case SHADER_OPCODE_TG4_OFFSET:
 452       return "tg4_offset";
 453    case SHADER_OPCODE_SHADER_TIME_ADD:
 454       return "shader_time_add";
 455
 456    case SHADER_OPCODE_UNTYPED_ATOMIC:
 457       return "untyped_atomic";
 458    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 459       return "untyped_surface_read";
 460
 461    case SHADER_OPCODE_LOAD_PAYLOAD:
 462       return "load_payload";
 463
 464    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 465       return "gen4_scratch_read";
 466    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 467       return "gen4_scratch_write";
 468    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 469       return "gen7_scratch_read";
 470    case SHADER_OPCODE_URB_WRITE_SIMD8:
 471       return "gen8_urb_write_simd8";
 472
 473    case VEC4_OPCODE_PACK_BYTES:
 474       return "pack_bytes";
 475    case VEC4_OPCODE_UNPACK_UNIFORM:
 476       return "unpack_uniform";
 477
 478    case FS_OPCODE_DDX_COARSE:
 479       return "ddx_coarse";
 480    case FS_OPCODE_DDX_FINE:
 481       return "ddx_fine";
 482    case FS_OPCODE_DDY_COARSE:
 483       return "ddy_coarse";
 484    case FS_OPCODE_DDY_FINE:
 485       return "ddy_fine";
 486
 487    case FS_OPCODE_PIXEL_X:
 488       return "pixel_x";
 489    case FS_OPCODE_PIXEL_Y:
 490       return "pixel_y";
 491
 492    case FS_OPCODE_CINTERP:
 493       return "cinterp";
 494    case FS_OPCODE_LINTERP:
 495       return "linterp";
 496
 497    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 498       return "uniform_pull_const";
 499    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 500       return "uniform_pull_const_gen7";
 501    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 502       return "varying_pull_const";
 503    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 504       return "varying_pull_const_gen7";
 505
 506    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 507       return "mov_dispatch_to_flags";
 508    case FS_OPCODE_DISCARD_JUMP:
 509       return "discard_jump";
 510
 511    case FS_OPCODE_SET_OMASK:
 512       return "set_omask";
 513    case FS_OPCODE_SET_SAMPLE_ID:
 514       return "set_sample_id";
 515    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 516       return "set_simd4x2_offset";
 517
 518    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 519       return "pack_half_2x16_split";
 520    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 521       return "unpack_half_2x16_split_x";
 522    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 523       return "unpack_half_2x16_split_y";
 524
 525    case FS_OPCODE_PLACEHOLDER_HALT:
 526       return "placeholder_halt";
 527
 528    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 529       return "interp_centroid";
 530    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 531       return "interp_sample";
 532    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 533       return "interp_shared_offset";
 534    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 535       return "interp_per_slot_offset";
 536
 537    case VS_OPCODE_URB_WRITE:
 538       return "vs_urb_write";
 539    case VS_OPCODE_PULL_CONSTANT_LOAD:
 540       return "pull_constant_load";
 541    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 542       return "pull_constant_load_gen7";
 543    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 544       return "unpack_flags_simd4x2";
 545
 546    case GS_OPCODE_URB_WRITE:
 547       return "gs_urb_write";
 548    case GS_OPCODE_URB_WRITE_ALLOCATE:
 549       return "gs_urb_write_allocate";
 550    case GS_OPCODE_THREAD_END:
 551       return "gs_thread_end";
 552    case GS_OPCODE_SET_WRITE_OFFSET:
 553       return "set_write_offset";
 554    case GS_OPCODE_SET_VERTEX_COUNT:
 555       return "set_vertex_count";
 556    case GS_OPCODE_SET_DWORD_2:
 557       return "set_dword_2";
 558    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 559       return "prepare_channel_masks";
 560    case GS_OPCODE_SET_CHANNEL_MASKS:
 561       return "set_channel_masks";
 562    case GS_OPCODE_GET_INSTANCE_ID:
 563       return "get_instance_id";
 564    case GS_OPCODE_FF_SYNC:
 565       return "ff_sync";
 566    case GS_OPCODE_SET_PRIMITIVE_ID:
 567       return "set_primitive_id";
 568    case GS_OPCODE_SVB_WRITE:
 569       return "gs_svb_write";
 570    case GS_OPCODE_SVB_SET_DST_INDEX:
 571       return "gs_svb_set_dst_index";
 572    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 573       return "gs_ff_sync_set_primitives";
 574    }
 575
 576    unreachable("not reached");
 577 }
 578
 579 bool
 580 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 581 {
 582    union {
 583       unsigned ud;
 584       int d;
 585       float f;
 586    } imm = { reg->dw1.ud }, sat_imm;
 587
 588    switch (type) {
 589    case BRW_REGISTER_TYPE_UD:
 590    case BRW_REGISTER_TYPE_D:
 591    case BRW_REGISTER_TYPE_UQ:
 592    case BRW_REGISTER_TYPE_Q:
 593       /* Nothing to do. */
 594       return false;
 595    case BRW_REGISTER_TYPE_UW:
 596       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 597       break;
 598    case BRW_REGISTER_TYPE_W:
 599       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 600       break;
 601    case BRW_REGISTER_TYPE_F:
 602       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 603       break;
 604    case BRW_REGISTER_TYPE_UB:
 605    case BRW_REGISTER_TYPE_B:
 606       unreachable("no UB/B immediates");
 607    case BRW_REGISTER_TYPE_V:
 608    case BRW_REGISTER_TYPE_UV:
 609    case BRW_REGISTER_TYPE_VF:
 610       unreachable("unimplemented: saturate vector immediate");
 611    case BRW_REGISTER_TYPE_DF:
 612    case BRW_REGISTER_TYPE_HF:
 613       unreachable("unimplemented: saturate DF/HF immediate");
 614    }
 615
 616    if (imm.ud != sat_imm.ud) {
 617       reg->dw1.ud = sat_imm.ud;
 618       return true;
 619    }
 620    return false;
 621 }
 622
 623 bool
 624 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 625 {
 626    switch (type) {
 627    case BRW_REGISTER_TYPE_D:
 628    case BRW_REGISTER_TYPE_UD:
 629       reg->dw1.d = -reg->dw1.d;
 630       return true;
 631    case BRW_REGISTER_TYPE_W:
 632    case BRW_REGISTER_TYPE_UW:
 633       reg->dw1.d = -(int16_t)reg->dw1.ud;
 634       return true;
 635    case BRW_REGISTER_TYPE_F:
 636       reg->dw1.f = -reg->dw1.f;
 637       return true;
 638    case BRW_REGISTER_TYPE_VF:
 639       reg->dw1.ud ^= 0x80808080;
 640       return true;
 641    case BRW_REGISTER_TYPE_UB:
 642    case BRW_REGISTER_TYPE_B:
 643       unreachable("no UB/B immediates");
 644    case BRW_REGISTER_TYPE_UV:
 645    case BRW_REGISTER_TYPE_V:
 646       assert(!"unimplemented: negate UV/V immediate");
 647    case BRW_REGISTER_TYPE_UQ:
 648    case BRW_REGISTER_TYPE_Q:
 649       assert(!"unimplemented: negate UQ/Q immediate");
 650    case BRW_REGISTER_TYPE_DF:
 651    case BRW_REGISTER_TYPE_HF:
 652       assert(!"unimplemented: negate DF/HF immediate");
 653    }
 654
 655    return false;
 656 }
 657
 658 bool
 659 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 660 {
 661    switch (type) {
 662    case BRW_REGISTER_TYPE_D:
 663       reg->dw1.d = abs(reg->dw1.d);
 664       return true;
 665    case BRW_REGISTER_TYPE_W:
 666       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 667       return true;
 668    case BRW_REGISTER_TYPE_F:
 669       reg->dw1.f = fabsf(reg->dw1.f);
 670       return true;
 671    case BRW_REGISTER_TYPE_VF:
 672       reg->dw1.ud &= ~0x80808080;
 673       return true;
 674    case BRW_REGISTER_TYPE_UB:
 675    case BRW_REGISTER_TYPE_B:
 676       unreachable("no UB/B immediates");
 677    case BRW_REGISTER_TYPE_UQ:
 678    case BRW_REGISTER_TYPE_UD:
 679    case BRW_REGISTER_TYPE_UW:
 680    case BRW_REGISTER_TYPE_UV:
 681       /* Presumably the absolute value modifier on an unsigned source is a
 682        * nop, but it would be nice to confirm.
 683        */
 684       assert(!"unimplemented: abs unsigned immediate");
 685    case BRW_REGISTER_TYPE_V:
 686       assert(!"unimplemented: abs V immediate");
 687    case BRW_REGISTER_TYPE_Q:
 688       assert(!"unimplemented: abs Q immediate");
 689    case BRW_REGISTER_TYPE_DF:
 690    case BRW_REGISTER_TYPE_HF:
 691       assert(!"unimplemented: abs DF/HF immediate");
 692    }
 693
 694    return false;
 695 }
 696
 697 backend_visitor::backend_visitor(struct brw_context *brw,
 698                                  struct gl_shader_program *shader_prog,
 699                                  struct gl_program *prog,
 700                                  struct brw_stage_prog_data *stage_prog_data,
 701                                  gl_shader_stage stage)
 702    : brw(brw),
 703      ctx(&brw->ctx),
 704      shader(shader_prog ?
 705         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 706      shader_prog(shader_prog),
 707      prog(prog),
 708      stage_prog_data(stage_prog_data),
 709      cfg(NULL),
 710      stage(stage)
 711 {
 712 }
 713
 714 bool
 715 backend_reg::is_zero() const
 716 {
 717    if (file != IMM)
 718       return false;
 719
 720    return fixed_hw_reg.dw1.d == 0;
 721 }
 722
 723 bool
 724 backend_reg::is_one() const
 725 {
 726    if (file != IMM)
 727       return false;
 728
 729    return type == BRW_REGISTER_TYPE_F
 730           ? fixed_hw_reg.dw1.f == 1.0
 731           : fixed_hw_reg.dw1.d == 1;
 732 }
 733
 734 bool
 735 backend_reg::is_null() const
 736 {
 737    return file == HW_REG &&
 738           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 739           fixed_hw_reg.nr == BRW_ARF_NULL;
 740 }
 741
 742
 743 bool
 744 backend_reg::is_accumulator() const
 745 {
 746    return file == HW_REG &&
 747           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 748           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 749 }
 750
 751 bool
 752 backend_instruction::is_3src() const
 753 {
 754    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 755 }
 756
 757 bool
 758 backend_instruction::is_tex() const
 759 {
 760    return (opcode == SHADER_OPCODE_TEX ||
 761            opcode == FS_OPCODE_TXB ||
 762            opcode == SHADER_OPCODE_TXD ||
 763            opcode == SHADER_OPCODE_TXF ||
 764            opcode == SHADER_OPCODE_TXF_CMS ||
 765            opcode == SHADER_OPCODE_TXF_UMS ||
 766            opcode == SHADER_OPCODE_TXF_MCS ||
 767            opcode == SHADER_OPCODE_TXL ||
 768            opcode == SHADER_OPCODE_TXS ||
 769            opcode == SHADER_OPCODE_LOD ||
 770            opcode == SHADER_OPCODE_TG4 ||
 771            opcode == SHADER_OPCODE_TG4_OFFSET);
 772 }
 773
 774 bool
 775 backend_instruction::is_math() const
 776 {
 777    return (opcode == SHADER_OPCODE_RCP ||
 778            opcode == SHADER_OPCODE_RSQ ||
 779            opcode == SHADER_OPCODE_SQRT ||
 780            opcode == SHADER_OPCODE_EXP2 ||
 781            opcode == SHADER_OPCODE_LOG2 ||
 782            opcode == SHADER_OPCODE_SIN ||
 783            opcode == SHADER_OPCODE_COS ||
 784            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 785            opcode == SHADER_OPCODE_INT_REMAINDER ||
 786            opcode == SHADER_OPCODE_POW);
 787 }
 788
 789 bool
 790 backend_instruction::is_control_flow() const
 791 {
 792    switch (opcode) {
 793    case BRW_OPCODE_DO:
 794    case BRW_OPCODE_WHILE:
 795    case BRW_OPCODE_IF:
 796    case BRW_OPCODE_ELSE:
 797    case BRW_OPCODE_ENDIF:
 798    case BRW_OPCODE_BREAK:
 799    case BRW_OPCODE_CONTINUE:
 800       return true;
 801    default:
 802       return false;
 803    }
 804 }
 805
 806 bool
 807 backend_instruction::can_do_source_mods() const
 808 {
 809    switch (opcode) {
 810    case BRW_OPCODE_ADDC:
 811    case BRW_OPCODE_BFE:
 812    case BRW_OPCODE_BFI1:
 813    case BRW_OPCODE_BFI2:
 814    case BRW_OPCODE_BFREV:
 815    case BRW_OPCODE_CBIT:
 816    case BRW_OPCODE_FBH:
 817    case BRW_OPCODE_FBL:
 818    case BRW_OPCODE_SUBB:
 819       return false;
 820    default:
 821       return true;
 822    }
 823 }
 824
 825 bool
 826 backend_instruction::can_do_saturate() const
 827 {
 828    switch (opcode) {
 829    case BRW_OPCODE_ADD:
 830    case BRW_OPCODE_ASR:
 831    case BRW_OPCODE_AVG:
 832    case BRW_OPCODE_DP2:
 833    case BRW_OPCODE_DP3:
 834    case BRW_OPCODE_DP4:
 835    case BRW_OPCODE_DPH:
 836    case BRW_OPCODE_F16TO32:
 837    case BRW_OPCODE_F32TO16:
 838    case BRW_OPCODE_LINE:
 839    case BRW_OPCODE_LRP:
 840    case BRW_OPCODE_MAC:
 841    case BRW_OPCODE_MACH:
 842    case BRW_OPCODE_MAD:
 843    case BRW_OPCODE_MATH:
 844    case BRW_OPCODE_MOV:
 845    case BRW_OPCODE_MUL:
 846    case BRW_OPCODE_PLN:
 847    case BRW_OPCODE_RNDD:
 848    case BRW_OPCODE_RNDE:
 849    case BRW_OPCODE_RNDU:
 850    case BRW_OPCODE_RNDZ:
 851    case BRW_OPCODE_SEL:
 852    case BRW_OPCODE_SHL:
 853    case BRW_OPCODE_SHR:
 854    case FS_OPCODE_LINTERP:
 855    case SHADER_OPCODE_COS:
 856    case SHADER_OPCODE_EXP2:
 857    case SHADER_OPCODE_LOG2:
 858    case SHADER_OPCODE_POW:
 859    case SHADER_OPCODE_RCP:
 860    case SHADER_OPCODE_RSQ:
 861    case SHADER_OPCODE_SIN:
 862    case SHADER_OPCODE_SQRT:
 863       return true;
 864    default:
 865       return false;
 866    }
 867 }
 868
 869 bool
 870 backend_instruction::can_do_cmod() const
 871 {
 872    switch (opcode) {
 873    case BRW_OPCODE_ADD:
 874    case BRW_OPCODE_ADDC:
 875    case BRW_OPCODE_AND:
 876    case BRW_OPCODE_ASR:
 877    case BRW_OPCODE_AVG:
 878    case BRW_OPCODE_CMP:
 879    case BRW_OPCODE_CMPN:
 880    case BRW_OPCODE_DP2:
 881    case BRW_OPCODE_DP3:
 882    case BRW_OPCODE_DP4:
 883    case BRW_OPCODE_DPH:
 884    case BRW_OPCODE_F16TO32:
 885    case BRW_OPCODE_F32TO16:
 886    case BRW_OPCODE_FRC:
 887    case BRW_OPCODE_LINE:
 888    case BRW_OPCODE_LRP:
 889    case BRW_OPCODE_LZD:
 890    case BRW_OPCODE_MAC:
 891    case BRW_OPCODE_MACH:
 892    case BRW_OPCODE_MAD:
 893    case BRW_OPCODE_MOV:
 894    case BRW_OPCODE_MUL:
 895    case BRW_OPCODE_NOT:
 896    case BRW_OPCODE_OR:
 897    case BRW_OPCODE_PLN:
 898    case BRW_OPCODE_RNDD:
 899    case BRW_OPCODE_RNDE:
 900    case BRW_OPCODE_RNDU:
 901    case BRW_OPCODE_RNDZ:
 902    case BRW_OPCODE_SAD2:
 903    case BRW_OPCODE_SADA2:
 904    case BRW_OPCODE_SHL:
 905    case BRW_OPCODE_SHR:
 906    case BRW_OPCODE_SUBB:
 907    case BRW_OPCODE_XOR:
 908    case FS_OPCODE_CINTERP:
 909    case FS_OPCODE_LINTERP:
 910       return true;
 911    default:
 912       return false;
 913    }
 914 }
 915
 916 bool
 917 backend_instruction::reads_accumulator_implicitly() const
 918 {
 919    switch (opcode) {
 920    case BRW_OPCODE_MAC:
 921    case BRW_OPCODE_MACH:
 922    case BRW_OPCODE_SADA2:
 923       return true;
 924    default:
 925       return false;
 926    }
 927 }
 928
 929 bool
 930 backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
 931 {
 932    return writes_accumulator ||
 933           (brw->gen < 6 &&
 934            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 935             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 936              opcode != FS_OPCODE_CINTERP)));
 937 }
 938
 939 bool
 940 backend_instruction::has_side_effects() const
 941 {
 942    switch (opcode) {
 943    case SHADER_OPCODE_UNTYPED_ATOMIC:
 944    case SHADER_OPCODE_URB_WRITE_SIMD8:
 945    case FS_OPCODE_FB_WRITE:
 946       return true;
 947    default:
 948       return false;
 949    }
 950 }
 951
 952 #ifndef NDEBUG
 953 static bool
 954 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 955 {
 956    bool found = false;
 957    foreach_inst_in_block (backend_instruction, i, block) {
 958       if (inst == i) {
 959          found = true;
 960       }
 961    }
 962    return found;
 963 }
 964 #endif
 965
 966 static void
 967 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 968 {
 969    for (bblock_t *block_iter = start_block->next();
 970         !block_iter->link.is_tail_sentinel();
 971         block_iter = block_iter->next()) {
 972       block_iter->start_ip += ip_adjustment;
 973       block_iter->end_ip += ip_adjustment;
 974    }
 975 }
 976
 977 void
 978 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
 979 {
 980    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 981
 982    block->end_ip++;
 983
 984    adjust_later_block_ips(block, 1);
 985
 986    exec_node::insert_after(inst);
 987 }
 988
 989 void
 990 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
 991 {
 992    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 993
 994    block->end_ip++;
 995
 996    adjust_later_block_ips(block, 1);
 997
 998    exec_node::insert_before(inst);
 999 }
1000
1001 void
1002 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1003 {
1004    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1005
1006    unsigned num_inst = list->length();
1007
1008    block->end_ip += num_inst;
1009
1010    adjust_later_block_ips(block, num_inst);
1011
1012    exec_node::insert_before(list);
1013 }
1014
1015 void
1016 backend_instruction::remove(bblock_t *block)
1017 {
1018    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1019
1020    adjust_later_block_ips(block, -1);
1021
1022    if (block->start_ip == block->end_ip) {
1023       block->cfg->remove_block(block);
1024    } else {
1025       block->end_ip--;
1026    }
1027
1028    exec_node::remove();
1029 }
1030
1031 void
1032 backend_visitor::dump_instructions()
1033 {
1034    dump_instructions(NULL);
1035 }
1036
1037 void
1038 backend_visitor::dump_instructions(const char *name)
1039 {
1040    FILE *file = stderr;
1041    if (name && geteuid() != 0) {
1042       file = fopen(name, "w");
1043       if (!file)
1044          file = stderr;
1045    }
1046
1047    int ip = 0;
1048    foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1049       if (!name)
1050          fprintf(stderr, "%d: ", ip++);
1051       dump_instruction(inst, file);
1052    }
1053
1054    if (file != stderr) {
1055       fclose(file);
1056    }
1057 }
1058
1059 void
1060 backend_visitor::calculate_cfg()
1061 {
1062    if (this->cfg)
1063       return;
1064    cfg = new(mem_ctx) cfg_t(&this->instructions);
1065 }
1066
1067 void
1068 backend_visitor::invalidate_cfg()
1069 {
1070    ralloc_free(this->cfg);
1071    this->cfg = NULL;
1072 }
1073
1074 /**
1075  * Sets up the starting offsets for the groups of binding table entries
1076  * commong to all pipeline stages.
1077  *
1078  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1079  * unused but also make sure that addition of small offsets to them will
1080  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1081  */
1082 void
1083 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1084 {
1085    int num_textures = _mesa_fls(prog->SamplersUsed);
1086
1087    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1088    next_binding_table_offset += num_textures;
1089
1090    if (shader) {
1091       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1092       next_binding_table_offset += shader->base.NumUniformBlocks;
1093    } else {
1094       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1095    }
1096
1097    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1098       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1099       next_binding_table_offset++;
1100    } else {
1101       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1102    }
1103
1104    if (prog->UsesGather) {
1105       if (brw->gen >= 8) {
1106          stage_prog_data->binding_table.gather_texture_start =
1107             stage_prog_data->binding_table.texture_start;
1108       } else {
1109          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1110          next_binding_table_offset += num_textures;
1111       }
1112    } else {
1113       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1114    }
1115
1116    if (shader_prog && shader_prog->NumAtomicBuffers) {
1117       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1118       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1119    } else {
1120       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1121    }
1122
1123    if (shader && shader->base.NumImages) {
1124       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1125       next_binding_table_offset += shader->base.NumImages;
1126    } else {
1127       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1128    }
1129
1130    /* This may or may not be used depending on how the compile goes. */
1131    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1132    next_binding_table_offset++;
1133
1134    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1135
1136    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1137 }