2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
29 #include "brw_vec4_tes.h"
30 #include "main/uniforms.h"
33 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
36 assert(surf_index
< BRW_MAX_SURFACES
);
38 prog_data
->binding_table
.size_bytes
=
39 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
43 brw_type_for_base_type(const struct glsl_type
*type
)
45 switch (type
->base_type
) {
47 return BRW_REGISTER_TYPE_F
;
50 case GLSL_TYPE_SUBROUTINE
:
51 return BRW_REGISTER_TYPE_D
;
53 return BRW_REGISTER_TYPE_UD
;
55 return brw_type_for_base_type(type
->fields
.array
);
56 case GLSL_TYPE_STRUCT
:
57 case GLSL_TYPE_SAMPLER
:
58 case GLSL_TYPE_ATOMIC_UINT
:
59 /* These should be overridden with the type of the member when
60 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
61 * way to trip up if we don't.
63 return BRW_REGISTER_TYPE_UD
;
65 return BRW_REGISTER_TYPE_UD
;
66 case GLSL_TYPE_DOUBLE
:
67 return BRW_REGISTER_TYPE_DF
;
70 case GLSL_TYPE_INTERFACE
:
71 case GLSL_TYPE_FUNCTION
:
72 unreachable("not reached");
75 return BRW_REGISTER_TYPE_F
;
78 enum brw_conditional_mod
79 brw_conditional_for_comparison(unsigned int op
)
83 return BRW_CONDITIONAL_L
;
84 case ir_binop_greater
:
85 return BRW_CONDITIONAL_G
;
87 return BRW_CONDITIONAL_LE
;
89 return BRW_CONDITIONAL_GE
;
91 case ir_binop_all_equal
: /* same as equal for scalars */
92 return BRW_CONDITIONAL_Z
;
94 case ir_binop_any_nequal
: /* same as nequal for scalars */
95 return BRW_CONDITIONAL_NZ
;
97 unreachable("not reached: bad operation for comparison");
102 brw_math_function(enum opcode op
)
105 case SHADER_OPCODE_RCP
:
106 return BRW_MATH_FUNCTION_INV
;
107 case SHADER_OPCODE_RSQ
:
108 return BRW_MATH_FUNCTION_RSQ
;
109 case SHADER_OPCODE_SQRT
:
110 return BRW_MATH_FUNCTION_SQRT
;
111 case SHADER_OPCODE_EXP2
:
112 return BRW_MATH_FUNCTION_EXP
;
113 case SHADER_OPCODE_LOG2
:
114 return BRW_MATH_FUNCTION_LOG
;
115 case SHADER_OPCODE_POW
:
116 return BRW_MATH_FUNCTION_POW
;
117 case SHADER_OPCODE_SIN
:
118 return BRW_MATH_FUNCTION_SIN
;
119 case SHADER_OPCODE_COS
:
120 return BRW_MATH_FUNCTION_COS
;
121 case SHADER_OPCODE_INT_QUOTIENT
:
122 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
123 case SHADER_OPCODE_INT_REMAINDER
:
124 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
126 unreachable("not reached: unknown math function");
131 brw_texture_offset(int *offsets
, unsigned num_components
)
133 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
135 /* Combine all three offsets into a single unsigned dword:
137 * bits 11:8 - U Offset (X component)
138 * bits 7:4 - V Offset (Y component)
139 * bits 3:0 - R Offset (Z component)
141 unsigned offset_bits
= 0;
142 for (unsigned i
= 0; i
< num_components
; i
++) {
143 const unsigned shift
= 4 * (2 - i
);
144 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
150 brw_instruction_name(const struct brw_device_info
*devinfo
, enum opcode op
)
153 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
154 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
155 * start of a loop in the IR.
157 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
160 assert(brw_opcode_desc(devinfo
, op
)->name
);
161 return brw_opcode_desc(devinfo
, op
)->name
;
162 case FS_OPCODE_FB_WRITE
:
164 case FS_OPCODE_FB_WRITE_LOGICAL
:
165 return "fb_write_logical";
166 case FS_OPCODE_REP_FB_WRITE
:
167 return "rep_fb_write";
168 case FS_OPCODE_FB_READ
:
170 case FS_OPCODE_FB_READ_LOGICAL
:
171 return "fb_read_logical";
173 case SHADER_OPCODE_RCP
:
175 case SHADER_OPCODE_RSQ
:
177 case SHADER_OPCODE_SQRT
:
179 case SHADER_OPCODE_EXP2
:
181 case SHADER_OPCODE_LOG2
:
183 case SHADER_OPCODE_POW
:
185 case SHADER_OPCODE_INT_QUOTIENT
:
187 case SHADER_OPCODE_INT_REMAINDER
:
189 case SHADER_OPCODE_SIN
:
191 case SHADER_OPCODE_COS
:
194 case SHADER_OPCODE_TEX
:
196 case SHADER_OPCODE_TEX_LOGICAL
:
197 return "tex_logical";
198 case SHADER_OPCODE_TXD
:
200 case SHADER_OPCODE_TXD_LOGICAL
:
201 return "txd_logical";
202 case SHADER_OPCODE_TXF
:
204 case SHADER_OPCODE_TXF_LOGICAL
:
205 return "txf_logical";
206 case SHADER_OPCODE_TXF_LZ
:
208 case SHADER_OPCODE_TXL
:
210 case SHADER_OPCODE_TXL_LOGICAL
:
211 return "txl_logical";
212 case SHADER_OPCODE_TXL_LZ
:
214 case SHADER_OPCODE_TXS
:
216 case SHADER_OPCODE_TXS_LOGICAL
:
217 return "txs_logical";
220 case FS_OPCODE_TXB_LOGICAL
:
221 return "txb_logical";
222 case SHADER_OPCODE_TXF_CMS
:
224 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
225 return "txf_cms_logical";
226 case SHADER_OPCODE_TXF_CMS_W
:
228 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
229 return "txf_cms_w_logical";
230 case SHADER_OPCODE_TXF_UMS
:
232 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
233 return "txf_ums_logical";
234 case SHADER_OPCODE_TXF_MCS
:
236 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
237 return "txf_mcs_logical";
238 case SHADER_OPCODE_LOD
:
240 case SHADER_OPCODE_LOD_LOGICAL
:
241 return "lod_logical";
242 case SHADER_OPCODE_TG4
:
244 case SHADER_OPCODE_TG4_LOGICAL
:
245 return "tg4_logical";
246 case SHADER_OPCODE_TG4_OFFSET
:
248 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
249 return "tg4_offset_logical";
250 case SHADER_OPCODE_SAMPLEINFO
:
252 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
253 return "sampleinfo_logical";
255 case SHADER_OPCODE_SHADER_TIME_ADD
:
256 return "shader_time_add";
258 case SHADER_OPCODE_UNTYPED_ATOMIC
:
259 return "untyped_atomic";
260 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
261 return "untyped_atomic_logical";
262 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
263 return "untyped_surface_read";
264 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
265 return "untyped_surface_read_logical";
266 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
267 return "untyped_surface_write";
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
269 return "untyped_surface_write_logical";
270 case SHADER_OPCODE_TYPED_ATOMIC
:
271 return "typed_atomic";
272 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
273 return "typed_atomic_logical";
274 case SHADER_OPCODE_TYPED_SURFACE_READ
:
275 return "typed_surface_read";
276 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
277 return "typed_surface_read_logical";
278 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
279 return "typed_surface_write";
280 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
281 return "typed_surface_write_logical";
282 case SHADER_OPCODE_MEMORY_FENCE
:
283 return "memory_fence";
285 case SHADER_OPCODE_LOAD_PAYLOAD
:
286 return "load_payload";
290 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
291 return "gen4_scratch_read";
292 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
293 return "gen4_scratch_write";
294 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
295 return "gen7_scratch_read";
296 case SHADER_OPCODE_URB_WRITE_SIMD8
:
297 return "gen8_urb_write_simd8";
298 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
299 return "gen8_urb_write_simd8_per_slot";
300 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
301 return "gen8_urb_write_simd8_masked";
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
303 return "gen8_urb_write_simd8_masked_per_slot";
304 case SHADER_OPCODE_URB_READ_SIMD8
:
305 return "urb_read_simd8";
306 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
307 return "urb_read_simd8_per_slot";
309 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
310 return "find_live_channel";
311 case SHADER_OPCODE_BROADCAST
:
314 case VEC4_OPCODE_MOV_BYTES
:
316 case VEC4_OPCODE_PACK_BYTES
:
318 case VEC4_OPCODE_UNPACK_UNIFORM
:
319 return "unpack_uniform";
321 case FS_OPCODE_DDX_COARSE
:
323 case FS_OPCODE_DDX_FINE
:
325 case FS_OPCODE_DDY_COARSE
:
327 case FS_OPCODE_DDY_FINE
:
330 case FS_OPCODE_CINTERP
:
332 case FS_OPCODE_LINTERP
:
335 case FS_OPCODE_PIXEL_X
:
337 case FS_OPCODE_PIXEL_Y
:
340 case FS_OPCODE_GET_BUFFER_SIZE
:
341 return "fs_get_buffer_size";
343 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
344 return "uniform_pull_const";
345 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
346 return "uniform_pull_const_gen7";
347 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
348 return "varying_pull_const_gen4";
349 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
350 return "varying_pull_const_gen7";
351 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
352 return "varying_pull_const_logical";
354 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
355 return "mov_dispatch_to_flags";
356 case FS_OPCODE_DISCARD_JUMP
:
357 return "discard_jump";
359 case FS_OPCODE_SET_SAMPLE_ID
:
360 return "set_sample_id";
361 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
362 return "set_simd4x2_offset";
364 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
365 return "pack_half_2x16_split";
366 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
367 return "unpack_half_2x16_split_x";
368 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
369 return "unpack_half_2x16_split_y";
371 case FS_OPCODE_PLACEHOLDER_HALT
:
372 return "placeholder_halt";
374 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
375 return "interp_sample";
376 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
377 return "interp_shared_offset";
378 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
379 return "interp_per_slot_offset";
381 case VS_OPCODE_URB_WRITE
:
382 return "vs_urb_write";
383 case VS_OPCODE_PULL_CONSTANT_LOAD
:
384 return "pull_constant_load";
385 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
386 return "pull_constant_load_gen7";
388 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
389 return "set_simd4x2_header_gen9";
391 case VS_OPCODE_GET_BUFFER_SIZE
:
392 return "vs_get_buffer_size";
394 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
395 return "unpack_flags_simd4x2";
397 case GS_OPCODE_URB_WRITE
:
398 return "gs_urb_write";
399 case GS_OPCODE_URB_WRITE_ALLOCATE
:
400 return "gs_urb_write_allocate";
401 case GS_OPCODE_THREAD_END
:
402 return "gs_thread_end";
403 case GS_OPCODE_SET_WRITE_OFFSET
:
404 return "set_write_offset";
405 case GS_OPCODE_SET_VERTEX_COUNT
:
406 return "set_vertex_count";
407 case GS_OPCODE_SET_DWORD_2
:
408 return "set_dword_2";
409 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
410 return "prepare_channel_masks";
411 case GS_OPCODE_SET_CHANNEL_MASKS
:
412 return "set_channel_masks";
413 case GS_OPCODE_GET_INSTANCE_ID
:
414 return "get_instance_id";
415 case GS_OPCODE_FF_SYNC
:
417 case GS_OPCODE_SET_PRIMITIVE_ID
:
418 return "set_primitive_id";
419 case GS_OPCODE_SVB_WRITE
:
420 return "gs_svb_write";
421 case GS_OPCODE_SVB_SET_DST_INDEX
:
422 return "gs_svb_set_dst_index";
423 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
424 return "gs_ff_sync_set_primitives";
425 case CS_OPCODE_CS_TERMINATE
:
426 return "cs_terminate";
427 case SHADER_OPCODE_BARRIER
:
429 case SHADER_OPCODE_MULH
:
431 case SHADER_OPCODE_MOV_INDIRECT
:
432 return "mov_indirect";
434 case VEC4_OPCODE_URB_READ
:
436 case TCS_OPCODE_GET_INSTANCE_ID
:
437 return "tcs_get_instance_id";
438 case TCS_OPCODE_URB_WRITE
:
439 return "tcs_urb_write";
440 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
441 return "tcs_set_input_urb_offsets";
442 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
443 return "tcs_set_output_urb_offsets";
444 case TCS_OPCODE_GET_PRIMITIVE_ID
:
445 return "tcs_get_primitive_id";
446 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
447 return "tcs_create_barrier_header";
448 case TCS_OPCODE_SRC0_010_IS_ZERO
:
449 return "tcs_src0<0,1,0>_is_zero";
450 case TCS_OPCODE_RELEASE_INPUT
:
451 return "tcs_release_input";
452 case TCS_OPCODE_THREAD_END
:
453 return "tcs_thread_end";
454 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
455 return "tes_create_input_read_header";
456 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
457 return "tes_add_indirect_urb_offset";
458 case TES_OPCODE_GET_PRIMITIVE_ID
:
459 return "tes_get_primitive_id";
462 unreachable("not reached");
466 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
473 } imm
, sat_imm
= { 0 };
475 const unsigned size
= type_sz(type
);
477 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
478 * irrelevant, so just check the size of the type and copy from/to an
479 * appropriately sized field.
487 case BRW_REGISTER_TYPE_UD
:
488 case BRW_REGISTER_TYPE_D
:
489 case BRW_REGISTER_TYPE_UW
:
490 case BRW_REGISTER_TYPE_W
:
491 case BRW_REGISTER_TYPE_UQ
:
492 case BRW_REGISTER_TYPE_Q
:
495 case BRW_REGISTER_TYPE_F
:
496 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
498 case BRW_REGISTER_TYPE_DF
:
499 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
501 case BRW_REGISTER_TYPE_UB
:
502 case BRW_REGISTER_TYPE_B
:
503 unreachable("no UB/B immediates");
504 case BRW_REGISTER_TYPE_V
:
505 case BRW_REGISTER_TYPE_UV
:
506 case BRW_REGISTER_TYPE_VF
:
507 unreachable("unimplemented: saturate vector immediate");
508 case BRW_REGISTER_TYPE_HF
:
509 unreachable("unimplemented: saturate HF immediate");
513 if (imm
.ud
!= sat_imm
.ud
) {
514 reg
->ud
= sat_imm
.ud
;
518 if (imm
.df
!= sat_imm
.df
) {
519 reg
->df
= sat_imm
.df
;
527 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
530 case BRW_REGISTER_TYPE_D
:
531 case BRW_REGISTER_TYPE_UD
:
534 case BRW_REGISTER_TYPE_W
:
535 case BRW_REGISTER_TYPE_UW
:
536 reg
->d
= -(int16_t)reg
->ud
;
538 case BRW_REGISTER_TYPE_F
:
541 case BRW_REGISTER_TYPE_VF
:
542 reg
->ud
^= 0x80808080;
544 case BRW_REGISTER_TYPE_DF
:
547 case BRW_REGISTER_TYPE_UB
:
548 case BRW_REGISTER_TYPE_B
:
549 unreachable("no UB/B immediates");
550 case BRW_REGISTER_TYPE_UV
:
551 case BRW_REGISTER_TYPE_V
:
552 assert(!"unimplemented: negate UV/V immediate");
553 case BRW_REGISTER_TYPE_UQ
:
554 case BRW_REGISTER_TYPE_Q
:
555 assert(!"unimplemented: negate UQ/Q immediate");
556 case BRW_REGISTER_TYPE_HF
:
557 assert(!"unimplemented: negate HF immediate");
564 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
567 case BRW_REGISTER_TYPE_D
:
568 reg
->d
= abs(reg
->d
);
570 case BRW_REGISTER_TYPE_W
:
571 reg
->d
= abs((int16_t)reg
->ud
);
573 case BRW_REGISTER_TYPE_F
:
574 reg
->f
= fabsf(reg
->f
);
576 case BRW_REGISTER_TYPE_DF
:
577 reg
->df
= fabs(reg
->df
);
579 case BRW_REGISTER_TYPE_VF
:
580 reg
->ud
&= ~0x80808080;
582 case BRW_REGISTER_TYPE_UB
:
583 case BRW_REGISTER_TYPE_B
:
584 unreachable("no UB/B immediates");
585 case BRW_REGISTER_TYPE_UQ
:
586 case BRW_REGISTER_TYPE_UD
:
587 case BRW_REGISTER_TYPE_UW
:
588 case BRW_REGISTER_TYPE_UV
:
589 /* Presumably the absolute value modifier on an unsigned source is a
590 * nop, but it would be nice to confirm.
592 assert(!"unimplemented: abs unsigned immediate");
593 case BRW_REGISTER_TYPE_V
:
594 assert(!"unimplemented: abs V immediate");
595 case BRW_REGISTER_TYPE_Q
:
596 assert(!"unimplemented: abs Q immediate");
597 case BRW_REGISTER_TYPE_HF
:
598 assert(!"unimplemented: abs HF immediate");
605 tesslevel_outer_components(GLenum tes_primitive_mode
)
607 switch (tes_primitive_mode
) {
615 unreachable("Bogus tessellation domain");
621 tesslevel_inner_components(GLenum tes_primitive_mode
)
623 switch (tes_primitive_mode
) {
631 unreachable("Bogus tessellation domain");
637 * Given a normal .xyzw writemask, convert it to a writemask for a vector
638 * that's stored backwards, i.e. .wzyx.
641 writemask_for_backwards_vector(unsigned mask
)
643 unsigned new_mask
= 0;
645 for (int i
= 0; i
< 4; i
++)
646 new_mask
|= ((mask
>> i
) & 1) << (3 - i
);
651 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
654 const nir_shader
*shader
,
655 struct brw_stage_prog_data
*stage_prog_data
)
656 : compiler(compiler
),
658 devinfo(compiler
->devinfo
),
660 stage_prog_data(stage_prog_data
),
665 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
666 stage_name
= _mesa_shader_stage_to_string(stage
);
667 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
668 is_passthrough_shader
=
669 nir
->info
.name
&& strcmp(nir
->info
.name
, "passthrough") == 0;
673 backend_reg::equals(const backend_reg
&r
) const
675 return brw_regs_equal(this, &r
) && reg_offset
== r
.reg_offset
;
679 backend_reg::is_zero() const
685 case BRW_REGISTER_TYPE_F
:
687 case BRW_REGISTER_TYPE_DF
:
689 case BRW_REGISTER_TYPE_D
:
690 case BRW_REGISTER_TYPE_UD
:
698 backend_reg::is_one() const
704 case BRW_REGISTER_TYPE_F
:
706 case BRW_REGISTER_TYPE_DF
:
708 case BRW_REGISTER_TYPE_D
:
709 case BRW_REGISTER_TYPE_UD
:
717 backend_reg::is_negative_one() const
723 case BRW_REGISTER_TYPE_F
:
725 case BRW_REGISTER_TYPE_DF
:
727 case BRW_REGISTER_TYPE_D
:
735 backend_reg::is_null() const
737 return file
== ARF
&& nr
== BRW_ARF_NULL
;
742 backend_reg::is_accumulator() const
744 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
748 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
750 return (file
== r
.file
&&
752 reg_offset
>= r
.reg_offset
&&
753 reg_offset
< r
.reg_offset
+ n
);
757 backend_instruction::is_commutative() const
765 case SHADER_OPCODE_MULH
:
768 /* MIN and MAX are commutative. */
769 if (conditional_mod
== BRW_CONDITIONAL_GE
||
770 conditional_mod
== BRW_CONDITIONAL_L
) {
780 backend_instruction::is_3src(const struct brw_device_info
*devinfo
) const
782 return ::is_3src(devinfo
, opcode
);
786 backend_instruction::is_tex() const
788 return (opcode
== SHADER_OPCODE_TEX
||
789 opcode
== FS_OPCODE_TXB
||
790 opcode
== SHADER_OPCODE_TXD
||
791 opcode
== SHADER_OPCODE_TXF
||
792 opcode
== SHADER_OPCODE_TXF_LZ
||
793 opcode
== SHADER_OPCODE_TXF_CMS
||
794 opcode
== SHADER_OPCODE_TXF_CMS_W
||
795 opcode
== SHADER_OPCODE_TXF_UMS
||
796 opcode
== SHADER_OPCODE_TXF_MCS
||
797 opcode
== SHADER_OPCODE_TXL
||
798 opcode
== SHADER_OPCODE_TXL_LZ
||
799 opcode
== SHADER_OPCODE_TXS
||
800 opcode
== SHADER_OPCODE_LOD
||
801 opcode
== SHADER_OPCODE_TG4
||
802 opcode
== SHADER_OPCODE_TG4_OFFSET
||
803 opcode
== SHADER_OPCODE_SAMPLEINFO
);
807 backend_instruction::is_math() const
809 return (opcode
== SHADER_OPCODE_RCP
||
810 opcode
== SHADER_OPCODE_RSQ
||
811 opcode
== SHADER_OPCODE_SQRT
||
812 opcode
== SHADER_OPCODE_EXP2
||
813 opcode
== SHADER_OPCODE_LOG2
||
814 opcode
== SHADER_OPCODE_SIN
||
815 opcode
== SHADER_OPCODE_COS
||
816 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
817 opcode
== SHADER_OPCODE_INT_REMAINDER
||
818 opcode
== SHADER_OPCODE_POW
);
822 backend_instruction::is_control_flow() const
826 case BRW_OPCODE_WHILE
:
828 case BRW_OPCODE_ELSE
:
829 case BRW_OPCODE_ENDIF
:
830 case BRW_OPCODE_BREAK
:
831 case BRW_OPCODE_CONTINUE
:
839 backend_instruction::can_do_source_mods() const
842 case BRW_OPCODE_ADDC
:
844 case BRW_OPCODE_BFI1
:
845 case BRW_OPCODE_BFI2
:
846 case BRW_OPCODE_BFREV
:
847 case BRW_OPCODE_CBIT
:
850 case BRW_OPCODE_SUBB
:
858 backend_instruction::can_do_saturate() const
868 case BRW_OPCODE_F16TO32
:
869 case BRW_OPCODE_F32TO16
:
870 case BRW_OPCODE_LINE
:
874 case BRW_OPCODE_MATH
:
877 case SHADER_OPCODE_MULH
:
879 case BRW_OPCODE_RNDD
:
880 case BRW_OPCODE_RNDE
:
881 case BRW_OPCODE_RNDU
:
882 case BRW_OPCODE_RNDZ
:
886 case FS_OPCODE_LINTERP
:
887 case SHADER_OPCODE_COS
:
888 case SHADER_OPCODE_EXP2
:
889 case SHADER_OPCODE_LOG2
:
890 case SHADER_OPCODE_POW
:
891 case SHADER_OPCODE_RCP
:
892 case SHADER_OPCODE_RSQ
:
893 case SHADER_OPCODE_SIN
:
894 case SHADER_OPCODE_SQRT
:
902 backend_instruction::can_do_cmod() const
906 case BRW_OPCODE_ADDC
:
911 case BRW_OPCODE_CMPN
:
916 case BRW_OPCODE_F16TO32
:
917 case BRW_OPCODE_F32TO16
:
919 case BRW_OPCODE_LINE
:
923 case BRW_OPCODE_MACH
:
930 case BRW_OPCODE_RNDD
:
931 case BRW_OPCODE_RNDE
:
932 case BRW_OPCODE_RNDU
:
933 case BRW_OPCODE_RNDZ
:
934 case BRW_OPCODE_SAD2
:
935 case BRW_OPCODE_SADA2
:
938 case BRW_OPCODE_SUBB
:
940 case FS_OPCODE_CINTERP
:
941 case FS_OPCODE_LINTERP
:
949 backend_instruction::reads_accumulator_implicitly() const
953 case BRW_OPCODE_MACH
:
954 case BRW_OPCODE_SADA2
:
962 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
964 return writes_accumulator
||
966 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
967 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
968 opcode
!= FS_OPCODE_CINTERP
)));
972 backend_instruction::has_side_effects() const
975 case SHADER_OPCODE_UNTYPED_ATOMIC
:
976 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
977 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
978 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
979 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
980 case SHADER_OPCODE_TYPED_ATOMIC
:
981 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
982 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
983 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
984 case SHADER_OPCODE_MEMORY_FENCE
:
985 case SHADER_OPCODE_URB_WRITE_SIMD8
:
986 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
987 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
988 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
989 case FS_OPCODE_FB_WRITE
:
990 case FS_OPCODE_FB_WRITE_LOGICAL
:
991 case SHADER_OPCODE_BARRIER
:
992 case TCS_OPCODE_URB_WRITE
:
993 case TCS_OPCODE_RELEASE_INPUT
:
1001 backend_instruction::is_volatile() const
1004 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1005 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1006 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1007 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1008 case SHADER_OPCODE_URB_READ_SIMD8
:
1009 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1010 case VEC4_OPCODE_URB_READ
:
1019 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1022 foreach_inst_in_block (backend_instruction
, i
, block
) {
1032 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1034 for (bblock_t
*block_iter
= start_block
->next();
1036 block_iter
= block_iter
->next()) {
1037 block_iter
->start_ip
+= ip_adjustment
;
1038 block_iter
->end_ip
+= ip_adjustment
;
1043 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1045 assert(this != inst
);
1047 if (!this->is_head_sentinel())
1048 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1052 adjust_later_block_ips(block
, 1);
1054 exec_node::insert_after(inst
);
1058 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1060 assert(this != inst
);
1062 if (!this->is_tail_sentinel())
1063 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1067 adjust_later_block_ips(block
, 1);
1069 exec_node::insert_before(inst
);
1073 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1075 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1077 unsigned num_inst
= list
->length();
1079 block
->end_ip
+= num_inst
;
1081 adjust_later_block_ips(block
, num_inst
);
1083 exec_node::insert_before(list
);
1087 backend_instruction::remove(bblock_t
*block
)
1089 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1091 adjust_later_block_ips(block
, -1);
1093 if (block
->start_ip
== block
->end_ip
) {
1094 block
->cfg
->remove_block(block
);
1099 exec_node::remove();
1103 backend_shader::dump_instructions()
1105 dump_instructions(NULL
);
1109 backend_shader::dump_instructions(const char *name
)
1111 FILE *file
= stderr
;
1112 if (name
&& geteuid() != 0) {
1113 file
= fopen(name
, "w");
1120 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1121 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1122 fprintf(file
, "%4d: ", ip
++);
1123 dump_instruction(inst
, file
);
1127 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1128 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1129 fprintf(file
, "%4d: ", ip
++);
1130 dump_instruction(inst
, file
);
1134 if (file
!= stderr
) {
1140 backend_shader::calculate_cfg()
1144 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1148 * Sets up the starting offsets for the groups of binding table entries
1149 * commong to all pipeline stages.
1151 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1152 * unused but also make sure that addition of small offsets to them will
1153 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1156 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1157 const struct brw_device_info
*devinfo
,
1158 const struct gl_shader_program
*shader_prog
,
1159 const struct gl_program
*prog
,
1160 struct brw_stage_prog_data
*stage_prog_data
,
1161 uint32_t next_binding_table_offset
)
1163 const struct gl_linked_shader
*shader
= NULL
;
1164 int num_textures
= util_last_bit(prog
->SamplersUsed
);
1167 shader
= shader_prog
->_LinkedShaders
[stage
];
1169 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1170 next_binding_table_offset
+= num_textures
;
1173 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1174 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1175 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1177 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1178 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1179 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1181 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1182 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1185 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1186 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1187 next_binding_table_offset
++;
1189 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1192 if (prog
->UsesGather
) {
1193 if (devinfo
->gen
>= 8) {
1194 stage_prog_data
->binding_table
.gather_texture_start
=
1195 stage_prog_data
->binding_table
.texture_start
;
1197 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1198 next_binding_table_offset
+= num_textures
;
1201 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1204 if (shader
&& shader
->NumAtomicBuffers
) {
1205 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1206 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1208 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1211 if (shader
&& shader
->NumImages
) {
1212 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1213 next_binding_table_offset
+= shader
->NumImages
;
1215 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1218 /* This may or may not be used depending on how the compile goes. */
1219 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1220 next_binding_table_offset
++;
1222 /* Plane 0 is just the regular texture section */
1223 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
1225 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
1226 next_binding_table_offset
+= num_textures
;
1228 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
1229 next_binding_table_offset
+= num_textures
;
1231 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1233 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1234 return next_binding_table_offset
;
1238 setup_vec4_uniform_value(const gl_constant_value
**params
,
1239 const gl_constant_value
*values
,
1242 static const gl_constant_value zero
= { 0 };
1244 for (unsigned i
= 0; i
< n
; ++i
)
1245 params
[i
] = &values
[i
];
1247 for (unsigned i
= n
; i
< 4; ++i
)
1252 brw_setup_image_uniform_values(gl_shader_stage stage
,
1253 struct brw_stage_prog_data
*stage_prog_data
,
1254 unsigned param_start_index
,
1255 const gl_uniform_storage
*storage
)
1257 const gl_constant_value
**param
=
1258 &stage_prog_data
->param
[param_start_index
];
1260 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1261 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1262 const brw_image_param
*image_param
=
1263 &stage_prog_data
->image_param
[image_idx
];
1265 /* Upload the brw_image_param structure. The order is expected to match
1266 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1268 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1269 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1270 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1271 (const gl_constant_value
*)image_param
->offset
, 2);
1272 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1273 (const gl_constant_value
*)image_param
->size
, 3);
1274 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1275 (const gl_constant_value
*)image_param
->stride
, 4);
1276 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1277 (const gl_constant_value
*)image_param
->tiling
, 3);
1278 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1279 (const gl_constant_value
*)image_param
->swizzling
, 2);
1280 param
+= BRW_IMAGE_PARAM_SIZE
;
1282 brw_mark_surface_used(
1284 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1289 * Decide which set of clip planes should be used when clipping via
1290 * gl_Position or gl_ClipVertex.
1292 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1294 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1295 /* There is currently a GLSL vertex shader, so clip according to GLSL
1296 * rules, which means compare gl_ClipVertex (or gl_Position, if
1297 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1298 * that were stored in EyeUserPlane at the time the clip planes were
1301 return ctx
->Transform
.EyeUserPlane
;
1303 /* Either we are using fixed function or an ARB vertex program. In
1304 * either case the clip planes are going to be compared against
1305 * gl_Position (which is in clip coordinates) so we have to clip using
1306 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1309 return ctx
->Transform
._ClipUserPlane
;
1313 extern "C" const unsigned *
1314 brw_compile_tes(const struct brw_compiler
*compiler
,
1317 const struct brw_tes_prog_key
*key
,
1318 struct brw_tes_prog_data
*prog_data
,
1319 const nir_shader
*src_shader
,
1320 struct gl_shader_program
*shader_prog
,
1321 int shader_time_index
,
1322 unsigned *final_assembly_size
,
1325 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
1326 struct gl_linked_shader
*shader
=
1327 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
1328 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1330 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1331 nir
->info
.inputs_read
= key
->inputs_read
;
1332 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1334 struct brw_vue_map input_vue_map
;
1335 brw_compute_tess_vue_map(&input_vue_map
,
1336 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
1337 nir
->info
.patch_inputs_read
);
1339 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
1340 brw_nir_lower_tes_inputs(nir
, &input_vue_map
);
1341 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1342 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
1344 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1345 nir
->info
.outputs_written
,
1346 nir
->info
.separate_shader
);
1348 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1350 assert(output_size_bytes
>= 1);
1351 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1353 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1357 /* URB entry sizes are stored as a multiple of 64 bytes. */
1358 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1360 bool need_patch_header
= nir
->info
.system_values_read
&
1361 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER
) |
1362 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER
));
1364 /* The TES will pull most inputs using URB read messages.
1366 * However, we push the patch header for TessLevel factors when required,
1367 * as it's a tiny amount of extra data.
1369 prog_data
->base
.urb_read_length
= need_patch_header
? 1 : 0;
1371 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1372 fprintf(stderr
, "TES Input ");
1373 brw_print_vue_map(stderr
, &input_vue_map
);
1374 fprintf(stderr
, "TES Output ");
1375 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1379 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1380 &prog_data
->base
.base
, shader
->Program
, nir
, 8,
1381 shader_time_index
, &input_vue_map
);
1384 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1388 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1389 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1391 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1392 &prog_data
->base
.base
, v
.promoted_constants
, false,
1393 MESA_SHADER_TESS_EVAL
);
1394 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1395 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1396 "%s tessellation evaluation shader %s",
1397 nir
->info
.label
? nir
->info
.label
1402 g
.generate_code(v
.cfg
, 8);
1404 return g
.get_assembly(final_assembly_size
);
1406 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1407 nir
, mem_ctx
, shader_time_index
);
1410 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1414 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1415 v
.dump_instructions();
1417 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1418 &prog_data
->base
, v
.cfg
,
1419 final_assembly_size
);