src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 struct gl_shader *
  36 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  37 {
  38    struct brw_shader *shader;
  39
  40    shader = rzalloc(NULL, struct brw_shader);
  41    if (shader) {
  42       shader->base.Type = type;
  43       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  44       shader->base.Name = name;
  45       _mesa_init_shader(ctx, &shader->base);
  46    }
  47
  48    return &shader->base;
  49 }
  50
  51 /**
  52  * Performs a compile of the shader stages even when we don't know
  53  * what non-orthogonal state will be set, in the hope that it reflects
  54  * the eventual NOS used, and thus allows us to produce link failures.
  55  */
  56 static bool
  57 brw_shader_precompile(struct gl_context *ctx,
  58                       struct gl_shader_program *sh_prog)
  59 {
  60    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  61    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  62    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  63
  64    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  65       return false;
  66
  67    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  68       return false;
  69
  70    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  71       return false;
  72
  73    return true;
  74 }
  75
  76 static inline bool
  77 is_scalar_shader_stage(struct brw_context *brw, int stage)
  78 {
  79    switch (stage) {
  80    case MESA_SHADER_FRAGMENT:
  81       return true;
  82    case MESA_SHADER_VERTEX:
  83       return brw->scalar_vs;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 static void
  90 brw_lower_packing_builtins(struct brw_context *brw,
  91                            gl_shader_stage shader_type,
  92                            exec_list *ir)
  93 {
  94    int ops = LOWER_PACK_SNORM_2x16
  95            | LOWER_UNPACK_SNORM_2x16
  96            | LOWER_PACK_UNORM_2x16
  97            | LOWER_UNPACK_UNORM_2x16;
  98
  99    if (is_scalar_shader_stage(brw, shader_type)) {
 100       ops |= LOWER_UNPACK_UNORM_4x8
 101            | LOWER_UNPACK_SNORM_4x8
 102            | LOWER_PACK_UNORM_4x8
 103            | LOWER_PACK_SNORM_4x8;
 104    }
 105
 106    if (brw->gen >= 7) {
 107       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 108        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 109        * lowering is needed. For SOA code, the Half2x16 ops must be
 110        * scalarized.
 111        */
 112       if (is_scalar_shader_stage(brw, shader_type)) {
 113          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 114              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 115       }
 116    } else {
 117       ops |= LOWER_PACK_HALF_2x16
 118           |  LOWER_UNPACK_HALF_2x16;
 119    }
 120
 121    lower_packing_builtins(ir, ops);
 122 }
 123
 124 static void
 125 process_glsl_ir(struct brw_context *brw,
 126                 struct gl_shader_program *shader_prog,
 127                 struct gl_shader *shader)
 128 {
 129    struct gl_context *ctx = &brw->ctx;
 130    const struct gl_shader_compiler_options *options =
 131       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 132
 133    /* Temporary memory context for any new IR. */
 134    void *mem_ctx = ralloc_context(NULL);
 135
 136    ralloc_adopt(mem_ctx, shader->ir);
 137
 138    /* lower_packing_builtins() inserts arithmetic instructions, so it
 139     * must precede lower_instructions().
 140     */
 141    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 142    do_mat_op_to_vec(shader->ir);
 143    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 144    lower_instructions(shader->ir,
 145                       MOD_TO_FLOOR |
 146                       DIV_TO_MUL_RCP |
 147                       SUB_TO_ADD_NEG |
 148                       EXP_TO_EXP2 |
 149                       LOG_TO_LOG2 |
 150                       bitfield_insert |
 151                       LDEXP_TO_ARITH);
 152
 153    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 154     * if-statements need to be flattened.
 155     */
 156    if (brw->gen < 6)
 157       lower_if_to_cond_assign(shader->ir, 16);
 158
 159    do_lower_texture_projection(shader->ir);
 160    brw_lower_texture_gradients(brw, shader->ir);
 161    do_vec_index_to_cond_assign(shader->ir);
 162    lower_vector_insert(shader->ir, true);
 163    if (options->NirOptions == NULL)
 164       brw_do_cubemap_normalize(shader->ir);
 165    lower_offset_arrays(shader->ir);
 166    brw_do_lower_unnormalized_offset(shader->ir);
 167    lower_noise(shader->ir);
 168    lower_quadop_vector(shader->ir, false);
 169
 170    bool lowered_variable_indexing =
 171       lower_variable_index_to_cond_assign(shader->ir,
 172                                           options->EmitNoIndirectInput,
 173                                           options->EmitNoIndirectOutput,
 174                                           options->EmitNoIndirectTemp,
 175                                           options->EmitNoIndirectUniform);
 176
 177    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 178       perf_debug("Unsupported form of variable indexing in FS; falling "
 179                  "back to very inefficient code generation\n");
 180    }
 181
 182    lower_ubo_reference(shader, shader->ir);
 183
 184    bool progress;
 185    do {
 186       progress = false;
 187
 188       if (is_scalar_shader_stage(brw, shader->Stage)) {
 189          brw_do_channel_expressions(shader->ir);
 190          brw_do_vector_splitting(shader->ir);
 191       }
 192
 193       progress = do_lower_jumps(shader->ir, true, true,
 194                                 true, /* main return */
 195                                 false, /* continue */
 196                                 false /* loops */
 197                                 ) || progress;
 198
 199       progress = do_common_optimization(shader->ir, true, true,
 200                                         options, ctx->Const.NativeIntegers) || progress;
 201    } while (progress);
 202
 203    if (options->NirOptions != NULL)
 204       lower_output_reads(shader->ir);
 205
 206    validate_ir_tree(shader->ir);
 207
 208    /* Now that we've finished altering the linked IR, reparent any live IR back
 209     * to the permanent memory context, and free the temporary one (discarding any
 210     * junk we optimized away).
 211     */
 212    reparent_ir(shader->ir, shader->ir);
 213    ralloc_free(mem_ctx);
 214
 215    if (ctx->_Shader->Flags & GLSL_DUMP) {
 216       fprintf(stderr, "\n");
 217       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 218               _mesa_shader_stage_to_string(shader->Stage),
 219               shader_prog->Name);
 220       _mesa_print_ir(stderr, shader->ir, NULL);
 221       fprintf(stderr, "\n");
 222    }
 223 }
 224
 225 GLboolean
 226 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 227 {
 228    struct brw_context *brw = brw_context(ctx);
 229    unsigned int stage;
 230
 231    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 232       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 233       const struct gl_shader_compiler_options *options =
 234          &ctx->Const.ShaderCompilerOptions[stage];
 235
 236       if (!shader)
 237          continue;
 238
 239       struct gl_program *prog =
 240          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 241                                 shader->Name);
 242       if (!prog)
 243         return false;
 244       prog->Parameters = _mesa_new_parameter_list();
 245
 246       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 247
 248       process_glsl_ir(brw, shProg, shader);
 249
 250       /* Make a pass over the IR to add state references for any built-in
 251        * uniforms that are used.  This has to be done now (during linking).
 252        * Code generation doesn't happen until the first time this shader is
 253        * used for rendering.  Waiting until then to generate the parameters is
 254        * too late.  At that point, the values for the built-in uniforms won't
 255        * get sent to the shader.
 256        */
 257       foreach_in_list(ir_instruction, node, shader->ir) {
 258          ir_variable *var = node->as_variable();
 259
 260          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 261              || (strncmp(var->name, "gl_", 3) != 0))
 262             continue;
 263
 264          const ir_state_slot *const slots = var->get_state_slots();
 265          assert(slots != NULL);
 266
 267          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 268             _mesa_add_state_reference(prog->Parameters,
 269                                       (gl_state_index *) slots[i].tokens);
 270          }
 271       }
 272
 273       do_set_program_inouts(shader->ir, prog, shader->Stage);
 274
 275       prog->SamplersUsed = shader->active_samplers;
 276       prog->ShadowSamplers = shader->shadow_samplers;
 277       _mesa_update_shader_textures_used(shProg, prog);
 278
 279       _mesa_reference_program(ctx, &shader->Program, prog);
 280
 281       brw_add_texrect_params(prog);
 282
 283       if (options->NirOptions)
 284          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 285
 286       _mesa_reference_program(ctx, &prog, NULL);
 287    }
 288
 289    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 290       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 291          const struct gl_shader *sh = shProg->Shaders[i];
 292          if (!sh)
 293             continue;
 294
 295          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 296                  _mesa_shader_stage_to_string(sh->Stage),
 297                  i, shProg->Name);
 298          fprintf(stderr, "%s", sh->Source);
 299          fprintf(stderr, "\n");
 300       }
 301    }
 302
 303    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 304       return false;
 305
 306    return true;
 307 }
 308
 309
 310 enum brw_reg_type
 311 brw_type_for_base_type(const struct glsl_type *type)
 312 {
 313    switch (type->base_type) {
 314    case GLSL_TYPE_FLOAT:
 315       return BRW_REGISTER_TYPE_F;
 316    case GLSL_TYPE_INT:
 317    case GLSL_TYPE_BOOL:
 318       return BRW_REGISTER_TYPE_D;
 319    case GLSL_TYPE_UINT:
 320       return BRW_REGISTER_TYPE_UD;
 321    case GLSL_TYPE_ARRAY:
 322       return brw_type_for_base_type(type->fields.array);
 323    case GLSL_TYPE_STRUCT:
 324    case GLSL_TYPE_SAMPLER:
 325    case GLSL_TYPE_ATOMIC_UINT:
 326       /* These should be overridden with the type of the member when
 327        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 328        * way to trip up if we don't.
 329        */
 330       return BRW_REGISTER_TYPE_UD;
 331    case GLSL_TYPE_IMAGE:
 332       return BRW_REGISTER_TYPE_UD;
 333    case GLSL_TYPE_VOID:
 334    case GLSL_TYPE_ERROR:
 335    case GLSL_TYPE_INTERFACE:
 336    case GLSL_TYPE_DOUBLE:
 337       unreachable("not reached");
 338    }
 339
 340    return BRW_REGISTER_TYPE_F;
 341 }
 342
 343 enum brw_conditional_mod
 344 brw_conditional_for_comparison(unsigned int op)
 345 {
 346    switch (op) {
 347    case ir_binop_less:
 348       return BRW_CONDITIONAL_L;
 349    case ir_binop_greater:
 350       return BRW_CONDITIONAL_G;
 351    case ir_binop_lequal:
 352       return BRW_CONDITIONAL_LE;
 353    case ir_binop_gequal:
 354       return BRW_CONDITIONAL_GE;
 355    case ir_binop_equal:
 356    case ir_binop_all_equal: /* same as equal for scalars */
 357       return BRW_CONDITIONAL_Z;
 358    case ir_binop_nequal:
 359    case ir_binop_any_nequal: /* same as nequal for scalars */
 360       return BRW_CONDITIONAL_NZ;
 361    default:
 362       unreachable("not reached: bad operation for comparison");
 363    }
 364 }
 365
 366 uint32_t
 367 brw_math_function(enum opcode op)
 368 {
 369    switch (op) {
 370    case SHADER_OPCODE_RCP:
 371       return BRW_MATH_FUNCTION_INV;
 372    case SHADER_OPCODE_RSQ:
 373       return BRW_MATH_FUNCTION_RSQ;
 374    case SHADER_OPCODE_SQRT:
 375       return BRW_MATH_FUNCTION_SQRT;
 376    case SHADER_OPCODE_EXP2:
 377       return BRW_MATH_FUNCTION_EXP;
 378    case SHADER_OPCODE_LOG2:
 379       return BRW_MATH_FUNCTION_LOG;
 380    case SHADER_OPCODE_POW:
 381       return BRW_MATH_FUNCTION_POW;
 382    case SHADER_OPCODE_SIN:
 383       return BRW_MATH_FUNCTION_SIN;
 384    case SHADER_OPCODE_COS:
 385       return BRW_MATH_FUNCTION_COS;
 386    case SHADER_OPCODE_INT_QUOTIENT:
 387       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 388    case SHADER_OPCODE_INT_REMAINDER:
 389       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 390    default:
 391       unreachable("not reached: unknown math function");
 392    }
 393 }
 394
 395 uint32_t
 396 brw_texture_offset(struct gl_context *ctx, int *offsets,
 397                    unsigned num_components)
 398 {
 399    /* If the driver does not support GL_ARB_gpu_shader5, the offset
 400     * must be constant.
 401     */
 402    assert(offsets != NULL || ctx->Extensions.ARB_gpu_shader5);
 403
 404    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 405
 406    /* Combine all three offsets into a single unsigned dword:
 407     *
 408     *    bits 11:8 - U Offset (X component)
 409     *    bits  7:4 - V Offset (Y component)
 410     *    bits  3:0 - R Offset (Z component)
 411     */
 412    unsigned offset_bits = 0;
 413    for (unsigned i = 0; i < num_components; i++) {
 414       const unsigned shift = 4 * (2 - i);
 415       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 416    }
 417    return offset_bits;
 418 }
 419
 420 const char *
 421 brw_instruction_name(enum opcode op)
 422 {
 423    switch (op) {
 424    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 425       assert(opcode_descs[op].name);
 426       return opcode_descs[op].name;
 427    case FS_OPCODE_FB_WRITE:
 428       return "fb_write";
 429    case FS_OPCODE_BLORP_FB_WRITE:
 430       return "blorp_fb_write";
 431    case FS_OPCODE_REP_FB_WRITE:
 432       return "rep_fb_write";
 433
 434    case SHADER_OPCODE_RCP:
 435       return "rcp";
 436    case SHADER_OPCODE_RSQ:
 437       return "rsq";
 438    case SHADER_OPCODE_SQRT:
 439       return "sqrt";
 440    case SHADER_OPCODE_EXP2:
 441       return "exp2";
 442    case SHADER_OPCODE_LOG2:
 443       return "log2";
 444    case SHADER_OPCODE_POW:
 445       return "pow";
 446    case SHADER_OPCODE_INT_QUOTIENT:
 447       return "int_quot";
 448    case SHADER_OPCODE_INT_REMAINDER:
 449       return "int_rem";
 450    case SHADER_OPCODE_SIN:
 451       return "sin";
 452    case SHADER_OPCODE_COS:
 453       return "cos";
 454
 455    case SHADER_OPCODE_TEX:
 456       return "tex";
 457    case SHADER_OPCODE_TXD:
 458       return "txd";
 459    case SHADER_OPCODE_TXF:
 460       return "txf";
 461    case SHADER_OPCODE_TXL:
 462       return "txl";
 463    case SHADER_OPCODE_TXS:
 464       return "txs";
 465    case FS_OPCODE_TXB:
 466       return "txb";
 467    case SHADER_OPCODE_TXF_CMS:
 468       return "txf_cms";
 469    case SHADER_OPCODE_TXF_UMS:
 470       return "txf_ums";
 471    case SHADER_OPCODE_TXF_MCS:
 472       return "txf_mcs";
 473    case SHADER_OPCODE_LOD:
 474       return "lod";
 475    case SHADER_OPCODE_TG4:
 476       return "tg4";
 477    case SHADER_OPCODE_TG4_OFFSET:
 478       return "tg4_offset";
 479    case SHADER_OPCODE_SHADER_TIME_ADD:
 480       return "shader_time_add";
 481
 482    case SHADER_OPCODE_UNTYPED_ATOMIC:
 483       return "untyped_atomic";
 484    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 485       return "untyped_surface_read";
 486
 487    case SHADER_OPCODE_LOAD_PAYLOAD:
 488       return "load_payload";
 489
 490    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 491       return "gen4_scratch_read";
 492    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 493       return "gen4_scratch_write";
 494    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 495       return "gen7_scratch_read";
 496    case SHADER_OPCODE_URB_WRITE_SIMD8:
 497       return "gen8_urb_write_simd8";
 498
 499    case VEC4_OPCODE_MOV_BYTES:
 500       return "mov_bytes";
 501    case VEC4_OPCODE_PACK_BYTES:
 502       return "pack_bytes";
 503    case VEC4_OPCODE_UNPACK_UNIFORM:
 504       return "unpack_uniform";
 505
 506    case FS_OPCODE_DDX_COARSE:
 507       return "ddx_coarse";
 508    case FS_OPCODE_DDX_FINE:
 509       return "ddx_fine";
 510    case FS_OPCODE_DDY_COARSE:
 511       return "ddy_coarse";
 512    case FS_OPCODE_DDY_FINE:
 513       return "ddy_fine";
 514
 515    case FS_OPCODE_CINTERP:
 516       return "cinterp";
 517    case FS_OPCODE_LINTERP:
 518       return "linterp";
 519
 520    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 521       return "uniform_pull_const";
 522    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 523       return "uniform_pull_const_gen7";
 524    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 525       return "varying_pull_const";
 526    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 527       return "varying_pull_const_gen7";
 528
 529    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 530       return "mov_dispatch_to_flags";
 531    case FS_OPCODE_DISCARD_JUMP:
 532       return "discard_jump";
 533
 534    case FS_OPCODE_SET_OMASK:
 535       return "set_omask";
 536    case FS_OPCODE_SET_SAMPLE_ID:
 537       return "set_sample_id";
 538    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 539       return "set_simd4x2_offset";
 540
 541    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 542       return "pack_half_2x16_split";
 543    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 544       return "unpack_half_2x16_split_x";
 545    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 546       return "unpack_half_2x16_split_y";
 547
 548    case FS_OPCODE_PLACEHOLDER_HALT:
 549       return "placeholder_halt";
 550
 551    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 552       return "interp_centroid";
 553    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 554       return "interp_sample";
 555    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 556       return "interp_shared_offset";
 557    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 558       return "interp_per_slot_offset";
 559
 560    case VS_OPCODE_URB_WRITE:
 561       return "vs_urb_write";
 562    case VS_OPCODE_PULL_CONSTANT_LOAD:
 563       return "pull_constant_load";
 564    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 565       return "pull_constant_load_gen7";
 566
 567    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 568       return "set_simd4x2_header_gen9";
 569
 570    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 571       return "unpack_flags_simd4x2";
 572
 573    case GS_OPCODE_URB_WRITE:
 574       return "gs_urb_write";
 575    case GS_OPCODE_URB_WRITE_ALLOCATE:
 576       return "gs_urb_write_allocate";
 577    case GS_OPCODE_THREAD_END:
 578       return "gs_thread_end";
 579    case GS_OPCODE_SET_WRITE_OFFSET:
 580       return "set_write_offset";
 581    case GS_OPCODE_SET_VERTEX_COUNT:
 582       return "set_vertex_count";
 583    case GS_OPCODE_SET_DWORD_2:
 584       return "set_dword_2";
 585    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 586       return "prepare_channel_masks";
 587    case GS_OPCODE_SET_CHANNEL_MASKS:
 588       return "set_channel_masks";
 589    case GS_OPCODE_GET_INSTANCE_ID:
 590       return "get_instance_id";
 591    case GS_OPCODE_FF_SYNC:
 592       return "ff_sync";
 593    case GS_OPCODE_SET_PRIMITIVE_ID:
 594       return "set_primitive_id";
 595    case GS_OPCODE_SVB_WRITE:
 596       return "gs_svb_write";
 597    case GS_OPCODE_SVB_SET_DST_INDEX:
 598       return "gs_svb_set_dst_index";
 599    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 600       return "gs_ff_sync_set_primitives";
 601    }
 602
 603    unreachable("not reached");
 604 }
 605
 606 bool
 607 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 608 {
 609    union {
 610       unsigned ud;
 611       int d;
 612       float f;
 613    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 614
 615    switch (type) {
 616    case BRW_REGISTER_TYPE_UD:
 617    case BRW_REGISTER_TYPE_D:
 618    case BRW_REGISTER_TYPE_UQ:
 619    case BRW_REGISTER_TYPE_Q:
 620       /* Nothing to do. */
 621       return false;
 622    case BRW_REGISTER_TYPE_UW:
 623       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 624       break;
 625    case BRW_REGISTER_TYPE_W:
 626       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 627       break;
 628    case BRW_REGISTER_TYPE_F:
 629       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 630       break;
 631    case BRW_REGISTER_TYPE_UB:
 632    case BRW_REGISTER_TYPE_B:
 633       unreachable("no UB/B immediates");
 634    case BRW_REGISTER_TYPE_V:
 635    case BRW_REGISTER_TYPE_UV:
 636    case BRW_REGISTER_TYPE_VF:
 637       unreachable("unimplemented: saturate vector immediate");
 638    case BRW_REGISTER_TYPE_DF:
 639    case BRW_REGISTER_TYPE_HF:
 640       unreachable("unimplemented: saturate DF/HF immediate");
 641    }
 642
 643    if (imm.ud != sat_imm.ud) {
 644       reg->dw1.ud = sat_imm.ud;
 645       return true;
 646    }
 647    return false;
 648 }
 649
 650 bool
 651 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 652 {
 653    switch (type) {
 654    case BRW_REGISTER_TYPE_D:
 655    case BRW_REGISTER_TYPE_UD:
 656       reg->dw1.d = -reg->dw1.d;
 657       return true;
 658    case BRW_REGISTER_TYPE_W:
 659    case BRW_REGISTER_TYPE_UW:
 660       reg->dw1.d = -(int16_t)reg->dw1.ud;
 661       return true;
 662    case BRW_REGISTER_TYPE_F:
 663       reg->dw1.f = -reg->dw1.f;
 664       return true;
 665    case BRW_REGISTER_TYPE_VF:
 666       reg->dw1.ud ^= 0x80808080;
 667       return true;
 668    case BRW_REGISTER_TYPE_UB:
 669    case BRW_REGISTER_TYPE_B:
 670       unreachable("no UB/B immediates");
 671    case BRW_REGISTER_TYPE_UV:
 672    case BRW_REGISTER_TYPE_V:
 673       assert(!"unimplemented: negate UV/V immediate");
 674    case BRW_REGISTER_TYPE_UQ:
 675    case BRW_REGISTER_TYPE_Q:
 676       assert(!"unimplemented: negate UQ/Q immediate");
 677    case BRW_REGISTER_TYPE_DF:
 678    case BRW_REGISTER_TYPE_HF:
 679       assert(!"unimplemented: negate DF/HF immediate");
 680    }
 681
 682    return false;
 683 }
 684
 685 bool
 686 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 687 {
 688    switch (type) {
 689    case BRW_REGISTER_TYPE_D:
 690       reg->dw1.d = abs(reg->dw1.d);
 691       return true;
 692    case BRW_REGISTER_TYPE_W:
 693       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 694       return true;
 695    case BRW_REGISTER_TYPE_F:
 696       reg->dw1.f = fabsf(reg->dw1.f);
 697       return true;
 698    case BRW_REGISTER_TYPE_VF:
 699       reg->dw1.ud &= ~0x80808080;
 700       return true;
 701    case BRW_REGISTER_TYPE_UB:
 702    case BRW_REGISTER_TYPE_B:
 703       unreachable("no UB/B immediates");
 704    case BRW_REGISTER_TYPE_UQ:
 705    case BRW_REGISTER_TYPE_UD:
 706    case BRW_REGISTER_TYPE_UW:
 707    case BRW_REGISTER_TYPE_UV:
 708       /* Presumably the absolute value modifier on an unsigned source is a
 709        * nop, but it would be nice to confirm.
 710        */
 711       assert(!"unimplemented: abs unsigned immediate");
 712    case BRW_REGISTER_TYPE_V:
 713       assert(!"unimplemented: abs V immediate");
 714    case BRW_REGISTER_TYPE_Q:
 715       assert(!"unimplemented: abs Q immediate");
 716    case BRW_REGISTER_TYPE_DF:
 717    case BRW_REGISTER_TYPE_HF:
 718       assert(!"unimplemented: abs DF/HF immediate");
 719    }
 720
 721    return false;
 722 }
 723
 724 backend_visitor::backend_visitor(struct brw_context *brw,
 725                                  struct gl_shader_program *shader_prog,
 726                                  struct gl_program *prog,
 727                                  struct brw_stage_prog_data *stage_prog_data,
 728                                  gl_shader_stage stage)
 729    : brw(brw),
 730      ctx(&brw->ctx),
 731      shader(shader_prog ?
 732         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 733      shader_prog(shader_prog),
 734      prog(prog),
 735      stage_prog_data(stage_prog_data),
 736      cfg(NULL),
 737      stage(stage)
 738 {
 739    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 740    stage_name = _mesa_shader_stage_to_string(stage);
 741    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 742 }
 743
 744 bool
 745 backend_reg::is_zero() const
 746 {
 747    if (file != IMM)
 748       return false;
 749
 750    return fixed_hw_reg.dw1.d == 0;
 751 }
 752
 753 bool
 754 backend_reg::is_one() const
 755 {
 756    if (file != IMM)
 757       return false;
 758
 759    return type == BRW_REGISTER_TYPE_F
 760           ? fixed_hw_reg.dw1.f == 1.0
 761           : fixed_hw_reg.dw1.d == 1;
 762 }
 763
 764 bool
 765 backend_reg::is_negative_one() const
 766 {
 767    if (file != IMM)
 768       return false;
 769
 770    switch (type) {
 771    case BRW_REGISTER_TYPE_F:
 772       return fixed_hw_reg.dw1.f == -1.0;
 773    case BRW_REGISTER_TYPE_D:
 774       return fixed_hw_reg.dw1.d == -1;
 775    default:
 776       return false;
 777    }
 778 }
 779
 780 bool
 781 backend_reg::is_null() const
 782 {
 783    return file == HW_REG &&
 784           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 785           fixed_hw_reg.nr == BRW_ARF_NULL;
 786 }
 787
 788
 789 bool
 790 backend_reg::is_accumulator() const
 791 {
 792    return file == HW_REG &&
 793           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 794           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 795 }
 796
 797 bool
 798 backend_reg::in_range(const backend_reg &r, unsigned n) const
 799 {
 800    return (file == r.file &&
 801            reg == r.reg &&
 802            reg_offset >= r.reg_offset &&
 803            reg_offset < r.reg_offset + n);
 804 }
 805
 806 bool
 807 backend_instruction::is_commutative() const
 808 {
 809    switch (opcode) {
 810    case BRW_OPCODE_AND:
 811    case BRW_OPCODE_OR:
 812    case BRW_OPCODE_XOR:
 813    case BRW_OPCODE_ADD:
 814    case BRW_OPCODE_MUL:
 815       return true;
 816    case BRW_OPCODE_SEL:
 817       /* MIN and MAX are commutative. */
 818       if (conditional_mod == BRW_CONDITIONAL_GE ||
 819           conditional_mod == BRW_CONDITIONAL_L) {
 820          return true;
 821       }
 822       /* fallthrough */
 823    default:
 824       return false;
 825    }
 826 }
 827
 828 bool
 829 backend_instruction::is_3src() const
 830 {
 831    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 832 }
 833
 834 bool
 835 backend_instruction::is_tex() const
 836 {
 837    return (opcode == SHADER_OPCODE_TEX ||
 838            opcode == FS_OPCODE_TXB ||
 839            opcode == SHADER_OPCODE_TXD ||
 840            opcode == SHADER_OPCODE_TXF ||
 841            opcode == SHADER_OPCODE_TXF_CMS ||
 842            opcode == SHADER_OPCODE_TXF_UMS ||
 843            opcode == SHADER_OPCODE_TXF_MCS ||
 844            opcode == SHADER_OPCODE_TXL ||
 845            opcode == SHADER_OPCODE_TXS ||
 846            opcode == SHADER_OPCODE_LOD ||
 847            opcode == SHADER_OPCODE_TG4 ||
 848            opcode == SHADER_OPCODE_TG4_OFFSET);
 849 }
 850
 851 bool
 852 backend_instruction::is_math() const
 853 {
 854    return (opcode == SHADER_OPCODE_RCP ||
 855            opcode == SHADER_OPCODE_RSQ ||
 856            opcode == SHADER_OPCODE_SQRT ||
 857            opcode == SHADER_OPCODE_EXP2 ||
 858            opcode == SHADER_OPCODE_LOG2 ||
 859            opcode == SHADER_OPCODE_SIN ||
 860            opcode == SHADER_OPCODE_COS ||
 861            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 862            opcode == SHADER_OPCODE_INT_REMAINDER ||
 863            opcode == SHADER_OPCODE_POW);
 864 }
 865
 866 bool
 867 backend_instruction::is_control_flow() const
 868 {
 869    switch (opcode) {
 870    case BRW_OPCODE_DO:
 871    case BRW_OPCODE_WHILE:
 872    case BRW_OPCODE_IF:
 873    case BRW_OPCODE_ELSE:
 874    case BRW_OPCODE_ENDIF:
 875    case BRW_OPCODE_BREAK:
 876    case BRW_OPCODE_CONTINUE:
 877       return true;
 878    default:
 879       return false;
 880    }
 881 }
 882
 883 bool
 884 backend_instruction::can_do_source_mods() const
 885 {
 886    switch (opcode) {
 887    case BRW_OPCODE_ADDC:
 888    case BRW_OPCODE_BFE:
 889    case BRW_OPCODE_BFI1:
 890    case BRW_OPCODE_BFI2:
 891    case BRW_OPCODE_BFREV:
 892    case BRW_OPCODE_CBIT:
 893    case BRW_OPCODE_FBH:
 894    case BRW_OPCODE_FBL:
 895    case BRW_OPCODE_SUBB:
 896       return false;
 897    default:
 898       return true;
 899    }
 900 }
 901
 902 bool
 903 backend_instruction::can_do_saturate() const
 904 {
 905    switch (opcode) {
 906    case BRW_OPCODE_ADD:
 907    case BRW_OPCODE_ASR:
 908    case BRW_OPCODE_AVG:
 909    case BRW_OPCODE_DP2:
 910    case BRW_OPCODE_DP3:
 911    case BRW_OPCODE_DP4:
 912    case BRW_OPCODE_DPH:
 913    case BRW_OPCODE_F16TO32:
 914    case BRW_OPCODE_F32TO16:
 915    case BRW_OPCODE_LINE:
 916    case BRW_OPCODE_LRP:
 917    case BRW_OPCODE_MAC:
 918    case BRW_OPCODE_MACH:
 919    case BRW_OPCODE_MAD:
 920    case BRW_OPCODE_MATH:
 921    case BRW_OPCODE_MOV:
 922    case BRW_OPCODE_MUL:
 923    case BRW_OPCODE_PLN:
 924    case BRW_OPCODE_RNDD:
 925    case BRW_OPCODE_RNDE:
 926    case BRW_OPCODE_RNDU:
 927    case BRW_OPCODE_RNDZ:
 928    case BRW_OPCODE_SEL:
 929    case BRW_OPCODE_SHL:
 930    case BRW_OPCODE_SHR:
 931    case FS_OPCODE_LINTERP:
 932    case SHADER_OPCODE_COS:
 933    case SHADER_OPCODE_EXP2:
 934    case SHADER_OPCODE_LOG2:
 935    case SHADER_OPCODE_POW:
 936    case SHADER_OPCODE_RCP:
 937    case SHADER_OPCODE_RSQ:
 938    case SHADER_OPCODE_SIN:
 939    case SHADER_OPCODE_SQRT:
 940       return true;
 941    default:
 942       return false;
 943    }
 944 }
 945
 946 bool
 947 backend_instruction::can_do_cmod() const
 948 {
 949    switch (opcode) {
 950    case BRW_OPCODE_ADD:
 951    case BRW_OPCODE_ADDC:
 952    case BRW_OPCODE_AND:
 953    case BRW_OPCODE_ASR:
 954    case BRW_OPCODE_AVG:
 955    case BRW_OPCODE_CMP:
 956    case BRW_OPCODE_CMPN:
 957    case BRW_OPCODE_DP2:
 958    case BRW_OPCODE_DP3:
 959    case BRW_OPCODE_DP4:
 960    case BRW_OPCODE_DPH:
 961    case BRW_OPCODE_F16TO32:
 962    case BRW_OPCODE_F32TO16:
 963    case BRW_OPCODE_FRC:
 964    case BRW_OPCODE_LINE:
 965    case BRW_OPCODE_LRP:
 966    case BRW_OPCODE_LZD:
 967    case BRW_OPCODE_MAC:
 968    case BRW_OPCODE_MACH:
 969    case BRW_OPCODE_MAD:
 970    case BRW_OPCODE_MOV:
 971    case BRW_OPCODE_MUL:
 972    case BRW_OPCODE_NOT:
 973    case BRW_OPCODE_OR:
 974    case BRW_OPCODE_PLN:
 975    case BRW_OPCODE_RNDD:
 976    case BRW_OPCODE_RNDE:
 977    case BRW_OPCODE_RNDU:
 978    case BRW_OPCODE_RNDZ:
 979    case BRW_OPCODE_SAD2:
 980    case BRW_OPCODE_SADA2:
 981    case BRW_OPCODE_SHL:
 982    case BRW_OPCODE_SHR:
 983    case BRW_OPCODE_SUBB:
 984    case BRW_OPCODE_XOR:
 985    case FS_OPCODE_CINTERP:
 986    case FS_OPCODE_LINTERP:
 987       return true;
 988    default:
 989       return false;
 990    }
 991 }
 992
 993 bool
 994 backend_instruction::reads_accumulator_implicitly() const
 995 {
 996    switch (opcode) {
 997    case BRW_OPCODE_MAC:
 998    case BRW_OPCODE_MACH:
 999    case BRW_OPCODE_SADA2:
1000       return true;
1001    default:
1002       return false;
1003    }
1004 }
1005
1006 bool
1007 backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
1008 {
1009    return writes_accumulator ||
1010           (brw->gen < 6 &&
1011            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1012             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1013              opcode != FS_OPCODE_CINTERP)));
1014 }
1015
1016 bool
1017 backend_instruction::has_side_effects() const
1018 {
1019    switch (opcode) {
1020    case SHADER_OPCODE_UNTYPED_ATOMIC:
1021    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1022    case SHADER_OPCODE_URB_WRITE_SIMD8:
1023    case FS_OPCODE_FB_WRITE:
1024       return true;
1025    default:
1026       return false;
1027    }
1028 }
1029
1030 #ifndef NDEBUG
1031 static bool
1032 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1033 {
1034    bool found = false;
1035    foreach_inst_in_block (backend_instruction, i, block) {
1036       if (inst == i) {
1037          found = true;
1038       }
1039    }
1040    return found;
1041 }
1042 #endif
1043
1044 static void
1045 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1046 {
1047    for (bblock_t *block_iter = start_block->next();
1048         !block_iter->link.is_tail_sentinel();
1049         block_iter = block_iter->next()) {
1050       block_iter->start_ip += ip_adjustment;
1051       block_iter->end_ip += ip_adjustment;
1052    }
1053 }
1054
1055 void
1056 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1057 {
1058    if (!this->is_head_sentinel())
1059       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1060
1061    block->end_ip++;
1062
1063    adjust_later_block_ips(block, 1);
1064
1065    exec_node::insert_after(inst);
1066 }
1067
1068 void
1069 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1070 {
1071    if (!this->is_tail_sentinel())
1072       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1073
1074    block->end_ip++;
1075
1076    adjust_later_block_ips(block, 1);
1077
1078    exec_node::insert_before(inst);
1079 }
1080
1081 void
1082 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1083 {
1084    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1085
1086    unsigned num_inst = list->length();
1087
1088    block->end_ip += num_inst;
1089
1090    adjust_later_block_ips(block, num_inst);
1091
1092    exec_node::insert_before(list);
1093 }
1094
1095 void
1096 backend_instruction::remove(bblock_t *block)
1097 {
1098    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1099
1100    adjust_later_block_ips(block, -1);
1101
1102    if (block->start_ip == block->end_ip) {
1103       block->cfg->remove_block(block);
1104    } else {
1105       block->end_ip--;
1106    }
1107
1108    exec_node::remove();
1109 }
1110
1111 void
1112 backend_visitor::dump_instructions()
1113 {
1114    dump_instructions(NULL);
1115 }
1116
1117 void
1118 backend_visitor::dump_instructions(const char *name)
1119 {
1120    FILE *file = stderr;
1121    if (name && geteuid() != 0) {
1122       file = fopen(name, "w");
1123       if (!file)
1124          file = stderr;
1125    }
1126
1127    if (cfg) {
1128       int ip = 0;
1129       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1130          fprintf(file, "%4d: ", ip++);
1131          dump_instruction(inst, file);
1132       }
1133    } else {
1134       int ip = 0;
1135       foreach_in_list(backend_instruction, inst, &instructions) {
1136          fprintf(file, "%4d: ", ip++);
1137          dump_instruction(inst, file);
1138       }
1139    }
1140
1141    if (file != stderr) {
1142       fclose(file);
1143    }
1144 }
1145
1146 void
1147 backend_visitor::calculate_cfg()
1148 {
1149    if (this->cfg)
1150       return;
1151    cfg = new(mem_ctx) cfg_t(&this->instructions);
1152 }
1153
1154 void
1155 backend_visitor::invalidate_cfg()
1156 {
1157    ralloc_free(this->cfg);
1158    this->cfg = NULL;
1159 }
1160
1161 /**
1162  * Sets up the starting offsets for the groups of binding table entries
1163  * commong to all pipeline stages.
1164  *
1165  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1166  * unused but also make sure that addition of small offsets to them will
1167  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1168  */
1169 void
1170 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1171 {
1172    int num_textures = _mesa_fls(prog->SamplersUsed);
1173
1174    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1175    next_binding_table_offset += num_textures;
1176
1177    if (shader) {
1178       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1179       next_binding_table_offset += shader->base.NumUniformBlocks;
1180    } else {
1181       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1182    }
1183
1184    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1185       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1186       next_binding_table_offset++;
1187    } else {
1188       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1189    }
1190
1191    if (prog->UsesGather) {
1192       if (brw->gen >= 8) {
1193          stage_prog_data->binding_table.gather_texture_start =
1194             stage_prog_data->binding_table.texture_start;
1195       } else {
1196          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1197          next_binding_table_offset += num_textures;
1198       }
1199    } else {
1200       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1201    }
1202
1203    if (shader_prog && shader_prog->NumAtomicBuffers) {
1204       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1205       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1206    } else {
1207       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1208    }
1209
1210    if (shader && shader->base.NumImages) {
1211       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1212       next_binding_table_offset += shader->base.NumImages;
1213    } else {
1214       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1215    }
1216
1217    /* This may or may not be used depending on how the compile goes. */
1218    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1219    next_binding_table_offset++;
1220
1221    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1222
1223    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1224 }