src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
  88       compiler->scalar_vs = true;
  89
  90    nir_shader_compiler_options *nir_options =
  91       rzalloc(compiler, nir_shader_compiler_options);
  92    nir_options->native_integers = true;
  93    /* In order to help allow for better CSE at the NIR level we tell NIR
  94     * to split all ffma instructions during opt_algebraic and we then
  95     * re-combine them as a later step.
  96     */
  97    nir_options->lower_ffma = true;
  98    nir_options->lower_sub = true;
  99
 100    /* We want the GLSL compiler to emit code that uses condition codes */
 101    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 102       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 103       compiler->glsl_compiler_options[i].MaxIfDepth =
 104          devinfo->gen < 6 ? 16 : UINT_MAX;
 105
 106       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 107       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 108       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 109       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 110       compiler->glsl_compiler_options[i].EmitNoIndirectOutput =
 111          (i == MESA_SHADER_FRAGMENT);
 112       compiler->glsl_compiler_options[i].EmitNoIndirectTemp =
 113          (i == MESA_SHADER_FRAGMENT);
 114       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 115       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 116
 117       /* !ARB_gpu_shader5 */
 118       if (devinfo->gen < 7)
 119          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 120    }
 121
 122    compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = true;
 123    compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].OptimizeForAOS = true;
 124
 125    if (compiler->scalar_vs) {
 126       /* If we're using the scalar backend for vertex shaders, we need to
 127        * configure these accordingly.
 128        */
 129       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectOutput = true;
 130       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectTemp = true;
 131       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = false;
 132
 133       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions = nir_options;
 134    }
 135
 136    compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions = nir_options;
 137    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions = nir_options;
 138
 139    return compiler;
 140 }
 141
 142 struct gl_shader *
 143 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 144 {
 145    struct brw_shader *shader;
 146
 147    shader = rzalloc(NULL, struct brw_shader);
 148    if (shader) {
 149       shader->base.Type = type;
 150       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 151       shader->base.Name = name;
 152       _mesa_init_shader(ctx, &shader->base);
 153    }
 154
 155    return &shader->base;
 156 }
 157
 158 /**
 159  * Performs a compile of the shader stages even when we don't know
 160  * what non-orthogonal state will be set, in the hope that it reflects
 161  * the eventual NOS used, and thus allows us to produce link failures.
 162  */
 163 static bool
 164 brw_shader_precompile(struct gl_context *ctx,
 165                       struct gl_shader_program *sh_prog)
 166 {
 167    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 168    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 169    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 170    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 171
 172    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 173       return false;
 174
 175    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 176       return false;
 177
 178    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 179       return false;
 180
 181    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 182       return false;
 183
 184    return true;
 185 }
 186
 187 static inline bool
 188 is_scalar_shader_stage(struct brw_context *brw, int stage)
 189 {
 190    switch (stage) {
 191    case MESA_SHADER_FRAGMENT:
 192       return true;
 193    case MESA_SHADER_VERTEX:
 194       return brw->intelScreen->compiler->scalar_vs;
 195    default:
 196       return false;
 197    }
 198 }
 199
 200 static void
 201 brw_lower_packing_builtins(struct brw_context *brw,
 202                            gl_shader_stage shader_type,
 203                            exec_list *ir)
 204 {
 205    int ops = LOWER_PACK_SNORM_2x16
 206            | LOWER_UNPACK_SNORM_2x16
 207            | LOWER_PACK_UNORM_2x16
 208            | LOWER_UNPACK_UNORM_2x16;
 209
 210    if (is_scalar_shader_stage(brw, shader_type)) {
 211       ops |= LOWER_UNPACK_UNORM_4x8
 212            | LOWER_UNPACK_SNORM_4x8
 213            | LOWER_PACK_UNORM_4x8
 214            | LOWER_PACK_SNORM_4x8;
 215    }
 216
 217    if (brw->gen >= 7) {
 218       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 219        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 220        * lowering is needed. For SOA code, the Half2x16 ops must be
 221        * scalarized.
 222        */
 223       if (is_scalar_shader_stage(brw, shader_type)) {
 224          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 225              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 226       }
 227    } else {
 228       ops |= LOWER_PACK_HALF_2x16
 229           |  LOWER_UNPACK_HALF_2x16;
 230    }
 231
 232    lower_packing_builtins(ir, ops);
 233 }
 234
 235 static void
 236 process_glsl_ir(struct brw_context *brw,
 237                 struct gl_shader_program *shader_prog,
 238                 struct gl_shader *shader)
 239 {
 240    struct gl_context *ctx = &brw->ctx;
 241    const struct gl_shader_compiler_options *options =
 242       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 243
 244    /* Temporary memory context for any new IR. */
 245    void *mem_ctx = ralloc_context(NULL);
 246
 247    ralloc_adopt(mem_ctx, shader->ir);
 248
 249    /* lower_packing_builtins() inserts arithmetic instructions, so it
 250     * must precede lower_instructions().
 251     */
 252    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 253    do_mat_op_to_vec(shader->ir);
 254    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 255    lower_instructions(shader->ir,
 256                       MOD_TO_FLOOR |
 257                       DIV_TO_MUL_RCP |
 258                       SUB_TO_ADD_NEG |
 259                       EXP_TO_EXP2 |
 260                       LOG_TO_LOG2 |
 261                       bitfield_insert |
 262                       LDEXP_TO_ARITH |
 263                       CARRY_TO_ARITH |
 264                       BORROW_TO_ARITH);
 265
 266    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 267     * if-statements need to be flattened.
 268     */
 269    if (brw->gen < 6)
 270       lower_if_to_cond_assign(shader->ir, 16);
 271
 272    do_lower_texture_projection(shader->ir);
 273    brw_lower_texture_gradients(brw, shader->ir);
 274    do_vec_index_to_cond_assign(shader->ir);
 275    lower_vector_insert(shader->ir, true);
 276    if (options->NirOptions == NULL)
 277       brw_do_cubemap_normalize(shader->ir);
 278    lower_offset_arrays(shader->ir);
 279    brw_do_lower_unnormalized_offset(shader->ir);
 280    lower_noise(shader->ir);
 281    lower_quadop_vector(shader->ir, false);
 282
 283    bool lowered_variable_indexing =
 284       lower_variable_index_to_cond_assign(shader->ir,
 285                                           options->EmitNoIndirectInput,
 286                                           options->EmitNoIndirectOutput,
 287                                           options->EmitNoIndirectTemp,
 288                                           options->EmitNoIndirectUniform);
 289
 290    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 291       perf_debug("Unsupported form of variable indexing in FS; falling "
 292                  "back to very inefficient code generation\n");
 293    }
 294
 295    lower_ubo_reference(shader, shader->ir);
 296
 297    bool progress;
 298    do {
 299       progress = false;
 300
 301       if (is_scalar_shader_stage(brw, shader->Stage)) {
 302          brw_do_channel_expressions(shader->ir);
 303          brw_do_vector_splitting(shader->ir);
 304       }
 305
 306       progress = do_lower_jumps(shader->ir, true, true,
 307                                 true, /* main return */
 308                                 false, /* continue */
 309                                 false /* loops */
 310                                 ) || progress;
 311
 312       progress = do_common_optimization(shader->ir, true, true,
 313                                         options, ctx->Const.NativeIntegers) || progress;
 314    } while (progress);
 315
 316    if (options->NirOptions != NULL)
 317       lower_output_reads(shader->ir);
 318
 319    validate_ir_tree(shader->ir);
 320
 321    /* Now that we've finished altering the linked IR, reparent any live IR back
 322     * to the permanent memory context, and free the temporary one (discarding any
 323     * junk we optimized away).
 324     */
 325    reparent_ir(shader->ir, shader->ir);
 326    ralloc_free(mem_ctx);
 327
 328    if (ctx->_Shader->Flags & GLSL_DUMP) {
 329       fprintf(stderr, "\n");
 330       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 331               _mesa_shader_stage_to_string(shader->Stage),
 332               shader_prog->Name);
 333       _mesa_print_ir(stderr, shader->ir, NULL);
 334       fprintf(stderr, "\n");
 335    }
 336 }
 337
 338 GLboolean
 339 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 340 {
 341    struct brw_context *brw = brw_context(ctx);
 342    unsigned int stage;
 343
 344    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 345       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 346       const struct gl_shader_compiler_options *options =
 347          &ctx->Const.ShaderCompilerOptions[stage];
 348
 349       if (!shader)
 350          continue;
 351
 352       struct gl_program *prog =
 353          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 354                                 shader->Name);
 355       if (!prog)
 356         return false;
 357       prog->Parameters = _mesa_new_parameter_list();
 358
 359       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 360
 361       process_glsl_ir(brw, shProg, shader);
 362
 363       /* Make a pass over the IR to add state references for any built-in
 364        * uniforms that are used.  This has to be done now (during linking).
 365        * Code generation doesn't happen until the first time this shader is
 366        * used for rendering.  Waiting until then to generate the parameters is
 367        * too late.  At that point, the values for the built-in uniforms won't
 368        * get sent to the shader.
 369        */
 370       foreach_in_list(ir_instruction, node, shader->ir) {
 371          ir_variable *var = node->as_variable();
 372
 373          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 374              || (strncmp(var->name, "gl_", 3) != 0))
 375             continue;
 376
 377          const ir_state_slot *const slots = var->get_state_slots();
 378          assert(slots != NULL);
 379
 380          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 381             _mesa_add_state_reference(prog->Parameters,
 382                                       (gl_state_index *) slots[i].tokens);
 383          }
 384       }
 385
 386       do_set_program_inouts(shader->ir, prog, shader->Stage);
 387
 388       prog->SamplersUsed = shader->active_samplers;
 389       prog->ShadowSamplers = shader->shadow_samplers;
 390       _mesa_update_shader_textures_used(shProg, prog);
 391
 392       _mesa_reference_program(ctx, &shader->Program, prog);
 393
 394       brw_add_texrect_params(prog);
 395
 396       if (options->NirOptions)
 397          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 398
 399       _mesa_reference_program(ctx, &prog, NULL);
 400    }
 401
 402    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 403       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 404          const struct gl_shader *sh = shProg->Shaders[i];
 405          if (!sh)
 406             continue;
 407
 408          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 409                  _mesa_shader_stage_to_string(sh->Stage),
 410                  i, shProg->Name);
 411          fprintf(stderr, "%s", sh->Source);
 412          fprintf(stderr, "\n");
 413       }
 414    }
 415
 416    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 417       return false;
 418
 419    return true;
 420 }
 421
 422
 423 enum brw_reg_type
 424 brw_type_for_base_type(const struct glsl_type *type)
 425 {
 426    switch (type->base_type) {
 427    case GLSL_TYPE_FLOAT:
 428       return BRW_REGISTER_TYPE_F;
 429    case GLSL_TYPE_INT:
 430    case GLSL_TYPE_BOOL:
 431       return BRW_REGISTER_TYPE_D;
 432    case GLSL_TYPE_UINT:
 433       return BRW_REGISTER_TYPE_UD;
 434    case GLSL_TYPE_ARRAY:
 435       return brw_type_for_base_type(type->fields.array);
 436    case GLSL_TYPE_STRUCT:
 437    case GLSL_TYPE_SAMPLER:
 438    case GLSL_TYPE_ATOMIC_UINT:
 439       /* These should be overridden with the type of the member when
 440        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 441        * way to trip up if we don't.
 442        */
 443       return BRW_REGISTER_TYPE_UD;
 444    case GLSL_TYPE_IMAGE:
 445       return BRW_REGISTER_TYPE_UD;
 446    case GLSL_TYPE_VOID:
 447    case GLSL_TYPE_ERROR:
 448    case GLSL_TYPE_INTERFACE:
 449    case GLSL_TYPE_DOUBLE:
 450       unreachable("not reached");
 451    }
 452
 453    return BRW_REGISTER_TYPE_F;
 454 }
 455
 456 enum brw_conditional_mod
 457 brw_conditional_for_comparison(unsigned int op)
 458 {
 459    switch (op) {
 460    case ir_binop_less:
 461       return BRW_CONDITIONAL_L;
 462    case ir_binop_greater:
 463       return BRW_CONDITIONAL_G;
 464    case ir_binop_lequal:
 465       return BRW_CONDITIONAL_LE;
 466    case ir_binop_gequal:
 467       return BRW_CONDITIONAL_GE;
 468    case ir_binop_equal:
 469    case ir_binop_all_equal: /* same as equal for scalars */
 470       return BRW_CONDITIONAL_Z;
 471    case ir_binop_nequal:
 472    case ir_binop_any_nequal: /* same as nequal for scalars */
 473       return BRW_CONDITIONAL_NZ;
 474    default:
 475       unreachable("not reached: bad operation for comparison");
 476    }
 477 }
 478
 479 uint32_t
 480 brw_math_function(enum opcode op)
 481 {
 482    switch (op) {
 483    case SHADER_OPCODE_RCP:
 484       return BRW_MATH_FUNCTION_INV;
 485    case SHADER_OPCODE_RSQ:
 486       return BRW_MATH_FUNCTION_RSQ;
 487    case SHADER_OPCODE_SQRT:
 488       return BRW_MATH_FUNCTION_SQRT;
 489    case SHADER_OPCODE_EXP2:
 490       return BRW_MATH_FUNCTION_EXP;
 491    case SHADER_OPCODE_LOG2:
 492       return BRW_MATH_FUNCTION_LOG;
 493    case SHADER_OPCODE_POW:
 494       return BRW_MATH_FUNCTION_POW;
 495    case SHADER_OPCODE_SIN:
 496       return BRW_MATH_FUNCTION_SIN;
 497    case SHADER_OPCODE_COS:
 498       return BRW_MATH_FUNCTION_COS;
 499    case SHADER_OPCODE_INT_QUOTIENT:
 500       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 501    case SHADER_OPCODE_INT_REMAINDER:
 502       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 503    default:
 504       unreachable("not reached: unknown math function");
 505    }
 506 }
 507
 508 uint32_t
 509 brw_texture_offset(int *offsets, unsigned num_components)
 510 {
 511    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 512
 513    /* Combine all three offsets into a single unsigned dword:
 514     *
 515     *    bits 11:8 - U Offset (X component)
 516     *    bits  7:4 - V Offset (Y component)
 517     *    bits  3:0 - R Offset (Z component)
 518     */
 519    unsigned offset_bits = 0;
 520    for (unsigned i = 0; i < num_components; i++) {
 521       const unsigned shift = 4 * (2 - i);
 522       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 523    }
 524    return offset_bits;
 525 }
 526
 527 const char *
 528 brw_instruction_name(enum opcode op)
 529 {
 530    switch (op) {
 531    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 532       assert(opcode_descs[op].name);
 533       return opcode_descs[op].name;
 534    case FS_OPCODE_FB_WRITE:
 535       return "fb_write";
 536    case FS_OPCODE_BLORP_FB_WRITE:
 537       return "blorp_fb_write";
 538    case FS_OPCODE_REP_FB_WRITE:
 539       return "rep_fb_write";
 540
 541    case SHADER_OPCODE_RCP:
 542       return "rcp";
 543    case SHADER_OPCODE_RSQ:
 544       return "rsq";
 545    case SHADER_OPCODE_SQRT:
 546       return "sqrt";
 547    case SHADER_OPCODE_EXP2:
 548       return "exp2";
 549    case SHADER_OPCODE_LOG2:
 550       return "log2";
 551    case SHADER_OPCODE_POW:
 552       return "pow";
 553    case SHADER_OPCODE_INT_QUOTIENT:
 554       return "int_quot";
 555    case SHADER_OPCODE_INT_REMAINDER:
 556       return "int_rem";
 557    case SHADER_OPCODE_SIN:
 558       return "sin";
 559    case SHADER_OPCODE_COS:
 560       return "cos";
 561
 562    case SHADER_OPCODE_TEX:
 563       return "tex";
 564    case SHADER_OPCODE_TXD:
 565       return "txd";
 566    case SHADER_OPCODE_TXF:
 567       return "txf";
 568    case SHADER_OPCODE_TXL:
 569       return "txl";
 570    case SHADER_OPCODE_TXS:
 571       return "txs";
 572    case FS_OPCODE_TXB:
 573       return "txb";
 574    case SHADER_OPCODE_TXF_CMS:
 575       return "txf_cms";
 576    case SHADER_OPCODE_TXF_UMS:
 577       return "txf_ums";
 578    case SHADER_OPCODE_TXF_MCS:
 579       return "txf_mcs";
 580    case SHADER_OPCODE_LOD:
 581       return "lod";
 582    case SHADER_OPCODE_TG4:
 583       return "tg4";
 584    case SHADER_OPCODE_TG4_OFFSET:
 585       return "tg4_offset";
 586    case SHADER_OPCODE_SHADER_TIME_ADD:
 587       return "shader_time_add";
 588
 589    case SHADER_OPCODE_UNTYPED_ATOMIC:
 590       return "untyped_atomic";
 591    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 592       return "untyped_surface_read";
 593    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 594       return "untyped_surface_write";
 595    case SHADER_OPCODE_TYPED_ATOMIC:
 596       return "typed_atomic";
 597    case SHADER_OPCODE_TYPED_SURFACE_READ:
 598       return "typed_surface_read";
 599    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 600       return "typed_surface_write";
 601    case SHADER_OPCODE_MEMORY_FENCE:
 602       return "memory_fence";
 603
 604    case SHADER_OPCODE_LOAD_PAYLOAD:
 605       return "load_payload";
 606
 607    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 608       return "gen4_scratch_read";
 609    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 610       return "gen4_scratch_write";
 611    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 612       return "gen7_scratch_read";
 613    case SHADER_OPCODE_URB_WRITE_SIMD8:
 614       return "gen8_urb_write_simd8";
 615
 616    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 617       return "find_live_channel";
 618    case SHADER_OPCODE_BROADCAST:
 619       return "broadcast";
 620
 621    case VEC4_OPCODE_MOV_BYTES:
 622       return "mov_bytes";
 623    case VEC4_OPCODE_PACK_BYTES:
 624       return "pack_bytes";
 625    case VEC4_OPCODE_UNPACK_UNIFORM:
 626       return "unpack_uniform";
 627
 628    case FS_OPCODE_DDX_COARSE:
 629       return "ddx_coarse";
 630    case FS_OPCODE_DDX_FINE:
 631       return "ddx_fine";
 632    case FS_OPCODE_DDY_COARSE:
 633       return "ddy_coarse";
 634    case FS_OPCODE_DDY_FINE:
 635       return "ddy_fine";
 636
 637    case FS_OPCODE_CINTERP:
 638       return "cinterp";
 639    case FS_OPCODE_LINTERP:
 640       return "linterp";
 641
 642    case FS_OPCODE_PIXEL_X:
 643       return "pixel_x";
 644    case FS_OPCODE_PIXEL_Y:
 645       return "pixel_y";
 646
 647    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 648       return "uniform_pull_const";
 649    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 650       return "uniform_pull_const_gen7";
 651    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 652       return "varying_pull_const";
 653    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 654       return "varying_pull_const_gen7";
 655
 656    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 657       return "mov_dispatch_to_flags";
 658    case FS_OPCODE_DISCARD_JUMP:
 659       return "discard_jump";
 660
 661    case FS_OPCODE_SET_OMASK:
 662       return "set_omask";
 663    case FS_OPCODE_SET_SAMPLE_ID:
 664       return "set_sample_id";
 665    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 666       return "set_simd4x2_offset";
 667
 668    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 669       return "pack_half_2x16_split";
 670    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 671       return "unpack_half_2x16_split_x";
 672    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 673       return "unpack_half_2x16_split_y";
 674
 675    case FS_OPCODE_PLACEHOLDER_HALT:
 676       return "placeholder_halt";
 677
 678    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 679       return "interp_centroid";
 680    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 681       return "interp_sample";
 682    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 683       return "interp_shared_offset";
 684    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 685       return "interp_per_slot_offset";
 686
 687    case VS_OPCODE_URB_WRITE:
 688       return "vs_urb_write";
 689    case VS_OPCODE_PULL_CONSTANT_LOAD:
 690       return "pull_constant_load";
 691    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 692       return "pull_constant_load_gen7";
 693
 694    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 695       return "set_simd4x2_header_gen9";
 696
 697    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 698       return "unpack_flags_simd4x2";
 699
 700    case GS_OPCODE_URB_WRITE:
 701       return "gs_urb_write";
 702    case GS_OPCODE_URB_WRITE_ALLOCATE:
 703       return "gs_urb_write_allocate";
 704    case GS_OPCODE_THREAD_END:
 705       return "gs_thread_end";
 706    case GS_OPCODE_SET_WRITE_OFFSET:
 707       return "set_write_offset";
 708    case GS_OPCODE_SET_VERTEX_COUNT:
 709       return "set_vertex_count";
 710    case GS_OPCODE_SET_DWORD_2:
 711       return "set_dword_2";
 712    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 713       return "prepare_channel_masks";
 714    case GS_OPCODE_SET_CHANNEL_MASKS:
 715       return "set_channel_masks";
 716    case GS_OPCODE_GET_INSTANCE_ID:
 717       return "get_instance_id";
 718    case GS_OPCODE_FF_SYNC:
 719       return "ff_sync";
 720    case GS_OPCODE_SET_PRIMITIVE_ID:
 721       return "set_primitive_id";
 722    case GS_OPCODE_SVB_WRITE:
 723       return "gs_svb_write";
 724    case GS_OPCODE_SVB_SET_DST_INDEX:
 725       return "gs_svb_set_dst_index";
 726    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 727       return "gs_ff_sync_set_primitives";
 728    case CS_OPCODE_CS_TERMINATE:
 729       return "cs_terminate";
 730    case SHADER_OPCODE_BARRIER:
 731       return "barrier";
 732    }
 733
 734    unreachable("not reached");
 735 }
 736
 737 bool
 738 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 739 {
 740    union {
 741       unsigned ud;
 742       int d;
 743       float f;
 744    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 745
 746    switch (type) {
 747    case BRW_REGISTER_TYPE_UD:
 748    case BRW_REGISTER_TYPE_D:
 749    case BRW_REGISTER_TYPE_UQ:
 750    case BRW_REGISTER_TYPE_Q:
 751       /* Nothing to do. */
 752       return false;
 753    case BRW_REGISTER_TYPE_UW:
 754       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 755       break;
 756    case BRW_REGISTER_TYPE_W:
 757       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 758       break;
 759    case BRW_REGISTER_TYPE_F:
 760       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 761       break;
 762    case BRW_REGISTER_TYPE_UB:
 763    case BRW_REGISTER_TYPE_B:
 764       unreachable("no UB/B immediates");
 765    case BRW_REGISTER_TYPE_V:
 766    case BRW_REGISTER_TYPE_UV:
 767    case BRW_REGISTER_TYPE_VF:
 768       unreachable("unimplemented: saturate vector immediate");
 769    case BRW_REGISTER_TYPE_DF:
 770    case BRW_REGISTER_TYPE_HF:
 771       unreachable("unimplemented: saturate DF/HF immediate");
 772    }
 773
 774    if (imm.ud != sat_imm.ud) {
 775       reg->dw1.ud = sat_imm.ud;
 776       return true;
 777    }
 778    return false;
 779 }
 780
 781 bool
 782 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 783 {
 784    switch (type) {
 785    case BRW_REGISTER_TYPE_D:
 786    case BRW_REGISTER_TYPE_UD:
 787       reg->dw1.d = -reg->dw1.d;
 788       return true;
 789    case BRW_REGISTER_TYPE_W:
 790    case BRW_REGISTER_TYPE_UW:
 791       reg->dw1.d = -(int16_t)reg->dw1.ud;
 792       return true;
 793    case BRW_REGISTER_TYPE_F:
 794       reg->dw1.f = -reg->dw1.f;
 795       return true;
 796    case BRW_REGISTER_TYPE_VF:
 797       reg->dw1.ud ^= 0x80808080;
 798       return true;
 799    case BRW_REGISTER_TYPE_UB:
 800    case BRW_REGISTER_TYPE_B:
 801       unreachable("no UB/B immediates");
 802    case BRW_REGISTER_TYPE_UV:
 803    case BRW_REGISTER_TYPE_V:
 804       assert(!"unimplemented: negate UV/V immediate");
 805    case BRW_REGISTER_TYPE_UQ:
 806    case BRW_REGISTER_TYPE_Q:
 807       assert(!"unimplemented: negate UQ/Q immediate");
 808    case BRW_REGISTER_TYPE_DF:
 809    case BRW_REGISTER_TYPE_HF:
 810       assert(!"unimplemented: negate DF/HF immediate");
 811    }
 812
 813    return false;
 814 }
 815
 816 bool
 817 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 818 {
 819    switch (type) {
 820    case BRW_REGISTER_TYPE_D:
 821       reg->dw1.d = abs(reg->dw1.d);
 822       return true;
 823    case BRW_REGISTER_TYPE_W:
 824       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 825       return true;
 826    case BRW_REGISTER_TYPE_F:
 827       reg->dw1.f = fabsf(reg->dw1.f);
 828       return true;
 829    case BRW_REGISTER_TYPE_VF:
 830       reg->dw1.ud &= ~0x80808080;
 831       return true;
 832    case BRW_REGISTER_TYPE_UB:
 833    case BRW_REGISTER_TYPE_B:
 834       unreachable("no UB/B immediates");
 835    case BRW_REGISTER_TYPE_UQ:
 836    case BRW_REGISTER_TYPE_UD:
 837    case BRW_REGISTER_TYPE_UW:
 838    case BRW_REGISTER_TYPE_UV:
 839       /* Presumably the absolute value modifier on an unsigned source is a
 840        * nop, but it would be nice to confirm.
 841        */
 842       assert(!"unimplemented: abs unsigned immediate");
 843    case BRW_REGISTER_TYPE_V:
 844       assert(!"unimplemented: abs V immediate");
 845    case BRW_REGISTER_TYPE_Q:
 846       assert(!"unimplemented: abs Q immediate");
 847    case BRW_REGISTER_TYPE_DF:
 848    case BRW_REGISTER_TYPE_HF:
 849       assert(!"unimplemented: abs DF/HF immediate");
 850    }
 851
 852    return false;
 853 }
 854
 855 backend_shader::backend_shader(const struct brw_compiler *compiler,
 856                                void *log_data,
 857                                void *mem_ctx,
 858                                struct gl_shader_program *shader_prog,
 859                                struct gl_program *prog,
 860                                struct brw_stage_prog_data *stage_prog_data,
 861                                gl_shader_stage stage)
 862    : compiler(compiler),
 863      log_data(log_data),
 864      devinfo(compiler->devinfo),
 865      shader(shader_prog ?
 866         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 867      shader_prog(shader_prog),
 868      prog(prog),
 869      stage_prog_data(stage_prog_data),
 870      mem_ctx(mem_ctx),
 871      cfg(NULL),
 872      stage(stage)
 873 {
 874    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 875    stage_name = _mesa_shader_stage_to_string(stage);
 876    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 877 }
 878
 879 bool
 880 backend_reg::is_zero() const
 881 {
 882    if (file != IMM)
 883       return false;
 884
 885    return fixed_hw_reg.dw1.d == 0;
 886 }
 887
 888 bool
 889 backend_reg::is_one() const
 890 {
 891    if (file != IMM)
 892       return false;
 893
 894    return type == BRW_REGISTER_TYPE_F
 895           ? fixed_hw_reg.dw1.f == 1.0
 896           : fixed_hw_reg.dw1.d == 1;
 897 }
 898
 899 bool
 900 backend_reg::is_negative_one() const
 901 {
 902    if (file != IMM)
 903       return false;
 904
 905    switch (type) {
 906    case BRW_REGISTER_TYPE_F:
 907       return fixed_hw_reg.dw1.f == -1.0;
 908    case BRW_REGISTER_TYPE_D:
 909       return fixed_hw_reg.dw1.d == -1;
 910    default:
 911       return false;
 912    }
 913 }
 914
 915 bool
 916 backend_reg::is_null() const
 917 {
 918    return file == HW_REG &&
 919           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 920           fixed_hw_reg.nr == BRW_ARF_NULL;
 921 }
 922
 923
 924 bool
 925 backend_reg::is_accumulator() const
 926 {
 927    return file == HW_REG &&
 928           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 929           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 930 }
 931
 932 bool
 933 backend_reg::in_range(const backend_reg &r, unsigned n) const
 934 {
 935    return (file == r.file &&
 936            reg == r.reg &&
 937            reg_offset >= r.reg_offset &&
 938            reg_offset < r.reg_offset + n);
 939 }
 940
 941 bool
 942 backend_instruction::is_commutative() const
 943 {
 944    switch (opcode) {
 945    case BRW_OPCODE_AND:
 946    case BRW_OPCODE_OR:
 947    case BRW_OPCODE_XOR:
 948    case BRW_OPCODE_ADD:
 949    case BRW_OPCODE_MUL:
 950       return true;
 951    case BRW_OPCODE_SEL:
 952       /* MIN and MAX are commutative. */
 953       if (conditional_mod == BRW_CONDITIONAL_GE ||
 954           conditional_mod == BRW_CONDITIONAL_L) {
 955          return true;
 956       }
 957       /* fallthrough */
 958    default:
 959       return false;
 960    }
 961 }
 962
 963 bool
 964 backend_instruction::is_3src() const
 965 {
 966    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 967 }
 968
 969 bool
 970 backend_instruction::is_tex() const
 971 {
 972    return (opcode == SHADER_OPCODE_TEX ||
 973            opcode == FS_OPCODE_TXB ||
 974            opcode == SHADER_OPCODE_TXD ||
 975            opcode == SHADER_OPCODE_TXF ||
 976            opcode == SHADER_OPCODE_TXF_CMS ||
 977            opcode == SHADER_OPCODE_TXF_UMS ||
 978            opcode == SHADER_OPCODE_TXF_MCS ||
 979            opcode == SHADER_OPCODE_TXL ||
 980            opcode == SHADER_OPCODE_TXS ||
 981            opcode == SHADER_OPCODE_LOD ||
 982            opcode == SHADER_OPCODE_TG4 ||
 983            opcode == SHADER_OPCODE_TG4_OFFSET);
 984 }
 985
 986 bool
 987 backend_instruction::is_math() const
 988 {
 989    return (opcode == SHADER_OPCODE_RCP ||
 990            opcode == SHADER_OPCODE_RSQ ||
 991            opcode == SHADER_OPCODE_SQRT ||
 992            opcode == SHADER_OPCODE_EXP2 ||
 993            opcode == SHADER_OPCODE_LOG2 ||
 994            opcode == SHADER_OPCODE_SIN ||
 995            opcode == SHADER_OPCODE_COS ||
 996            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 997            opcode == SHADER_OPCODE_INT_REMAINDER ||
 998            opcode == SHADER_OPCODE_POW);
 999 }
1000
1001 bool
1002 backend_instruction::is_control_flow() const
1003 {
1004    switch (opcode) {
1005    case BRW_OPCODE_DO:
1006    case BRW_OPCODE_WHILE:
1007    case BRW_OPCODE_IF:
1008    case BRW_OPCODE_ELSE:
1009    case BRW_OPCODE_ENDIF:
1010    case BRW_OPCODE_BREAK:
1011    case BRW_OPCODE_CONTINUE:
1012       return true;
1013    default:
1014       return false;
1015    }
1016 }
1017
1018 bool
1019 backend_instruction::can_do_source_mods() const
1020 {
1021    switch (opcode) {
1022    case BRW_OPCODE_ADDC:
1023    case BRW_OPCODE_BFE:
1024    case BRW_OPCODE_BFI1:
1025    case BRW_OPCODE_BFI2:
1026    case BRW_OPCODE_BFREV:
1027    case BRW_OPCODE_CBIT:
1028    case BRW_OPCODE_FBH:
1029    case BRW_OPCODE_FBL:
1030    case BRW_OPCODE_SUBB:
1031       return false;
1032    default:
1033       return true;
1034    }
1035 }
1036
1037 bool
1038 backend_instruction::can_do_saturate() const
1039 {
1040    switch (opcode) {
1041    case BRW_OPCODE_ADD:
1042    case BRW_OPCODE_ASR:
1043    case BRW_OPCODE_AVG:
1044    case BRW_OPCODE_DP2:
1045    case BRW_OPCODE_DP3:
1046    case BRW_OPCODE_DP4:
1047    case BRW_OPCODE_DPH:
1048    case BRW_OPCODE_F16TO32:
1049    case BRW_OPCODE_F32TO16:
1050    case BRW_OPCODE_LINE:
1051    case BRW_OPCODE_LRP:
1052    case BRW_OPCODE_MAC:
1053    case BRW_OPCODE_MAD:
1054    case BRW_OPCODE_MATH:
1055    case BRW_OPCODE_MOV:
1056    case BRW_OPCODE_MUL:
1057    case BRW_OPCODE_PLN:
1058    case BRW_OPCODE_RNDD:
1059    case BRW_OPCODE_RNDE:
1060    case BRW_OPCODE_RNDU:
1061    case BRW_OPCODE_RNDZ:
1062    case BRW_OPCODE_SEL:
1063    case BRW_OPCODE_SHL:
1064    case BRW_OPCODE_SHR:
1065    case FS_OPCODE_LINTERP:
1066    case SHADER_OPCODE_COS:
1067    case SHADER_OPCODE_EXP2:
1068    case SHADER_OPCODE_LOG2:
1069    case SHADER_OPCODE_POW:
1070    case SHADER_OPCODE_RCP:
1071    case SHADER_OPCODE_RSQ:
1072    case SHADER_OPCODE_SIN:
1073    case SHADER_OPCODE_SQRT:
1074       return true;
1075    default:
1076       return false;
1077    }
1078 }
1079
1080 bool
1081 backend_instruction::can_do_cmod() const
1082 {
1083    switch (opcode) {
1084    case BRW_OPCODE_ADD:
1085    case BRW_OPCODE_ADDC:
1086    case BRW_OPCODE_AND:
1087    case BRW_OPCODE_ASR:
1088    case BRW_OPCODE_AVG:
1089    case BRW_OPCODE_CMP:
1090    case BRW_OPCODE_CMPN:
1091    case BRW_OPCODE_DP2:
1092    case BRW_OPCODE_DP3:
1093    case BRW_OPCODE_DP4:
1094    case BRW_OPCODE_DPH:
1095    case BRW_OPCODE_F16TO32:
1096    case BRW_OPCODE_F32TO16:
1097    case BRW_OPCODE_FRC:
1098    case BRW_OPCODE_LINE:
1099    case BRW_OPCODE_LRP:
1100    case BRW_OPCODE_LZD:
1101    case BRW_OPCODE_MAC:
1102    case BRW_OPCODE_MACH:
1103    case BRW_OPCODE_MAD:
1104    case BRW_OPCODE_MOV:
1105    case BRW_OPCODE_MUL:
1106    case BRW_OPCODE_NOT:
1107    case BRW_OPCODE_OR:
1108    case BRW_OPCODE_PLN:
1109    case BRW_OPCODE_RNDD:
1110    case BRW_OPCODE_RNDE:
1111    case BRW_OPCODE_RNDU:
1112    case BRW_OPCODE_RNDZ:
1113    case BRW_OPCODE_SAD2:
1114    case BRW_OPCODE_SADA2:
1115    case BRW_OPCODE_SHL:
1116    case BRW_OPCODE_SHR:
1117    case BRW_OPCODE_SUBB:
1118    case BRW_OPCODE_XOR:
1119    case FS_OPCODE_CINTERP:
1120    case FS_OPCODE_LINTERP:
1121       return true;
1122    default:
1123       return false;
1124    }
1125 }
1126
1127 bool
1128 backend_instruction::reads_accumulator_implicitly() const
1129 {
1130    switch (opcode) {
1131    case BRW_OPCODE_MAC:
1132    case BRW_OPCODE_MACH:
1133    case BRW_OPCODE_SADA2:
1134       return true;
1135    default:
1136       return false;
1137    }
1138 }
1139
1140 bool
1141 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1142 {
1143    return writes_accumulator ||
1144           (devinfo->gen < 6 &&
1145            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1146             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1147              opcode != FS_OPCODE_CINTERP)));
1148 }
1149
1150 bool
1151 backend_instruction::has_side_effects() const
1152 {
1153    switch (opcode) {
1154    case SHADER_OPCODE_UNTYPED_ATOMIC:
1155    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1156    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1157    case SHADER_OPCODE_TYPED_ATOMIC:
1158    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1159    case SHADER_OPCODE_MEMORY_FENCE:
1160    case SHADER_OPCODE_URB_WRITE_SIMD8:
1161    case FS_OPCODE_FB_WRITE:
1162    case SHADER_OPCODE_BARRIER:
1163       return true;
1164    default:
1165       return false;
1166    }
1167 }
1168
1169 #ifndef NDEBUG
1170 static bool
1171 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1172 {
1173    bool found = false;
1174    foreach_inst_in_block (backend_instruction, i, block) {
1175       if (inst == i) {
1176          found = true;
1177       }
1178    }
1179    return found;
1180 }
1181 #endif
1182
1183 static void
1184 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1185 {
1186    for (bblock_t *block_iter = start_block->next();
1187         !block_iter->link.is_tail_sentinel();
1188         block_iter = block_iter->next()) {
1189       block_iter->start_ip += ip_adjustment;
1190       block_iter->end_ip += ip_adjustment;
1191    }
1192 }
1193
1194 void
1195 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1196 {
1197    if (!this->is_head_sentinel())
1198       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1199
1200    block->end_ip++;
1201
1202    adjust_later_block_ips(block, 1);
1203
1204    exec_node::insert_after(inst);
1205 }
1206
1207 void
1208 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1209 {
1210    if (!this->is_tail_sentinel())
1211       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1212
1213    block->end_ip++;
1214
1215    adjust_later_block_ips(block, 1);
1216
1217    exec_node::insert_before(inst);
1218 }
1219
1220 void
1221 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1222 {
1223    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1224
1225    unsigned num_inst = list->length();
1226
1227    block->end_ip += num_inst;
1228
1229    adjust_later_block_ips(block, num_inst);
1230
1231    exec_node::insert_before(list);
1232 }
1233
1234 void
1235 backend_instruction::remove(bblock_t *block)
1236 {
1237    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1238
1239    adjust_later_block_ips(block, -1);
1240
1241    if (block->start_ip == block->end_ip) {
1242       block->cfg->remove_block(block);
1243    } else {
1244       block->end_ip--;
1245    }
1246
1247    exec_node::remove();
1248 }
1249
1250 void
1251 backend_shader::dump_instructions()
1252 {
1253    dump_instructions(NULL);
1254 }
1255
1256 void
1257 backend_shader::dump_instructions(const char *name)
1258 {
1259    FILE *file = stderr;
1260    if (name && geteuid() != 0) {
1261       file = fopen(name, "w");
1262       if (!file)
1263          file = stderr;
1264    }
1265
1266    if (cfg) {
1267       int ip = 0;
1268       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1269          fprintf(file, "%4d: ", ip++);
1270          dump_instruction(inst, file);
1271       }
1272    } else {
1273       int ip = 0;
1274       foreach_in_list(backend_instruction, inst, &instructions) {
1275          fprintf(file, "%4d: ", ip++);
1276          dump_instruction(inst, file);
1277       }
1278    }
1279
1280    if (file != stderr) {
1281       fclose(file);
1282    }
1283 }
1284
1285 void
1286 backend_shader::calculate_cfg()
1287 {
1288    if (this->cfg)
1289       return;
1290    cfg = new(mem_ctx) cfg_t(&this->instructions);
1291 }
1292
1293 void
1294 backend_shader::invalidate_cfg()
1295 {
1296    ralloc_free(this->cfg);
1297    this->cfg = NULL;
1298 }
1299
1300 /**
1301  * Sets up the starting offsets for the groups of binding table entries
1302  * commong to all pipeline stages.
1303  *
1304  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1305  * unused but also make sure that addition of small offsets to them will
1306  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1307  */
1308 void
1309 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1310 {
1311    int num_textures = _mesa_fls(prog->SamplersUsed);
1312
1313    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1314    next_binding_table_offset += num_textures;
1315
1316    if (shader) {
1317       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1318       next_binding_table_offset += shader->base.NumUniformBlocks;
1319    } else {
1320       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1321    }
1322
1323    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1324       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1325       next_binding_table_offset++;
1326    } else {
1327       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1328    }
1329
1330    if (prog->UsesGather) {
1331       if (devinfo->gen >= 8) {
1332          stage_prog_data->binding_table.gather_texture_start =
1333             stage_prog_data->binding_table.texture_start;
1334       } else {
1335          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1336          next_binding_table_offset += num_textures;
1337       }
1338    } else {
1339       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1340    }
1341
1342    if (shader_prog && shader_prog->NumAtomicBuffers) {
1343       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1344       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1345    } else {
1346       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1347    }
1348
1349    if (shader && shader->base.NumImages) {
1350       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1351       next_binding_table_offset += shader->base.NumImages;
1352    } else {
1353       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1354    }
1355
1356    /* This may or may not be used depending on how the compile goes. */
1357    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1358    next_binding_table_offset++;
1359
1360    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1361
1362    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1363 }