i965: relax brw_texture_offset assert
[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 extern "C" {
25 #include "main/macros.h"
26 #include "brw_context.h"
27 }
28 #include "brw_vs.h"
29 #include "brw_vec4_gs.h"
30 #include "brw_fs.h"
31 #include "glsl/ir_optimization.h"
32 #include "glsl/glsl_parser_extras.h"
33 #include "main/shaderapi.h"
34
35 struct gl_shader *
36 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
37 {
38 struct brw_shader *shader;
39
40 shader = rzalloc(NULL, struct brw_shader);
41 if (shader) {
42 shader->base.Type = type;
43 shader->base.Name = name;
44 _mesa_init_shader(ctx, &shader->base);
45 }
46
47 return &shader->base;
48 }
49
50 struct gl_shader_program *
51 brw_new_shader_program(struct gl_context *ctx, GLuint name)
52 {
53 struct gl_shader_program *prog = rzalloc(NULL, struct gl_shader_program);
54 if (prog) {
55 prog->Name = name;
56 _mesa_init_shader_program(ctx, prog);
57 }
58 return prog;
59 }
60
61 /**
62 * Performs a compile of the shader stages even when we don't know
63 * what non-orthogonal state will be set, in the hope that it reflects
64 * the eventual NOS used, and thus allows us to produce link failures.
65 */
66 static bool
67 brw_shader_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
68 {
69 struct brw_context *brw = brw_context(ctx);
70
71 if (brw->precompile && !brw_fs_precompile(ctx, prog))
72 return false;
73
74 if (brw->precompile && !brw_gs_precompile(ctx, prog))
75 return false;
76
77 if (brw->precompile && !brw_vs_precompile(ctx, prog))
78 return false;
79
80 return true;
81 }
82
83 static void
84 brw_lower_packing_builtins(struct brw_context *brw,
85 gl_shader_type shader_type,
86 exec_list *ir)
87 {
88 int ops = LOWER_PACK_SNORM_2x16
89 | LOWER_UNPACK_SNORM_2x16
90 | LOWER_PACK_UNORM_2x16
91 | LOWER_UNPACK_UNORM_2x16
92 | LOWER_PACK_SNORM_4x8
93 | LOWER_UNPACK_SNORM_4x8
94 | LOWER_PACK_UNORM_4x8
95 | LOWER_UNPACK_UNORM_4x8;
96
97 if (brw->gen >= 7) {
98 /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
99 * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
100 * lowering is needed. For SOA code, the Half2x16 ops must be
101 * scalarized.
102 */
103 if (shader_type == MESA_SHADER_FRAGMENT) {
104 ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
105 | LOWER_UNPACK_HALF_2x16_TO_SPLIT;
106 }
107 } else {
108 ops |= LOWER_PACK_HALF_2x16
109 | LOWER_UNPACK_HALF_2x16;
110 }
111
112 lower_packing_builtins(ir, ops);
113 }
114
115 GLboolean
116 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
117 {
118 struct brw_context *brw = brw_context(ctx);
119 unsigned int stage;
120
121 for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
122 struct brw_shader *shader =
123 (struct brw_shader *)shProg->_LinkedShaders[stage];
124
125 if (!shader)
126 continue;
127
128 struct gl_program *prog =
129 ctx->Driver.NewProgram(ctx, _mesa_program_index_to_target(stage),
130 shader->base.Name);
131 if (!prog)
132 return false;
133 prog->Parameters = _mesa_new_parameter_list();
134
135 _mesa_copy_linked_program_data((gl_shader_type) stage, shProg, prog);
136
137 void *mem_ctx = ralloc_context(NULL);
138 bool progress;
139
140 if (shader->ir)
141 ralloc_free(shader->ir);
142 shader->ir = new(shader) exec_list;
143 clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
144
145 /* lower_packing_builtins() inserts arithmetic instructions, so it
146 * must precede lower_instructions().
147 */
148 brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader->ir);
149 do_mat_op_to_vec(shader->ir);
150 const int bitfield_insert = brw->gen >= 7
151 ? BITFIELD_INSERT_TO_BFM_BFI
152 : 0;
153 const int lrp_to_arith = brw->gen < 6 ? LRP_TO_ARITH : 0;
154 lower_instructions(shader->ir,
155 MOD_TO_FRACT |
156 DIV_TO_MUL_RCP |
157 SUB_TO_ADD_NEG |
158 EXP_TO_EXP2 |
159 LOG_TO_LOG2 |
160 bitfield_insert |
161 lrp_to_arith |
162 LDEXP_TO_ARITH);
163
164 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
165 * if-statements need to be flattened.
166 */
167 if (brw->gen < 6)
168 lower_if_to_cond_assign(shader->ir, 16);
169
170 do_lower_texture_projection(shader->ir);
171 brw_lower_texture_gradients(brw, shader->ir);
172 do_vec_index_to_cond_assign(shader->ir);
173 lower_vector_insert(shader->ir, true);
174 brw_do_cubemap_normalize(shader->ir);
175 lower_noise(shader->ir);
176 lower_quadop_vector(shader->ir, false);
177
178 bool input = true;
179 bool output = stage == MESA_SHADER_FRAGMENT;
180 bool temp = stage == MESA_SHADER_FRAGMENT;
181 bool uniform = false;
182
183 bool lowered_variable_indexing =
184 lower_variable_index_to_cond_assign(shader->ir,
185 input, output, temp, uniform);
186
187 if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
188 perf_debug("Unsupported form of variable indexing in FS; falling "
189 "back to very inefficient code generation\n");
190 }
191
192 /* FINISHME: Do this before the variable index lowering. */
193 lower_ubo_reference(&shader->base, shader->ir);
194
195 do {
196 progress = false;
197
198 if (stage == MESA_SHADER_FRAGMENT) {
199 brw_do_channel_expressions(shader->ir);
200 brw_do_vector_splitting(shader->ir);
201 }
202
203 progress = do_lower_jumps(shader->ir, true, true,
204 true, /* main return */
205 false, /* continue */
206 false /* loops */
207 ) || progress;
208
209 progress = do_common_optimization(shader->ir, true, true, 32,
210 &ctx->ShaderCompilerOptions[stage])
211 || progress;
212 } while (progress);
213
214 /* Make a pass over the IR to add state references for any built-in
215 * uniforms that are used. This has to be done now (during linking).
216 * Code generation doesn't happen until the first time this shader is
217 * used for rendering. Waiting until then to generate the parameters is
218 * too late. At that point, the values for the built-in uniforms won't
219 * get sent to the shader.
220 */
221 foreach_list(node, shader->ir) {
222 ir_variable *var = ((ir_instruction *) node)->as_variable();
223
224 if ((var == NULL) || (var->mode != ir_var_uniform)
225 || (strncmp(var->name, "gl_", 3) != 0))
226 continue;
227
228 const ir_state_slot *const slots = var->state_slots;
229 assert(var->state_slots != NULL);
230
231 for (unsigned int i = 0; i < var->num_state_slots; i++) {
232 _mesa_add_state_reference(prog->Parameters,
233 (gl_state_index *) slots[i].tokens);
234 }
235 }
236
237 validate_ir_tree(shader->ir);
238
239 reparent_ir(shader->ir, shader->ir);
240 ralloc_free(mem_ctx);
241
242 do_set_program_inouts(shader->ir, prog, shader->base.Type);
243
244 prog->SamplersUsed = shader->base.active_samplers;
245 _mesa_update_shader_textures_used(shProg, prog);
246
247 _mesa_reference_program(ctx, &shader->base.Program, prog);
248
249 brw_add_texrect_params(prog);
250
251 /* This has to be done last. Any operation that can cause
252 * prog->ParameterValues to get reallocated (e.g., anything that adds a
253 * program constant) has to happen before creating this linkage.
254 */
255 _mesa_associate_uniform_storage(ctx, shProg, prog->Parameters);
256
257 _mesa_reference_program(ctx, &prog, NULL);
258
259 if (ctx->Shader.Flags & GLSL_DUMP) {
260 printf("\n");
261 printf("GLSL IR for linked %s program %d:\n",
262 _mesa_glsl_shader_target_name(shader->base.Type), shProg->Name);
263 _mesa_print_ir(shader->base.ir, NULL);
264 printf("\n");
265 }
266 }
267
268 if (ctx->Shader.Flags & GLSL_DUMP) {
269 for (unsigned i = 0; i < shProg->NumShaders; i++) {
270 const struct gl_shader *sh = shProg->Shaders[i];
271 if (!sh)
272 continue;
273
274 printf("GLSL %s shader %d source for linked program %d:\n",
275 _mesa_glsl_shader_target_name(sh->Type),
276 i,
277 shProg->Name);
278 printf("%s", sh->Source);
279 printf("\n");
280 }
281 }
282
283 if (!brw_shader_precompile(ctx, shProg))
284 return false;
285
286 return true;
287 }
288
289
290 int
291 brw_type_for_base_type(const struct glsl_type *type)
292 {
293 switch (type->base_type) {
294 case GLSL_TYPE_FLOAT:
295 return BRW_REGISTER_TYPE_F;
296 case GLSL_TYPE_INT:
297 case GLSL_TYPE_BOOL:
298 return BRW_REGISTER_TYPE_D;
299 case GLSL_TYPE_UINT:
300 return BRW_REGISTER_TYPE_UD;
301 case GLSL_TYPE_ARRAY:
302 return brw_type_for_base_type(type->fields.array);
303 case GLSL_TYPE_STRUCT:
304 case GLSL_TYPE_SAMPLER:
305 /* These should be overridden with the type of the member when
306 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
307 * way to trip up if we don't.
308 */
309 return BRW_REGISTER_TYPE_UD;
310 case GLSL_TYPE_VOID:
311 case GLSL_TYPE_ERROR:
312 case GLSL_TYPE_INTERFACE:
313 assert(!"not reached");
314 break;
315 }
316
317 return BRW_REGISTER_TYPE_F;
318 }
319
320 uint32_t
321 brw_conditional_for_comparison(unsigned int op)
322 {
323 switch (op) {
324 case ir_binop_less:
325 return BRW_CONDITIONAL_L;
326 case ir_binop_greater:
327 return BRW_CONDITIONAL_G;
328 case ir_binop_lequal:
329 return BRW_CONDITIONAL_LE;
330 case ir_binop_gequal:
331 return BRW_CONDITIONAL_GE;
332 case ir_binop_equal:
333 case ir_binop_all_equal: /* same as equal for scalars */
334 return BRW_CONDITIONAL_Z;
335 case ir_binop_nequal:
336 case ir_binop_any_nequal: /* same as nequal for scalars */
337 return BRW_CONDITIONAL_NZ;
338 default:
339 assert(!"not reached: bad operation for comparison");
340 return BRW_CONDITIONAL_NZ;
341 }
342 }
343
344 uint32_t
345 brw_math_function(enum opcode op)
346 {
347 switch (op) {
348 case SHADER_OPCODE_RCP:
349 return BRW_MATH_FUNCTION_INV;
350 case SHADER_OPCODE_RSQ:
351 return BRW_MATH_FUNCTION_RSQ;
352 case SHADER_OPCODE_SQRT:
353 return BRW_MATH_FUNCTION_SQRT;
354 case SHADER_OPCODE_EXP2:
355 return BRW_MATH_FUNCTION_EXP;
356 case SHADER_OPCODE_LOG2:
357 return BRW_MATH_FUNCTION_LOG;
358 case SHADER_OPCODE_POW:
359 return BRW_MATH_FUNCTION_POW;
360 case SHADER_OPCODE_SIN:
361 return BRW_MATH_FUNCTION_SIN;
362 case SHADER_OPCODE_COS:
363 return BRW_MATH_FUNCTION_COS;
364 case SHADER_OPCODE_INT_QUOTIENT:
365 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
366 case SHADER_OPCODE_INT_REMAINDER:
367 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
368 default:
369 assert(!"not reached: unknown math function");
370 return 0;
371 }
372 }
373
374 uint32_t
375 brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
376 {
377 /* If the driver does not support GL_ARB_gpu_shader5, the offset
378 * must be constant.
379 */
380 assert(offset != NULL || ctx->Extensions.ARB_gpu_shader5);
381
382 if (!offset) return 0; /* nonconstant offset; caller will handle it. */
383
384 signed char offsets[3];
385 for (unsigned i = 0; i < offset->type->vector_elements; i++)
386 offsets[i] = (signed char) offset->value.i[i];
387
388 /* Combine all three offsets into a single unsigned dword:
389 *
390 * bits 11:8 - U Offset (X component)
391 * bits 7:4 - V Offset (Y component)
392 * bits 3:0 - R Offset (Z component)
393 */
394 unsigned offset_bits = 0;
395 for (unsigned i = 0; i < offset->type->vector_elements; i++) {
396 const unsigned shift = 4 * (2 - i);
397 offset_bits |= (offsets[i] << shift) & (0xF << shift);
398 }
399 return offset_bits;
400 }
401
402 const char *
403 brw_instruction_name(enum opcode op)
404 {
405 char *fallback;
406
407 if (op < ARRAY_SIZE(opcode_descs) && opcode_descs[op].name)
408 return opcode_descs[op].name;
409
410 switch (op) {
411 case FS_OPCODE_FB_WRITE:
412 return "fb_write";
413
414 case SHADER_OPCODE_RCP:
415 return "rcp";
416 case SHADER_OPCODE_RSQ:
417 return "rsq";
418 case SHADER_OPCODE_SQRT:
419 return "sqrt";
420 case SHADER_OPCODE_EXP2:
421 return "exp2";
422 case SHADER_OPCODE_LOG2:
423 return "log2";
424 case SHADER_OPCODE_POW:
425 return "pow";
426 case SHADER_OPCODE_INT_QUOTIENT:
427 return "int_quot";
428 case SHADER_OPCODE_INT_REMAINDER:
429 return "int_rem";
430 case SHADER_OPCODE_SIN:
431 return "sin";
432 case SHADER_OPCODE_COS:
433 return "cos";
434
435 case SHADER_OPCODE_TEX:
436 return "tex";
437 case SHADER_OPCODE_TXD:
438 return "txd";
439 case SHADER_OPCODE_TXF:
440 return "txf";
441 case SHADER_OPCODE_TXL:
442 return "txl";
443 case SHADER_OPCODE_TXS:
444 return "txs";
445 case FS_OPCODE_TXB:
446 return "txb";
447 case SHADER_OPCODE_TXF_MS:
448 return "txf_ms";
449 case SHADER_OPCODE_TG4:
450 return "tg4";
451 case SHADER_OPCODE_TG4_OFFSET:
452 return "tg4_offset";
453
454 case FS_OPCODE_DDX:
455 return "ddx";
456 case FS_OPCODE_DDY:
457 return "ddy";
458
459 case FS_OPCODE_PIXEL_X:
460 return "pixel_x";
461 case FS_OPCODE_PIXEL_Y:
462 return "pixel_y";
463
464 case FS_OPCODE_CINTERP:
465 return "cinterp";
466 case FS_OPCODE_LINTERP:
467 return "linterp";
468
469 case FS_OPCODE_SPILL:
470 return "spill";
471 case FS_OPCODE_UNSPILL:
472 return "unspill";
473
474 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
475 return "uniform_pull_const";
476 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
477 return "uniform_pull_const_gen7";
478 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
479 return "varying_pull_const";
480 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
481 return "varying_pull_const_gen7";
482
483 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
484 return "mov_dispatch_to_flags";
485 case FS_OPCODE_DISCARD_JUMP:
486 return "discard_jump";
487
488 case FS_OPCODE_SET_SIMD4X2_OFFSET:
489 return "set_simd4x2_offset";
490
491 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
492 return "pack_half_2x16_split";
493 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
494 return "unpack_half_2x16_split_x";
495 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
496 return "unpack_half_2x16_split_y";
497
498 case FS_OPCODE_PLACEHOLDER_HALT:
499 return "placeholder_halt";
500
501 case VS_OPCODE_URB_WRITE:
502 return "vs_urb_write";
503 case VS_OPCODE_SCRATCH_READ:
504 return "scratch_read";
505 case VS_OPCODE_SCRATCH_WRITE:
506 return "scratch_write";
507 case VS_OPCODE_PULL_CONSTANT_LOAD:
508 return "pull_constant_load";
509 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
510 return "pull_constant_load_gen7";
511 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
512 return "unpack_flags_simd4x2";
513
514 case GS_OPCODE_URB_WRITE:
515 return "gs_urb_write";
516 case GS_OPCODE_THREAD_END:
517 return "gs_thread_end";
518 case GS_OPCODE_SET_WRITE_OFFSET:
519 return "set_write_offset";
520 case GS_OPCODE_SET_VERTEX_COUNT:
521 return "set_vertex_count";
522 case GS_OPCODE_SET_DWORD_2_IMMED:
523 return "set_dword_2_immed";
524 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
525 return "prepare_channel_masks";
526 case GS_OPCODE_SET_CHANNEL_MASKS:
527 return "set_channel_masks";
528
529 default:
530 /* Yes, this leaks. It's in debug code, it should never occur, and if
531 * it does, you should just add the case to the list above.
532 */
533 asprintf(&fallback, "op%d", op);
534 return fallback;
535 }
536 }
537
538 bool
539 backend_instruction::is_tex()
540 {
541 return (opcode == SHADER_OPCODE_TEX ||
542 opcode == FS_OPCODE_TXB ||
543 opcode == SHADER_OPCODE_TXD ||
544 opcode == SHADER_OPCODE_TXF ||
545 opcode == SHADER_OPCODE_TXF_MS ||
546 opcode == SHADER_OPCODE_TXL ||
547 opcode == SHADER_OPCODE_TXS ||
548 opcode == SHADER_OPCODE_LOD ||
549 opcode == SHADER_OPCODE_TG4 ||
550 opcode == SHADER_OPCODE_TG4_OFFSET);
551 }
552
553 bool
554 backend_instruction::is_math()
555 {
556 return (opcode == SHADER_OPCODE_RCP ||
557 opcode == SHADER_OPCODE_RSQ ||
558 opcode == SHADER_OPCODE_SQRT ||
559 opcode == SHADER_OPCODE_EXP2 ||
560 opcode == SHADER_OPCODE_LOG2 ||
561 opcode == SHADER_OPCODE_SIN ||
562 opcode == SHADER_OPCODE_COS ||
563 opcode == SHADER_OPCODE_INT_QUOTIENT ||
564 opcode == SHADER_OPCODE_INT_REMAINDER ||
565 opcode == SHADER_OPCODE_POW);
566 }
567
568 bool
569 backend_instruction::is_control_flow()
570 {
571 switch (opcode) {
572 case BRW_OPCODE_DO:
573 case BRW_OPCODE_WHILE:
574 case BRW_OPCODE_IF:
575 case BRW_OPCODE_ELSE:
576 case BRW_OPCODE_ENDIF:
577 case BRW_OPCODE_BREAK:
578 case BRW_OPCODE_CONTINUE:
579 return true;
580 default:
581 return false;
582 }
583 }
584
585 bool
586 backend_instruction::can_do_source_mods()
587 {
588 switch (opcode) {
589 case BRW_OPCODE_ADDC:
590 case BRW_OPCODE_BFE:
591 case BRW_OPCODE_BFI1:
592 case BRW_OPCODE_BFI2:
593 case BRW_OPCODE_BFREV:
594 case BRW_OPCODE_CBIT:
595 case BRW_OPCODE_FBH:
596 case BRW_OPCODE_FBL:
597 case BRW_OPCODE_SUBB:
598 return false;
599 default:
600 return true;
601 }
602 }
603
604 void
605 backend_visitor::dump_instructions()
606 {
607 int ip = 0;
608 foreach_list(node, &this->instructions) {
609 backend_instruction *inst = (backend_instruction *)node;
610 printf("%d: ", ip++);
611 dump_instruction(inst);
612 }
613 }
614
615
616 /**
617 * Sets up the starting offsets for the groups of binding table entries
618 * commong to all pipeline stages.
619 *
620 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
621 * unused but also make sure that addition of small offsets to them will
622 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
623 */
624 void
625 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
626 {
627 int num_textures = _mesa_fls(prog->SamplersUsed);
628
629 stage_prog_data->binding_table.texture_start = next_binding_table_offset;
630 next_binding_table_offset += num_textures;
631
632 if (shader) {
633 stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
634 next_binding_table_offset += shader->base.NumUniformBlocks;
635 } else {
636 stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
637 }
638
639 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
640 stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
641 next_binding_table_offset++;
642 } else {
643 stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
644 }
645
646 if (prog->UsesGather) {
647 stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
648 next_binding_table_offset += num_textures;
649 } else {
650 stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
651 }
652
653 /* This may or may not be used depending on how the compile goes. */
654 stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
655 next_binding_table_offset++;
656
657 assert(next_binding_table_offset <= BRW_MAX_SURFACES);
658
659 /* prog_data->base.binding_table.size will be set by mark_surface_used. */
660 }