src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/uniforms.h"
  31
  32 extern "C" void
  33 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  34                       unsigned surf_index)
  35 {
  36    assert(surf_index < BRW_MAX_SURFACES);
  37
  38    prog_data->binding_table.size_bytes =
  39       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  40 }
  41
  42 enum brw_reg_type
  43 brw_type_for_base_type(const struct glsl_type *type)
  44 {
  45    switch (type->base_type) {
  46    case GLSL_TYPE_FLOAT:
  47       return BRW_REGISTER_TYPE_F;
  48    case GLSL_TYPE_INT:
  49    case GLSL_TYPE_BOOL:
  50    case GLSL_TYPE_SUBROUTINE:
  51       return BRW_REGISTER_TYPE_D;
  52    case GLSL_TYPE_UINT:
  53       return BRW_REGISTER_TYPE_UD;
  54    case GLSL_TYPE_ARRAY:
  55       return brw_type_for_base_type(type->fields.array);
  56    case GLSL_TYPE_STRUCT:
  57    case GLSL_TYPE_SAMPLER:
  58    case GLSL_TYPE_ATOMIC_UINT:
  59       /* These should be overridden with the type of the member when
  60        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  61        * way to trip up if we don't.
  62        */
  63       return BRW_REGISTER_TYPE_UD;
  64    case GLSL_TYPE_IMAGE:
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_DOUBLE:
  67       return BRW_REGISTER_TYPE_DF;
  68    case GLSL_TYPE_VOID:
  69    case GLSL_TYPE_ERROR:
  70    case GLSL_TYPE_INTERFACE:
  71    case GLSL_TYPE_FUNCTION:
  72    case GLSL_TYPE_UINT64:
  73    case GLSL_TYPE_INT64:
  74       unreachable("not reached");
  75    }
  76
  77    return BRW_REGISTER_TYPE_F;
  78 }
  79
  80 enum brw_conditional_mod
  81 brw_conditional_for_comparison(unsigned int op)
  82 {
  83    switch (op) {
  84    case ir_binop_less:
  85       return BRW_CONDITIONAL_L;
  86    case ir_binop_greater:
  87       return BRW_CONDITIONAL_G;
  88    case ir_binop_lequal:
  89       return BRW_CONDITIONAL_LE;
  90    case ir_binop_gequal:
  91       return BRW_CONDITIONAL_GE;
  92    case ir_binop_equal:
  93    case ir_binop_all_equal: /* same as equal for scalars */
  94       return BRW_CONDITIONAL_Z;
  95    case ir_binop_nequal:
  96    case ir_binop_any_nequal: /* same as nequal for scalars */
  97       return BRW_CONDITIONAL_NZ;
  98    default:
  99       unreachable("not reached: bad operation for comparison");
 100    }
 101 }
 102
 103 uint32_t
 104 brw_math_function(enum opcode op)
 105 {
 106    switch (op) {
 107    case SHADER_OPCODE_RCP:
 108       return BRW_MATH_FUNCTION_INV;
 109    case SHADER_OPCODE_RSQ:
 110       return BRW_MATH_FUNCTION_RSQ;
 111    case SHADER_OPCODE_SQRT:
 112       return BRW_MATH_FUNCTION_SQRT;
 113    case SHADER_OPCODE_EXP2:
 114       return BRW_MATH_FUNCTION_EXP;
 115    case SHADER_OPCODE_LOG2:
 116       return BRW_MATH_FUNCTION_LOG;
 117    case SHADER_OPCODE_POW:
 118       return BRW_MATH_FUNCTION_POW;
 119    case SHADER_OPCODE_SIN:
 120       return BRW_MATH_FUNCTION_SIN;
 121    case SHADER_OPCODE_COS:
 122       return BRW_MATH_FUNCTION_COS;
 123    case SHADER_OPCODE_INT_QUOTIENT:
 124       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 125    case SHADER_OPCODE_INT_REMAINDER:
 126       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 127    default:
 128       unreachable("not reached: unknown math function");
 129    }
 130 }
 131
 132 bool
 133 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 134 {
 135    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 136
 137    /* offset out of bounds; caller will handle it. */
 138    for (unsigned i = 0; i < num_components; i++)
 139       if (offsets[i] > 7 || offsets[i] < -8)
 140          return false;
 141
 142    /* Combine all three offsets into a single unsigned dword:
 143     *
 144     *    bits 11:8 - U Offset (X component)
 145     *    bits  7:4 - V Offset (Y component)
 146     *    bits  3:0 - R Offset (Z component)
 147     */
 148    *offset_bits = 0;
 149    for (unsigned i = 0; i < num_components; i++) {
 150       const unsigned shift = 4 * (2 - i);
 151       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 152    }
 153    return true;
 154 }
 155
 156 const char *
 157 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 158 {
 159    switch (op) {
 160    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 161       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 162        * start of a loop in the IR.
 163        */
 164       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 165          return "do";
 166
 167       assert(brw_opcode_desc(devinfo, op)->name);
 168       return brw_opcode_desc(devinfo, op)->name;
 169    case FS_OPCODE_FB_WRITE:
 170       return "fb_write";
 171    case FS_OPCODE_FB_WRITE_LOGICAL:
 172       return "fb_write_logical";
 173    case FS_OPCODE_REP_FB_WRITE:
 174       return "rep_fb_write";
 175    case FS_OPCODE_FB_READ:
 176       return "fb_read";
 177    case FS_OPCODE_FB_READ_LOGICAL:
 178       return "fb_read_logical";
 179
 180    case SHADER_OPCODE_RCP:
 181       return "rcp";
 182    case SHADER_OPCODE_RSQ:
 183       return "rsq";
 184    case SHADER_OPCODE_SQRT:
 185       return "sqrt";
 186    case SHADER_OPCODE_EXP2:
 187       return "exp2";
 188    case SHADER_OPCODE_LOG2:
 189       return "log2";
 190    case SHADER_OPCODE_POW:
 191       return "pow";
 192    case SHADER_OPCODE_INT_QUOTIENT:
 193       return "int_quot";
 194    case SHADER_OPCODE_INT_REMAINDER:
 195       return "int_rem";
 196    case SHADER_OPCODE_SIN:
 197       return "sin";
 198    case SHADER_OPCODE_COS:
 199       return "cos";
 200
 201    case SHADER_OPCODE_TEX:
 202       return "tex";
 203    case SHADER_OPCODE_TEX_LOGICAL:
 204       return "tex_logical";
 205    case SHADER_OPCODE_TXD:
 206       return "txd";
 207    case SHADER_OPCODE_TXD_LOGICAL:
 208       return "txd_logical";
 209    case SHADER_OPCODE_TXF:
 210       return "txf";
 211    case SHADER_OPCODE_TXF_LOGICAL:
 212       return "txf_logical";
 213    case SHADER_OPCODE_TXF_LZ:
 214       return "txf_lz";
 215    case SHADER_OPCODE_TXL:
 216       return "txl";
 217    case SHADER_OPCODE_TXL_LOGICAL:
 218       return "txl_logical";
 219    case SHADER_OPCODE_TXL_LZ:
 220       return "txl_lz";
 221    case SHADER_OPCODE_TXS:
 222       return "txs";
 223    case SHADER_OPCODE_TXS_LOGICAL:
 224       return "txs_logical";
 225    case FS_OPCODE_TXB:
 226       return "txb";
 227    case FS_OPCODE_TXB_LOGICAL:
 228       return "txb_logical";
 229    case SHADER_OPCODE_TXF_CMS:
 230       return "txf_cms";
 231    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 232       return "txf_cms_logical";
 233    case SHADER_OPCODE_TXF_CMS_W:
 234       return "txf_cms_w";
 235    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 236       return "txf_cms_w_logical";
 237    case SHADER_OPCODE_TXF_UMS:
 238       return "txf_ums";
 239    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 240       return "txf_ums_logical";
 241    case SHADER_OPCODE_TXF_MCS:
 242       return "txf_mcs";
 243    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 244       return "txf_mcs_logical";
 245    case SHADER_OPCODE_LOD:
 246       return "lod";
 247    case SHADER_OPCODE_LOD_LOGICAL:
 248       return "lod_logical";
 249    case SHADER_OPCODE_TG4:
 250       return "tg4";
 251    case SHADER_OPCODE_TG4_LOGICAL:
 252       return "tg4_logical";
 253    case SHADER_OPCODE_TG4_OFFSET:
 254       return "tg4_offset";
 255    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 256       return "tg4_offset_logical";
 257    case SHADER_OPCODE_SAMPLEINFO:
 258       return "sampleinfo";
 259    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 260       return "sampleinfo_logical";
 261
 262    case SHADER_OPCODE_SHADER_TIME_ADD:
 263       return "shader_time_add";
 264
 265    case SHADER_OPCODE_UNTYPED_ATOMIC:
 266       return "untyped_atomic";
 267    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 268       return "untyped_atomic_logical";
 269    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 270       return "untyped_surface_read";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 272       return "untyped_surface_read_logical";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 274       return "untyped_surface_write";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 276       return "untyped_surface_write_logical";
 277    case SHADER_OPCODE_TYPED_ATOMIC:
 278       return "typed_atomic";
 279    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 280       return "typed_atomic_logical";
 281    case SHADER_OPCODE_TYPED_SURFACE_READ:
 282       return "typed_surface_read";
 283    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 284       return "typed_surface_read_logical";
 285    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 286       return "typed_surface_write";
 287    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 288       return "typed_surface_write_logical";
 289    case SHADER_OPCODE_MEMORY_FENCE:
 290       return "memory_fence";
 291
 292    case SHADER_OPCODE_LOAD_PAYLOAD:
 293       return "load_payload";
 294    case FS_OPCODE_PACK:
 295       return "pack";
 296
 297    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 298       return "gen4_scratch_read";
 299    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 300       return "gen4_scratch_write";
 301    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 302       return "gen7_scratch_read";
 303    case SHADER_OPCODE_URB_WRITE_SIMD8:
 304       return "gen8_urb_write_simd8";
 305    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 306       return "gen8_urb_write_simd8_per_slot";
 307    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 308       return "gen8_urb_write_simd8_masked";
 309    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 310       return "gen8_urb_write_simd8_masked_per_slot";
 311    case SHADER_OPCODE_URB_READ_SIMD8:
 312       return "urb_read_simd8";
 313    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 314       return "urb_read_simd8_per_slot";
 315
 316    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 317       return "find_live_channel";
 318    case SHADER_OPCODE_BROADCAST:
 319       return "broadcast";
 320
 321    case VEC4_OPCODE_MOV_BYTES:
 322       return "mov_bytes";
 323    case VEC4_OPCODE_PACK_BYTES:
 324       return "pack_bytes";
 325    case VEC4_OPCODE_UNPACK_UNIFORM:
 326       return "unpack_uniform";
 327    case VEC4_OPCODE_FROM_DOUBLE:
 328       return "double_to_single";
 329    case VEC4_OPCODE_TO_DOUBLE:
 330       return "single_to_double";
 331    case VEC4_OPCODE_PICK_LOW_32BIT:
 332       return "pick_low_32bit";
 333    case VEC4_OPCODE_PICK_HIGH_32BIT:
 334       return "pick_high_32bit";
 335    case VEC4_OPCODE_SET_LOW_32BIT:
 336       return "set_low_32bit";
 337    case VEC4_OPCODE_SET_HIGH_32BIT:
 338       return "set_high_32bit";
 339
 340    case FS_OPCODE_DDX_COARSE:
 341       return "ddx_coarse";
 342    case FS_OPCODE_DDX_FINE:
 343       return "ddx_fine";
 344    case FS_OPCODE_DDY_COARSE:
 345       return "ddy_coarse";
 346    case FS_OPCODE_DDY_FINE:
 347       return "ddy_fine";
 348
 349    case FS_OPCODE_CINTERP:
 350       return "cinterp";
 351    case FS_OPCODE_LINTERP:
 352       return "linterp";
 353
 354    case FS_OPCODE_PIXEL_X:
 355       return "pixel_x";
 356    case FS_OPCODE_PIXEL_Y:
 357       return "pixel_y";
 358
 359    case FS_OPCODE_GET_BUFFER_SIZE:
 360       return "fs_get_buffer_size";
 361
 362    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 363       return "uniform_pull_const";
 364    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 365       return "uniform_pull_const_gen7";
 366    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 367       return "varying_pull_const_gen4";
 368    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 369       return "varying_pull_const_gen7";
 370    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 371       return "varying_pull_const_logical";
 372
 373    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 374       return "mov_dispatch_to_flags";
 375    case FS_OPCODE_DISCARD_JUMP:
 376       return "discard_jump";
 377
 378    case FS_OPCODE_SET_SAMPLE_ID:
 379       return "set_sample_id";
 380
 381    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 382       return "pack_half_2x16_split";
 383    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 384       return "unpack_half_2x16_split_x";
 385    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 386       return "unpack_half_2x16_split_y";
 387
 388    case FS_OPCODE_PLACEHOLDER_HALT:
 389       return "placeholder_halt";
 390
 391    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 392       return "interp_sample";
 393    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 394       return "interp_shared_offset";
 395    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 396       return "interp_per_slot_offset";
 397
 398    case VS_OPCODE_URB_WRITE:
 399       return "vs_urb_write";
 400    case VS_OPCODE_PULL_CONSTANT_LOAD:
 401       return "pull_constant_load";
 402    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 403       return "pull_constant_load_gen7";
 404
 405    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 406       return "set_simd4x2_header_gen9";
 407
 408    case VS_OPCODE_GET_BUFFER_SIZE:
 409       return "vs_get_buffer_size";
 410
 411    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 412       return "unpack_flags_simd4x2";
 413
 414    case GS_OPCODE_URB_WRITE:
 415       return "gs_urb_write";
 416    case GS_OPCODE_URB_WRITE_ALLOCATE:
 417       return "gs_urb_write_allocate";
 418    case GS_OPCODE_THREAD_END:
 419       return "gs_thread_end";
 420    case GS_OPCODE_SET_WRITE_OFFSET:
 421       return "set_write_offset";
 422    case GS_OPCODE_SET_VERTEX_COUNT:
 423       return "set_vertex_count";
 424    case GS_OPCODE_SET_DWORD_2:
 425       return "set_dword_2";
 426    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 427       return "prepare_channel_masks";
 428    case GS_OPCODE_SET_CHANNEL_MASKS:
 429       return "set_channel_masks";
 430    case GS_OPCODE_GET_INSTANCE_ID:
 431       return "get_instance_id";
 432    case GS_OPCODE_FF_SYNC:
 433       return "ff_sync";
 434    case GS_OPCODE_SET_PRIMITIVE_ID:
 435       return "set_primitive_id";
 436    case GS_OPCODE_SVB_WRITE:
 437       return "gs_svb_write";
 438    case GS_OPCODE_SVB_SET_DST_INDEX:
 439       return "gs_svb_set_dst_index";
 440    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 441       return "gs_ff_sync_set_primitives";
 442    case CS_OPCODE_CS_TERMINATE:
 443       return "cs_terminate";
 444    case SHADER_OPCODE_BARRIER:
 445       return "barrier";
 446    case SHADER_OPCODE_MULH:
 447       return "mulh";
 448    case SHADER_OPCODE_MOV_INDIRECT:
 449       return "mov_indirect";
 450
 451    case VEC4_OPCODE_URB_READ:
 452       return "urb_read";
 453    case TCS_OPCODE_GET_INSTANCE_ID:
 454       return "tcs_get_instance_id";
 455    case TCS_OPCODE_URB_WRITE:
 456       return "tcs_urb_write";
 457    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 458       return "tcs_set_input_urb_offsets";
 459    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 460       return "tcs_set_output_urb_offsets";
 461    case TCS_OPCODE_GET_PRIMITIVE_ID:
 462       return "tcs_get_primitive_id";
 463    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 464       return "tcs_create_barrier_header";
 465    case TCS_OPCODE_SRC0_010_IS_ZERO:
 466       return "tcs_src0<0,1,0>_is_zero";
 467    case TCS_OPCODE_RELEASE_INPUT:
 468       return "tcs_release_input";
 469    case TCS_OPCODE_THREAD_END:
 470       return "tcs_thread_end";
 471    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 472       return "tes_create_input_read_header";
 473    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 474       return "tes_add_indirect_urb_offset";
 475    case TES_OPCODE_GET_PRIMITIVE_ID:
 476       return "tes_get_primitive_id";
 477    }
 478
 479    unreachable("not reached");
 480 }
 481
 482 bool
 483 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 484 {
 485    union {
 486       unsigned ud;
 487       int d;
 488       float f;
 489       double df;
 490    } imm, sat_imm = { 0 };
 491
 492    const unsigned size = type_sz(type);
 493
 494    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 495     * irrelevant, so just check the size of the type and copy from/to an
 496     * appropriately sized field.
 497     */
 498    if (size < 8)
 499       imm.ud = reg->ud;
 500    else
 501       imm.df = reg->df;
 502
 503    switch (type) {
 504    case BRW_REGISTER_TYPE_UD:
 505    case BRW_REGISTER_TYPE_D:
 506    case BRW_REGISTER_TYPE_UW:
 507    case BRW_REGISTER_TYPE_W:
 508    case BRW_REGISTER_TYPE_UQ:
 509    case BRW_REGISTER_TYPE_Q:
 510       /* Nothing to do. */
 511       return false;
 512    case BRW_REGISTER_TYPE_F:
 513       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 514       break;
 515    case BRW_REGISTER_TYPE_DF:
 516       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 517       break;
 518    case BRW_REGISTER_TYPE_UB:
 519    case BRW_REGISTER_TYPE_B:
 520       unreachable("no UB/B immediates");
 521    case BRW_REGISTER_TYPE_V:
 522    case BRW_REGISTER_TYPE_UV:
 523    case BRW_REGISTER_TYPE_VF:
 524       unreachable("unimplemented: saturate vector immediate");
 525    case BRW_REGISTER_TYPE_HF:
 526       unreachable("unimplemented: saturate HF immediate");
 527    }
 528
 529    if (size < 8) {
 530       if (imm.ud != sat_imm.ud) {
 531          reg->ud = sat_imm.ud;
 532          return true;
 533       }
 534    } else {
 535       if (imm.df != sat_imm.df) {
 536          reg->df = sat_imm.df;
 537          return true;
 538       }
 539    }
 540    return false;
 541 }
 542
 543 bool
 544 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 545 {
 546    switch (type) {
 547    case BRW_REGISTER_TYPE_D:
 548    case BRW_REGISTER_TYPE_UD:
 549       reg->d = -reg->d;
 550       return true;
 551    case BRW_REGISTER_TYPE_W:
 552    case BRW_REGISTER_TYPE_UW:
 553       reg->d = -(int16_t)reg->ud;
 554       return true;
 555    case BRW_REGISTER_TYPE_F:
 556       reg->f = -reg->f;
 557       return true;
 558    case BRW_REGISTER_TYPE_VF:
 559       reg->ud ^= 0x80808080;
 560       return true;
 561    case BRW_REGISTER_TYPE_DF:
 562       reg->df = -reg->df;
 563       return true;
 564    case BRW_REGISTER_TYPE_UB:
 565    case BRW_REGISTER_TYPE_B:
 566       unreachable("no UB/B immediates");
 567    case BRW_REGISTER_TYPE_UV:
 568    case BRW_REGISTER_TYPE_V:
 569       assert(!"unimplemented: negate UV/V immediate");
 570    case BRW_REGISTER_TYPE_UQ:
 571    case BRW_REGISTER_TYPE_Q:
 572       assert(!"unimplemented: negate UQ/Q immediate");
 573    case BRW_REGISTER_TYPE_HF:
 574       assert(!"unimplemented: negate HF immediate");
 575    }
 576
 577    return false;
 578 }
 579
 580 bool
 581 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 582 {
 583    switch (type) {
 584    case BRW_REGISTER_TYPE_D:
 585       reg->d = abs(reg->d);
 586       return true;
 587    case BRW_REGISTER_TYPE_W:
 588       reg->d = abs((int16_t)reg->ud);
 589       return true;
 590    case BRW_REGISTER_TYPE_F:
 591       reg->f = fabsf(reg->f);
 592       return true;
 593    case BRW_REGISTER_TYPE_DF:
 594       reg->df = fabs(reg->df);
 595       return true;
 596    case BRW_REGISTER_TYPE_VF:
 597       reg->ud &= ~0x80808080;
 598       return true;
 599    case BRW_REGISTER_TYPE_UB:
 600    case BRW_REGISTER_TYPE_B:
 601       unreachable("no UB/B immediates");
 602    case BRW_REGISTER_TYPE_UQ:
 603    case BRW_REGISTER_TYPE_UD:
 604    case BRW_REGISTER_TYPE_UW:
 605    case BRW_REGISTER_TYPE_UV:
 606       /* Presumably the absolute value modifier on an unsigned source is a
 607        * nop, but it would be nice to confirm.
 608        */
 609       assert(!"unimplemented: abs unsigned immediate");
 610    case BRW_REGISTER_TYPE_V:
 611       assert(!"unimplemented: abs V immediate");
 612    case BRW_REGISTER_TYPE_Q:
 613       assert(!"unimplemented: abs Q immediate");
 614    case BRW_REGISTER_TYPE_HF:
 615       assert(!"unimplemented: abs HF immediate");
 616    }
 617
 618    return false;
 619 }
 620
 621 /**
 622  * Get the appropriate atomic op for an image atomic intrinsic.
 623  */
 624 unsigned
 625 get_atomic_counter_op(nir_intrinsic_op op)
 626 {
 627    switch (op) {
 628    case nir_intrinsic_atomic_counter_inc:
 629       return BRW_AOP_INC;
 630    case nir_intrinsic_atomic_counter_dec:
 631       return BRW_AOP_PREDEC;
 632    case nir_intrinsic_atomic_counter_add:
 633       return BRW_AOP_ADD;
 634    case nir_intrinsic_atomic_counter_min:
 635       return BRW_AOP_UMIN;
 636    case nir_intrinsic_atomic_counter_max:
 637       return BRW_AOP_UMAX;
 638    case nir_intrinsic_atomic_counter_and:
 639       return BRW_AOP_AND;
 640    case nir_intrinsic_atomic_counter_or:
 641       return BRW_AOP_OR;
 642    case nir_intrinsic_atomic_counter_xor:
 643       return BRW_AOP_XOR;
 644    case nir_intrinsic_atomic_counter_exchange:
 645       return BRW_AOP_MOV;
 646    case nir_intrinsic_atomic_counter_comp_swap:
 647       return BRW_AOP_CMPWR;
 648    default:
 649       unreachable("Not reachable.");
 650    }
 651 }
 652
 653 backend_shader::backend_shader(const struct brw_compiler *compiler,
 654                                void *log_data,
 655                                void *mem_ctx,
 656                                const nir_shader *shader,
 657                                struct brw_stage_prog_data *stage_prog_data)
 658    : compiler(compiler),
 659      log_data(log_data),
 660      devinfo(compiler->devinfo),
 661      nir(shader),
 662      stage_prog_data(stage_prog_data),
 663      mem_ctx(mem_ctx),
 664      cfg(NULL),
 665      stage(shader->stage)
 666 {
 667    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 668    stage_name = _mesa_shader_stage_to_string(stage);
 669    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 670 }
 671
 672 bool
 673 backend_reg::equals(const backend_reg &r) const
 674 {
 675    return brw_regs_equal(this, &r) && offset == r.offset;
 676 }
 677
 678 bool
 679 backend_reg::is_zero() const
 680 {
 681    if (file != IMM)
 682       return false;
 683
 684    switch (type) {
 685    case BRW_REGISTER_TYPE_F:
 686       return f == 0;
 687    case BRW_REGISTER_TYPE_DF:
 688       return df == 0;
 689    case BRW_REGISTER_TYPE_D:
 690    case BRW_REGISTER_TYPE_UD:
 691       return d == 0;
 692    default:
 693       return false;
 694    }
 695 }
 696
 697 bool
 698 backend_reg::is_one() const
 699 {
 700    if (file != IMM)
 701       return false;
 702
 703    switch (type) {
 704    case BRW_REGISTER_TYPE_F:
 705       return f == 1.0f;
 706    case BRW_REGISTER_TYPE_DF:
 707       return df == 1.0;
 708    case BRW_REGISTER_TYPE_D:
 709    case BRW_REGISTER_TYPE_UD:
 710       return d == 1;
 711    default:
 712       return false;
 713    }
 714 }
 715
 716 bool
 717 backend_reg::is_negative_one() const
 718 {
 719    if (file != IMM)
 720       return false;
 721
 722    switch (type) {
 723    case BRW_REGISTER_TYPE_F:
 724       return f == -1.0;
 725    case BRW_REGISTER_TYPE_DF:
 726       return df == -1.0;
 727    case BRW_REGISTER_TYPE_D:
 728       return d == -1;
 729    default:
 730       return false;
 731    }
 732 }
 733
 734 bool
 735 backend_reg::is_null() const
 736 {
 737    return file == ARF && nr == BRW_ARF_NULL;
 738 }
 739
 740
 741 bool
 742 backend_reg::is_accumulator() const
 743 {
 744    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 745 }
 746
 747 bool
 748 backend_instruction::is_commutative() const
 749 {
 750    switch (opcode) {
 751    case BRW_OPCODE_AND:
 752    case BRW_OPCODE_OR:
 753    case BRW_OPCODE_XOR:
 754    case BRW_OPCODE_ADD:
 755    case BRW_OPCODE_MUL:
 756    case SHADER_OPCODE_MULH:
 757       return true;
 758    case BRW_OPCODE_SEL:
 759       /* MIN and MAX are commutative. */
 760       if (conditional_mod == BRW_CONDITIONAL_GE ||
 761           conditional_mod == BRW_CONDITIONAL_L) {
 762          return true;
 763       }
 764       /* fallthrough */
 765    default:
 766       return false;
 767    }
 768 }
 769
 770 bool
 771 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 772 {
 773    return ::is_3src(devinfo, opcode);
 774 }
 775
 776 bool
 777 backend_instruction::is_tex() const
 778 {
 779    return (opcode == SHADER_OPCODE_TEX ||
 780            opcode == FS_OPCODE_TXB ||
 781            opcode == SHADER_OPCODE_TXD ||
 782            opcode == SHADER_OPCODE_TXF ||
 783            opcode == SHADER_OPCODE_TXF_LZ ||
 784            opcode == SHADER_OPCODE_TXF_CMS ||
 785            opcode == SHADER_OPCODE_TXF_CMS_W ||
 786            opcode == SHADER_OPCODE_TXF_UMS ||
 787            opcode == SHADER_OPCODE_TXF_MCS ||
 788            opcode == SHADER_OPCODE_TXL ||
 789            opcode == SHADER_OPCODE_TXL_LZ ||
 790            opcode == SHADER_OPCODE_TXS ||
 791            opcode == SHADER_OPCODE_LOD ||
 792            opcode == SHADER_OPCODE_TG4 ||
 793            opcode == SHADER_OPCODE_TG4_OFFSET ||
 794            opcode == SHADER_OPCODE_SAMPLEINFO);
 795 }
 796
 797 bool
 798 backend_instruction::is_math() const
 799 {
 800    return (opcode == SHADER_OPCODE_RCP ||
 801            opcode == SHADER_OPCODE_RSQ ||
 802            opcode == SHADER_OPCODE_SQRT ||
 803            opcode == SHADER_OPCODE_EXP2 ||
 804            opcode == SHADER_OPCODE_LOG2 ||
 805            opcode == SHADER_OPCODE_SIN ||
 806            opcode == SHADER_OPCODE_COS ||
 807            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 808            opcode == SHADER_OPCODE_INT_REMAINDER ||
 809            opcode == SHADER_OPCODE_POW);
 810 }
 811
 812 bool
 813 backend_instruction::is_control_flow() const
 814 {
 815    switch (opcode) {
 816    case BRW_OPCODE_DO:
 817    case BRW_OPCODE_WHILE:
 818    case BRW_OPCODE_IF:
 819    case BRW_OPCODE_ELSE:
 820    case BRW_OPCODE_ENDIF:
 821    case BRW_OPCODE_BREAK:
 822    case BRW_OPCODE_CONTINUE:
 823       return true;
 824    default:
 825       return false;
 826    }
 827 }
 828
 829 bool
 830 backend_instruction::can_do_source_mods() const
 831 {
 832    switch (opcode) {
 833    case BRW_OPCODE_ADDC:
 834    case BRW_OPCODE_BFE:
 835    case BRW_OPCODE_BFI1:
 836    case BRW_OPCODE_BFI2:
 837    case BRW_OPCODE_BFREV:
 838    case BRW_OPCODE_CBIT:
 839    case BRW_OPCODE_FBH:
 840    case BRW_OPCODE_FBL:
 841    case BRW_OPCODE_SUBB:
 842       return false;
 843    default:
 844       return true;
 845    }
 846 }
 847
 848 bool
 849 backend_instruction::can_do_saturate() const
 850 {
 851    switch (opcode) {
 852    case BRW_OPCODE_ADD:
 853    case BRW_OPCODE_ASR:
 854    case BRW_OPCODE_AVG:
 855    case BRW_OPCODE_DP2:
 856    case BRW_OPCODE_DP3:
 857    case BRW_OPCODE_DP4:
 858    case BRW_OPCODE_DPH:
 859    case BRW_OPCODE_F16TO32:
 860    case BRW_OPCODE_F32TO16:
 861    case BRW_OPCODE_LINE:
 862    case BRW_OPCODE_LRP:
 863    case BRW_OPCODE_MAC:
 864    case BRW_OPCODE_MAD:
 865    case BRW_OPCODE_MATH:
 866    case BRW_OPCODE_MOV:
 867    case BRW_OPCODE_MUL:
 868    case SHADER_OPCODE_MULH:
 869    case BRW_OPCODE_PLN:
 870    case BRW_OPCODE_RNDD:
 871    case BRW_OPCODE_RNDE:
 872    case BRW_OPCODE_RNDU:
 873    case BRW_OPCODE_RNDZ:
 874    case BRW_OPCODE_SEL:
 875    case BRW_OPCODE_SHL:
 876    case BRW_OPCODE_SHR:
 877    case FS_OPCODE_LINTERP:
 878    case SHADER_OPCODE_COS:
 879    case SHADER_OPCODE_EXP2:
 880    case SHADER_OPCODE_LOG2:
 881    case SHADER_OPCODE_POW:
 882    case SHADER_OPCODE_RCP:
 883    case SHADER_OPCODE_RSQ:
 884    case SHADER_OPCODE_SIN:
 885    case SHADER_OPCODE_SQRT:
 886       return true;
 887    default:
 888       return false;
 889    }
 890 }
 891
 892 bool
 893 backend_instruction::can_do_cmod() const
 894 {
 895    switch (opcode) {
 896    case BRW_OPCODE_ADD:
 897    case BRW_OPCODE_ADDC:
 898    case BRW_OPCODE_AND:
 899    case BRW_OPCODE_ASR:
 900    case BRW_OPCODE_AVG:
 901    case BRW_OPCODE_CMP:
 902    case BRW_OPCODE_CMPN:
 903    case BRW_OPCODE_DP2:
 904    case BRW_OPCODE_DP3:
 905    case BRW_OPCODE_DP4:
 906    case BRW_OPCODE_DPH:
 907    case BRW_OPCODE_F16TO32:
 908    case BRW_OPCODE_F32TO16:
 909    case BRW_OPCODE_FRC:
 910    case BRW_OPCODE_LINE:
 911    case BRW_OPCODE_LRP:
 912    case BRW_OPCODE_LZD:
 913    case BRW_OPCODE_MAC:
 914    case BRW_OPCODE_MACH:
 915    case BRW_OPCODE_MAD:
 916    case BRW_OPCODE_MOV:
 917    case BRW_OPCODE_MUL:
 918    case BRW_OPCODE_NOT:
 919    case BRW_OPCODE_OR:
 920    case BRW_OPCODE_PLN:
 921    case BRW_OPCODE_RNDD:
 922    case BRW_OPCODE_RNDE:
 923    case BRW_OPCODE_RNDU:
 924    case BRW_OPCODE_RNDZ:
 925    case BRW_OPCODE_SAD2:
 926    case BRW_OPCODE_SADA2:
 927    case BRW_OPCODE_SHL:
 928    case BRW_OPCODE_SHR:
 929    case BRW_OPCODE_SUBB:
 930    case BRW_OPCODE_XOR:
 931    case FS_OPCODE_CINTERP:
 932    case FS_OPCODE_LINTERP:
 933       return true;
 934    default:
 935       return false;
 936    }
 937 }
 938
 939 bool
 940 backend_instruction::reads_accumulator_implicitly() const
 941 {
 942    switch (opcode) {
 943    case BRW_OPCODE_MAC:
 944    case BRW_OPCODE_MACH:
 945    case BRW_OPCODE_SADA2:
 946       return true;
 947    default:
 948       return false;
 949    }
 950 }
 951
 952 bool
 953 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 954 {
 955    return writes_accumulator ||
 956           (devinfo->gen < 6 &&
 957            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 958             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 959              opcode != FS_OPCODE_CINTERP)));
 960 }
 961
 962 bool
 963 backend_instruction::has_side_effects() const
 964 {
 965    switch (opcode) {
 966    case SHADER_OPCODE_UNTYPED_ATOMIC:
 967    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 968    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 969    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 970    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 971    case SHADER_OPCODE_TYPED_ATOMIC:
 972    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 973    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 974    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 975    case SHADER_OPCODE_MEMORY_FENCE:
 976    case SHADER_OPCODE_URB_WRITE_SIMD8:
 977    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 978    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 979    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 980    case FS_OPCODE_FB_WRITE:
 981    case FS_OPCODE_FB_WRITE_LOGICAL:
 982    case SHADER_OPCODE_BARRIER:
 983    case TCS_OPCODE_URB_WRITE:
 984    case TCS_OPCODE_RELEASE_INPUT:
 985       return true;
 986    default:
 987       return false;
 988    }
 989 }
 990
 991 bool
 992 backend_instruction::is_volatile() const
 993 {
 994    switch (opcode) {
 995    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 996    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 997    case SHADER_OPCODE_TYPED_SURFACE_READ:
 998    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 999    case SHADER_OPCODE_URB_READ_SIMD8:
1000    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1001    case VEC4_OPCODE_URB_READ:
1002       return true;
1003    default:
1004       return false;
1005    }
1006 }
1007
1008 #ifndef NDEBUG
1009 static bool
1010 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1011 {
1012    bool found = false;
1013    foreach_inst_in_block (backend_instruction, i, block) {
1014       if (inst == i) {
1015          found = true;
1016       }
1017    }
1018    return found;
1019 }
1020 #endif
1021
1022 static void
1023 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1024 {
1025    for (bblock_t *block_iter = start_block->next();
1026         block_iter;
1027         block_iter = block_iter->next()) {
1028       block_iter->start_ip += ip_adjustment;
1029       block_iter->end_ip += ip_adjustment;
1030    }
1031 }
1032
1033 void
1034 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1035 {
1036    assert(this != inst);
1037
1038    if (!this->is_head_sentinel())
1039       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1040
1041    block->end_ip++;
1042
1043    adjust_later_block_ips(block, 1);
1044
1045    exec_node::insert_after(inst);
1046 }
1047
1048 void
1049 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1050 {
1051    assert(this != inst);
1052
1053    if (!this->is_tail_sentinel())
1054       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1055
1056    block->end_ip++;
1057
1058    adjust_later_block_ips(block, 1);
1059
1060    exec_node::insert_before(inst);
1061 }
1062
1063 void
1064 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1065 {
1066    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    unsigned num_inst = list->length();
1069
1070    block->end_ip += num_inst;
1071
1072    adjust_later_block_ips(block, num_inst);
1073
1074    exec_node::insert_before(list);
1075 }
1076
1077 void
1078 backend_instruction::remove(bblock_t *block)
1079 {
1080    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1081
1082    adjust_later_block_ips(block, -1);
1083
1084    if (block->start_ip == block->end_ip) {
1085       block->cfg->remove_block(block);
1086    } else {
1087       block->end_ip--;
1088    }
1089
1090    exec_node::remove();
1091 }
1092
1093 void
1094 backend_shader::dump_instructions()
1095 {
1096    dump_instructions(NULL);
1097 }
1098
1099 void
1100 backend_shader::dump_instructions(const char *name)
1101 {
1102    FILE *file = stderr;
1103    if (name && geteuid() != 0) {
1104       file = fopen(name, "w");
1105       if (!file)
1106          file = stderr;
1107    }
1108
1109    if (cfg) {
1110       int ip = 0;
1111       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1112          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1113             fprintf(file, "%4d: ", ip++);
1114          dump_instruction(inst, file);
1115       }
1116    } else {
1117       int ip = 0;
1118       foreach_in_list(backend_instruction, inst, &instructions) {
1119          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1120             fprintf(file, "%4d: ", ip++);
1121          dump_instruction(inst, file);
1122       }
1123    }
1124
1125    if (file != stderr) {
1126       fclose(file);
1127    }
1128 }
1129
1130 void
1131 backend_shader::calculate_cfg()
1132 {
1133    if (this->cfg)
1134       return;
1135    cfg = new(mem_ctx) cfg_t(&this->instructions);
1136 }
1137
1138 /**
1139  * Sets up the starting offsets for the groups of binding table entries
1140  * commong to all pipeline stages.
1141  *
1142  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1143  * unused but also make sure that addition of small offsets to them will
1144  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1145  */
1146 uint32_t
1147 brw_assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
1148                                         const struct gl_program *prog,
1149                                         struct brw_stage_prog_data *stage_prog_data,
1150                                         uint32_t next_binding_table_offset)
1151 {
1152    int num_textures = util_last_bit(prog->SamplersUsed);
1153
1154    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1155    next_binding_table_offset += num_textures;
1156
1157    if (prog->info.num_ubos) {
1158       assert(prog->info.num_ubos <= BRW_MAX_UBO);
1159       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1160       next_binding_table_offset += prog->info.num_ubos;
1161    } else {
1162       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1163    }
1164
1165    if (prog->info.num_ssbos) {
1166       assert(prog->info.num_ssbos <= BRW_MAX_SSBO);
1167       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1168       next_binding_table_offset += prog->info.num_ssbos;
1169    } else {
1170       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1171    }
1172
1173    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1174       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1175       next_binding_table_offset++;
1176    } else {
1177       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1178    }
1179
1180    if (prog->nir->info->uses_texture_gather) {
1181       if (devinfo->gen >= 8) {
1182          stage_prog_data->binding_table.gather_texture_start =
1183             stage_prog_data->binding_table.texture_start;
1184       } else {
1185          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1186          next_binding_table_offset += num_textures;
1187       }
1188    } else {
1189       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1190    }
1191
1192    if (prog->info.num_abos) {
1193       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1194       next_binding_table_offset += prog->info.num_abos;
1195    } else {
1196       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1197    }
1198
1199    if (prog->info.num_images) {
1200       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1201       next_binding_table_offset += prog->info.num_images;
1202    } else {
1203       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1204    }
1205
1206    /* This may or may not be used depending on how the compile goes. */
1207    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1208    next_binding_table_offset++;
1209
1210    /* Plane 0 is just the regular texture section */
1211    stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
1212
1213    stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
1214    next_binding_table_offset += num_textures;
1215
1216    stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
1217    next_binding_table_offset += num_textures;
1218
1219    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1220
1221    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1222    return next_binding_table_offset;
1223 }
1224
1225 static void
1226 setup_vec4_uniform_value(const gl_constant_value **params,
1227                          const gl_constant_value *values,
1228                          unsigned n)
1229 {
1230    static const gl_constant_value zero = { 0 };
1231
1232    for (unsigned i = 0; i < n; ++i)
1233       params[i] = &values[i];
1234
1235    for (unsigned i = n; i < 4; ++i)
1236       params[i] = &zero;
1237 }
1238
1239 void
1240 brw_setup_image_uniform_values(gl_shader_stage stage,
1241                                struct brw_stage_prog_data *stage_prog_data,
1242                                unsigned param_start_index,
1243                                const gl_uniform_storage *storage)
1244 {
1245    const gl_constant_value **param =
1246       &stage_prog_data->param[param_start_index];
1247
1248    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1249       const unsigned image_idx = storage->opaque[stage].index + i;
1250       const brw_image_param *image_param =
1251          &stage_prog_data->image_param[image_idx];
1252
1253       /* Upload the brw_image_param structure.  The order is expected to match
1254        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1255        */
1256       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1257          (const gl_constant_value *)&image_param->surface_idx, 1);
1258       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1259          (const gl_constant_value *)image_param->offset, 2);
1260       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1261          (const gl_constant_value *)image_param->size, 3);
1262       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1263          (const gl_constant_value *)image_param->stride, 4);
1264       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1265          (const gl_constant_value *)image_param->tiling, 3);
1266       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1267          (const gl_constant_value *)image_param->swizzling, 2);
1268       param += BRW_IMAGE_PARAM_SIZE;
1269
1270       brw_mark_surface_used(
1271          stage_prog_data,
1272          stage_prog_data->binding_table.image_start + image_idx);
1273    }
1274 }
1275
1276 /**
1277  * Decide which set of clip planes should be used when clipping via
1278  * gl_Position or gl_ClipVertex.
1279  */
1280 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1281 {
1282    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1283       /* There is currently a GLSL vertex shader, so clip according to GLSL
1284        * rules, which means compare gl_ClipVertex (or gl_Position, if
1285        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1286        * that were stored in EyeUserPlane at the time the clip planes were
1287        * specified.
1288        */
1289       return ctx->Transform.EyeUserPlane;
1290    } else {
1291       /* Either we are using fixed function or an ARB vertex program.  In
1292        * either case the clip planes are going to be compared against
1293        * gl_Position (which is in clip coordinates) so we have to clip using
1294        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1295        * core.
1296        */
1297       return ctx->Transform._ClipUserPlane;
1298    }
1299 }
1300
1301 extern "C" const unsigned *
1302 brw_compile_tes(const struct brw_compiler *compiler,
1303                 void *log_data,
1304                 void *mem_ctx,
1305                 const struct brw_tes_prog_key *key,
1306                 const struct brw_vue_map *input_vue_map,
1307                 struct brw_tes_prog_data *prog_data,
1308                 const nir_shader *src_shader,
1309                 struct gl_program *prog,
1310                 int shader_time_index,
1311                 unsigned *final_assembly_size,
1312                 char **error_str)
1313 {
1314    const struct gen_device_info *devinfo = compiler->devinfo;
1315    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1316
1317    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1318    nir->info->inputs_read = key->inputs_read;
1319    nir->info->patch_inputs_read = key->patch_inputs_read;
1320
1321    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1322    brw_nir_lower_tes_inputs(nir, input_vue_map);
1323    brw_nir_lower_vue_outputs(nir, is_scalar);
1324    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1325
1326    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1327                        nir->info->outputs_written,
1328                        nir->info->separate_shader);
1329
1330    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1331
1332    assert(output_size_bytes >= 1);
1333    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1334       if (error_str)
1335          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1336       return NULL;
1337    }
1338
1339    prog_data->base.clip_distance_mask =
1340       ((1 << nir->info->clip_distance_array_size) - 1);
1341    prog_data->base.cull_distance_mask =
1342       ((1 << nir->info->cull_distance_array_size) - 1) <<
1343       nir->info->clip_distance_array_size;
1344
1345    /* URB entry sizes are stored as a multiple of 64 bytes. */
1346    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1347    prog_data->base.urb_read_length = 0;
1348
1349    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1350    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1351                  TESS_SPACING_FRACTIONAL_ODD - 1);
1352    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1353                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1354
1355    prog_data->partitioning =
1356       (enum brw_tess_partitioning) (nir->info->tess.spacing - 1);
1357
1358    switch (nir->info->tess.primitive_mode) {
1359    case GL_QUADS:
1360       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1361       break;
1362    case GL_TRIANGLES:
1363       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1364       break;
1365    case GL_ISOLINES:
1366       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1367       break;
1368    default:
1369       unreachable("invalid domain shader primitive mode");
1370    }
1371
1372    if (nir->info->tess.point_mode) {
1373       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1374    } else if (nir->info->tess.primitive_mode == GL_ISOLINES) {
1375       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1376    } else {
1377       /* Hardware winding order is backwards from OpenGL */
1378       prog_data->output_topology =
1379          nir->info->tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1380                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1381    }
1382
1383    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1384       fprintf(stderr, "TES Input ");
1385       brw_print_vue_map(stderr, input_vue_map);
1386       fprintf(stderr, "TES Output ");
1387       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1388    }
1389
1390    if (is_scalar) {
1391       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1392                    &prog_data->base.base, NULL, nir, 8,
1393                    shader_time_index, input_vue_map);
1394       if (!v.run_tes()) {
1395          if (error_str)
1396             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1397          return NULL;
1398       }
1399
1400       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1401       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1402
1403       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1404                      &prog_data->base.base, v.promoted_constants, false,
1405                      MESA_SHADER_TESS_EVAL);
1406       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1407          g.enable_debug(ralloc_asprintf(mem_ctx,
1408                                         "%s tessellation evaluation shader %s",
1409                                         nir->info->label ? nir->info->label
1410                                                         : "unnamed",
1411                                         nir->info->name));
1412       }
1413
1414       g.generate_code(v.cfg, 8);
1415
1416       return g.get_assembly(final_assembly_size);
1417    } else {
1418       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1419                               nir, mem_ctx, shader_time_index);
1420       if (!v.run()) {
1421          if (error_str)
1422             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1423          return NULL;
1424       }
1425
1426       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1427          v.dump_instructions();
1428
1429       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1430                                         &prog_data->base, v.cfg,
1431                                         final_assembly_size);
1432    }
1433 }